Topic

Voltage Mode Control of SMPS

Subject
Switched Mode & Resonant Converters. (EE6308D)

Instructor
Sandeep J.
Adhoc Faculty
Department of Electrical Engineering
National Institute of Technology Calicut
Introduction
• Consider the negative feedback loop for a typical DC-DC converter –
compensator or error amplifier and modulator are the major components.
• For small, slow variations in output voltage, the loop is stable. Variations in
output voltage may be caused by:
• Change in input voltage.
• Change in load current.
• Such variations in output voltage will be acquired by the sensor circuit and is
fed to the compensator.
• Compensator would bring corresponding changes in the modulating voltages
such that the width of the pulse applied to the switching device is adjusted to
maintain the output voltage at a constant value.
• This negative feedback system is stable for low frequencies.
Introduction (contd..)
• What happens in the presence of low level noise voltages or voltage transients in
the feedback system?
• If Fourier series of such imperfections in the loop is constructed, we will get a
continuous spectrum.
• All the frequency components of the spectrum will undergo gain changes and phase
shifts in the output filter, error amplifier and the PWM modulator.
• If any such changes results in positive feedback instead of negative feedback,
oscillations creep into the system response.
• Assume that a signal of some random frequency is injected into the loop at the
feedback point of the error amplifier.
• This would modify the output after a series of gain and phase changes caused by
the elements of the loop.
• If the modified output is exactly in phase with the injected signal, then the output
will oscillate at a frequency equal to the frequency of the injected signal.
Gain Characteristics of LC Filter
• All topologies that have an output LC filter is being discussed – buck derived
converters.
• The frequency response of the output filter is important as it determines how
the frequency response of the error amplifier must be shaped for satisfying the
stability of a system.
• The gain characteristics of output LC filter without considering the ESR of the
capacitor at different load condition is discussed initially.
• For detailed discussion, the critically damped condition of the output filter is
considered.
• It can be assumed that if the circuit is stable for a load corresponding to
critically damped condition, then the circuit is stable for other load conditions
also.
Gain Characteristics of LC Filter (contd..)
• The gain characteristics of output LC filter without the capacitor ESR is given
below:
Gain Characteristics of LC Filter (contd..)
• It is seen that the gain is 0dB at DC and low frequencies up to the corner
frequency. During this phase, the capacitor impedance is much greater that the
inductor impedance.
• Beyond the corner frequency, the impedance of the capacitor decreases and that
of the inductor increases, both at a rate of 20dB/decade – the gain slope falls at a
rate of 40dB/decade.
• Practically, the capacitors have an internal resistance (ESR) in series with their
output leads.
• The gain characteristics of the output filter gets modified as a result of the
presence of ESR.
• Beyond the corner frequency, in the lower frequency range where the capacitor
impedance is much greater than the ESR, the gain still falls at a rate of
40dB/decade.
Gain Characteristics of LC Filter (contd..)
• At higher frequencies, where the capacitor impedance is less than the ESR, the
circuit is an RL circuit rather than an LC circuit.
Gain Characteristics of LC Filter (contd..)
• At higher frequencies, the inductive impedance increase at a rate of
20dB/decade whereas that of the ESR remains a constant – the gain falls at
20dB/decade.
• The change from a slope of 40dB/decade to a slope of 20dB/decade occurs at a
frequency where the capacitor impedance equals the ESR.
• The slope changes considered here are asymptotic. Practically, they will be
much more smoother.
Total Gain Characteristics
• Apart from the gain characteristics of LC filter, two more gain characteristics
need to be analyzed – the pulse width modulator gain and the sampling
network gain.
• The gain from error amplifier output to the average voltage at the input of the
output filter inductor is defined as the pulse width modulator gain – includes
the converter gain.
• This gain depends on the output voltage expression of the converter, but is
independent of the frequency (a constant).
• Conventionally, potential divider circuits are the simplest sensing circuit used in
SMPS circuit.
• The ratio of resistors in potential divider circuit forms the gain for sampling
network – frequency independent.
Total Gain Characteristics (contd..)
• The situation with sensor circuits that employs hall effect voltage sensors is
different, since the gain defined for such circuits are frequency dependent.
• The total gain characteristic is defined by the sum of output LC filter gain, pulse
width modulator gain and the sampling network gain.
• Since pulse width modulator gain and sampling network gain are constants, the
gain characteristics of LC filter is shifted in positive gain direction.
• From DC to the corner frequency of the LC filter, the total gain is given by the
sum of pulse width modulator gain and the sampling network gain.
• At the corner frequency, the gain starts to drop with a slope of 40dB/decade
until a frequency for which the capacitor impedance equals ESR.
• Further, the gain drops with a slope of 20dB/decade.
Stability Criteria
• The first criterion for a stable loop is that at the frequency where the total open
loop gain is unity, the total open loop phase shift of all elements must be less
than 360o. The amount by which the total phase shift is less than 360o is called
the Phase Margin.
• The second criterion for the stable circuit is that to prevent the rapid changes of
phase shift with frequency characteristics of a circuit with a -40dB/decade gain
slope, the slope of the open loop gain – frequency curve of the entire circuit as
it passes through the cross over frequency should be -20dB/decade.
• Maintain a required phase margin for stable loop operation (normally, between
45o to 60o).
Shaping Frequency Response of Error Amplifier
• For the first stability criterion, the phase margin is taken to be 45 degree.
• Choose the cross over frequency at which the total open loop gain is desired to
be 0dB. Select a value for the gain of error amplifier, such that the total open
loop gain is 0dB at the cross over frequency.
• Design the gain slope of error amplifier, such that the total open loop gain falls
at a slope of 20dB/decade at the cross over frequency.
• Fine tune the gain-frequency characteristics of error amplifier to achieve the
desired phase margin.
• Cross over frequency can be chosen to be 1/5th to 1/10th the switching
frequency.
• Assume fco=1/5th the switching frequency.
• ESR in the capacitor would cause a change
in the falling slope of the gain at fesr.
• In most cases, fesr is less than fco and the
gain will already fall at rate of
20dB/decade.
• To force the total system cross over
frequency to be the desired fco, gain of the
error amplifier at fco is chosen to be equal
to the negative of the total gain of the
plant.
• If the plant gain is falling at 20dB/decade
at fco, then the gain of error amplifier is
made horizontal at fco to satisfy the
second stability criterion.
• Error amplifier with such a gain
characteristic can be realized using opamp
 • Gain of opamp circuit is Z2/Z1.
• The total open loop gain is the sum of
the gain of error amplifier and gain of
the plant.
• At low frequencies, a high total open
gain is expected.
• If error amplifier gain remains constant down to DC, then the total open loop gain
is small – at some frequency less than fco, the error amplifier should be permitted
to have a high gain value.
• This can be attained by a series RC circuit as Z2 – at low frequencies, Z2 is pre-
dominantly capacitive and as at high frequencies Z2 is resistive.
• If Z1 is a resistor R1, then at low frequencies the gain is given by Xc1/R1. The gain
rises at a rate of 20dB/decade.
• As the frequency increases, at a value of fz=1/2πR2C1, the gain of error amplifier
would become horizontal.
• As we move towards right of fco, if the error amplifier gain is permitted to remain horizontal,
then the relative gain at high frequency is large – noise will be picked up and transmitted with
large amplitudes.
• To reduce the gain at high frequencies, a capacitor C2 is placed across Z2 that comprise of R2
and C1.
• Since frequency is high, C1 is already out of the picture. Xc2 will be smaller compared to R2 and
therefore R2 will be out of the circuit.
• Thus at higher frequencies, the effective gain of error amplifier is given by Xc2/R1.
• As the frequency increases, at a value of fp=1/2πC2R2, the gain of the error amplifier would
start to fall at a rate of 20dB/decade (total gain falls at the rate of 40dB/decade).
• fp & fz are chosen such that fco/fz=fp/fco.
• Phase margin improves if fp & fz are kept farther apart.
• Low value of fz would fail the requirement of high gain at low frequencies.
• Large value of fp would fail the requirement of low gain at high frequencies.
• With proper pole and zero placement, this selection of frequencies can be made properly.
Error Amplifier Transfer Function
• Impedances Z1 and Z2 are expressed in terms of the complex variable s=jω.
• The impedance Z2 consists of a capacitor C2 in parallel with the series combination of
resistor R2 and capacitor C1.
Z1( s )  R1
1 
Z 2( s )  sC 2

R2  1
sC1
R2  1 1
sC1 sC 2
Z 2( s )
Gea ( s ) 
Z1( s )
1  sz1 1  sz 2 1  sz3 
Gea ( s ) 
sp0 1  sp1 1  sp2 1  sp3 
• z and p values are given by RC products and they represent frequencies – zero frequency and
pole frequency.
• Pole frequency, fp0=1/2πR0C0 corresponds to the pole at the origin.
 • Go to 0dB at frequency corresponding to the
pole at the origin fp0.
• At fp0, draw a line backward in frequency with a
slope of 20dB/decade.
• On this line, at a frequency fz=1/2πR2C1, the
slope of the gain curve turns horizontal. Extend
the horizontal line indefinitely.

• At a higher frequency fp=1/2πR2C2, there exists a pole and therefore gain falls at a rate of
20dB/decade.
• The horizontal part of the gain is given by R2/R1 which is made equal in magnitude and
opposite in sign with the plant gain at cross over frequency.
• Thus an error amplifier gain curve having a single pole at the origin, a single zero and a
single pole can have a desired shape as shown in the figure above.
• Pole and zero frequencies are selected to yield the desired phase margin.
 Z2 • The transfer function derived is
Gea ( s ) 
Z1 commonly referred to as type – II


R2  1  1
sC1 sC 2
amplifier.

R1R 2  1  • A type – II error amplifier can be

1 employed when the capacitor has an
sC1 sC 2
1  sR 2C1 ESR such that fco lies on a -20dB/decade
 slope of the gain curve.
sR1(C1  C 2)(1  sR 2C1C 2 )
(C1  C 2) • Frequency corresponding to the pole at
1  sR 2C1 the origin is fp0=1/2πR1(C1+C2).
C1  C 2  Gea ( s ) 
sR1(C1  C 2)(1  sR 2C 2)
• The zero frequency is given by fz=1/2πR2C1 and the pole frequency is fp=1/2πR2C2.
• Now the problem of designing error amplifier has reduced to the selection of proper pole
and zero frequencies.
• Note that, a zero in the left half of the s-plane would result in a phase lead and a pole in the
left half of the s-plane would result in phase lag.
• fco/fz=fp/fco=K
• The phase lead at a frequency f due to a zero at frequency fz is given by . At fco, .
• The phase lag at a frequency f due to a zero at frequency fp is given by . At fco, .
• The total phase shift at fco is the sum of these two angles.
• In addition, there is a phase shift due to the pole at the origin which is equal to
a phase lag of 90 degrees.
• The error amplifier being considered is an inverting amplifier and therefore a
phase lag of 180 degrees is generated.
• In other words, at low frequencies the circuit is just an integrator with resistive
input and capacitive feedback.

1
lag  270o  tan 1 K  tan 1
K
Transconductance Error Amplifier
• Transconductance error amplifiers uses Operational Transconductance
Amplifiers (OTA) as their building block.
• OTAs are versatile building blocks that intrinsically offer wide bandwidth for
many types of amplifiers. The OTA, or voltage-controlled current source, can be
viewed as an ideal transistor.
• Transconductance gm is the change in output current for unit change in input
voltage .
• For a shunt impedance Zo at the output node, .
• Gain, .
• Gain characteristics of a type – II error amplifier can be
achieved using an OTA using the structure shown
alongside.
• At low frequency, XC1 is much greater than R1, thereby
making C1 & C2 parallel to any internal capacitance of OTA.
• Due to the paralleling effect, there is a shift in the pole to a lower frequency
with reduced gain. At this frequency, due to the effect of pole located, the gain
falls at a rate of 20dB/decade.
• At a frequency of 1/2πR1C1, where XC1=R1, there exists a zero and therefore the
gain becomes horizontal with a magnitude of gmR1.
• At a frequency of 1/2πR1C2, where XC2=R1, there exists a pole and the gain starts
to fall at a rate of 20dB/decade.
Voltage Mode Control Circuitry
Voltage Mode Control Circuitry (contd..)
• A sawtooth oscillator generates sawtooth waveform of required switching
frequency – T=RtCt.
• An error amplifier compares a fraction of the output voltage with the reference
voltage to generate the modulating signal.
• PWM voltage comparator generates the pulse required for operating the
converter by comparing the modulating signal with the sawtooth waveform.
• The fraction of the output voltage is fed to the inverting terminal of the error
amplifier so that as the output voltage increases, the error amplifier output
decreases.
• The current limit amplifier operates only to shutdown the supply when
maximum current limit is exceeded.
SG3525/UC3525
SG3525/UC3525 (contd..)
• Pins 1 (Inverting Input) and 2 (Non Inverting Input) are the inputs to the on-board
error amplifier.
• When voltage on the Inverting Input (pin 1) is greater than voltage on the Non-Inverting
Input (pin 2), duty cycle is decreased.
• When voltage on the Non-Inverting Input (pin 2) is greater than voltage on the Inverting
Input (pin 1), duty cycle is increased.
• The frequency of PWM is dependent on the timing capacitance and the timing
resistance. The timing capacitor (CT) is connected between pin 5 and ground. The
timing resistor (RT) is connected between pin 6 and ground. The resistance
between pins 5 and 7 (RD) determines the 1dead time.
f 
CT 0.7 RT  3RD 

• There is a flip-flop before the driver stage, due to which the output signals will
have frequencies half that of the oscillator frequency that is calculated using the
above formula.
SG3525/UC3525 (contd..)
• A capacitance connected between pin 8 and ground provides the soft-start
functionality. The larger the capacitance, the larger the soft-start time.
• Pin 16 is the output from the voltage reference section. SG3525 contains an
internal voltage reference module rated at +5.1V that is trimmed to provide a
±1% accuracy - used to provide a reference voltage to the error amplifier for
setting the feedback reference voltage.
• Pin 15 is VCC – the supply voltage to the SG3525 that makes it run. VCC must lie
within the range 8V to 35V - an under-voltage lockout circuit that prevents
operation when VCC is below 8V.
• Pin 13 is VC – the supply voltage to the SG3525 driver stage. It is connected to
the collectors of the transistors in the output totem-pole stage.
• Pin 12 is the ground connection and should be connected to the circuit ground.
It must share a common ground with the device it drives.
SG3525/UC3525 (contd..)
• Pins 11 and 14 are the outputs from which the drive signals are to be taken.
When driving MOSFETs in a bridge configuration, high-low side drivers or gate-
drive transformers must be used as the SG3525 is designed only for low-side
drive.
• Pin 10 is shutdown. When this pin is low, PWM is enabled. When this pin is
high, the PWM latch is immediately set. This provides the fastest turn-off signal
to the outputs. An alternative method of shutting down the SG3525 is to pull
either pin 8 or pin 9 low.
• This pin should not be left floating as it could pick up noise and cause problems.
So, this pin is usually held low with a pull-down resistor.
• Pin 9 is compensation. It may be used in conjunction with pin 1 to provide
feedback compensation.
Thank You