Lecture 2
Lecture 2
Lecture 2
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 1
What is this chapter about?
Introduce Basic Design for Testability
(DFT) Techniques
Focus on Widely Used or Emerging DFT
Architectures
IllustrateBasic Test Architectures,
Low-Power Test Architectures, and
At-Speed Test Architectures
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 2
Digital Test Architectures
Introduction
Scan Design
Logic Built-In Self-Test
Test Compression
Random-Access Scan Design
Concluding Remarks
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 3
Introduction
Fault
At-Speed Test Low-
Logic Tolerance
Scan Delay Compre- Power
BIST Defect and
Testing ssion Testing
Tolerance
Hello
Evolution of DFT advances in testing digital circuits
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 4
Introduction
Scan Design
Replace all selected storage elements with scan cells
Connect scan cells into multiple shift registers (scan chains)
Become inefficient to test deep submicron or nanometer
VLSI
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 5
Introduction
Test Compression
A supplemental DFT technique to scan
Can reduce test data volume and test application time
Add some additional on-chip hardware
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 6
Scan Design
Widely used structured DFT architecture
Replace all selected storage elements with scan cells
Connect scan cells into scan chains
Operated in three modes:
Normal mode
– All test signals are turned off.
– The scan design operates in the circuit’s original functional
configuration.
Shift mode
– to shift data into and out of the scan cells
Capture mode
– to capture test response into scan cells
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 7
Scan Architectures
X1 Y1
DI 0 X2 Combinational logic
D Q Q/SO Y2
SI 1 X3
FF1 FF2 FF3
SE CK
D Q D Q D Q
Muxed-D Scan Cell CK . .
The multiplexer uses a scan Sequential circuit example
enable (SE) to select
between the data input (DI)
and the scan input (SI).
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Scan Architectures
X1 Y1 Replace FF1, FF2 and
PI X2 PO FF3 with SFF1, SFF2 and
X3 Combinational logic Y2
SFF3.
PPI PPO
In shift mode, SE is set to
1, the scan cells operate
as a single scan chain.
SFF1 SFF2 SFF3
In capture mode, SE is set
SI
DI
SI Q . DI
SI Q . DI
SI Q . SO
to 0, scan cells are used to
capture the test response
SE SE SE
from the combinational
SE
CK
. . . . logic.
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 9
Scan Architectures
Input selection is
conducted using two
DI independent clocks, data
Q/SO
SI clock DCK and shift
clock SCK.
DCK SCK
Clocked-Scan Cell
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 10
Scan Architectures
X1 Y1 DCK and SCK are
PI X2 PO used for
X3 Combinational logic Y2
distinguishing shift
PPI PPO and capture
operations; while SE
is used to switch the
shift and capture
SFF1 SFF2 SFF3 operations in muxed-
D scan design.
SI
DI
SI Q . DI
SI Q . DI
SI Q . SO
DCK SCK DCK SCK DCK SCK
DCK
SCK
. . . .
Clocked-Scan Design
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 11
Scan Architectures
SRL can be used as an LSSD
D . . .
L1
SRL
+L1
scan cell. This scan cell
contains two latches, a
C . master two-port D latch L1
and a slave D latch L2.
I . .
L2
+L2 Clocks C, A, and B are used
to select between D and +L1
A . . and +L2.
B
Level-Sensitive Scan Design
(LSSD) can be implemented
Polarity–hold shift register latch (SRL) using a single-latch design or
a double-latch design.
LSSD Scan Cell
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Scan Architectures
X1 X3
Combinational logic 1 Combinational logic 2 Y2
The system clocks
X2 Y1 C1 and C2 should
be applied in a
nonoverlapping
SRL1 SRL2 SRL3 fashion.
D D D
SI I +L2 I +L2 I +L2 SO
C C C
A +L1 A +L1 A +L1
B B B
C1 .. ..
A
B .
C2
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Scan Architectures
X1 During the shift
Y1 operation, clocks A and
X2 Combinational logic
X3 Y2 B are applied in a
nonoverlapping
SRL1 SRL2 SRL3 manner, and the scan
cells, SRL1 ~ SRL3, form
SI
D
I +L2 . D
I +L2 . D
I +L2 . a single scan chain from
SO SI to SO.
C C C
A +L1 A +L1 A +L1
B B B During the capture
C1 .. .. operation, clocks C1and
C2are applied in a non-
A
C2 or B . . overlapping manner to
load the
LSSD double-latch design test response from the
combinational logic
into the scan cells.
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Scan Architectures
Enhanced-Scan Design
An alternative at-speed scan design for testing
delay faults; testing of a delay fault requires a pair
of test vectors in an at-speed fashion.
Enhanced-scan cell can store two bits of data;
achieved by adding a D latch to a muxed-D scan
cell or clocked-scan cell.
Disadvantages:
– Higher hardware overhead
– May activate many false paths causing an over-test
problem
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The first test vector V1 is
shifted into SFF1 ~ SFFs
Scan Architectures and then stored into the
additional latches (LA1 ~
X1 Y1 LAs) when the UPDATE
X2
.. Combinational logic .. Y2 signal is set to 1.
Xn
. . Ym Next, the second test vector
LA1 LA2 LAs V2 is shifted into the scan
D D D
cells while the UPDATE
UPDATE . C
Q
C
Q
… C
Q signal is set to 0, in order to
preserve the V1 value in the
SFF1
. SFF2 SFFs
latches (LA1 ~ LAs).
Once the second vector V2
SDI
SE .
DI
SI Q
SE
. DI
SI Q
SE
. …
DI
SI Q
SE
is shifted in, the UPDATE
signal is applied, in order to
CK . …
… . .
change V1 to V2 while
capturing the output
response at-speed into the
Enhanced-Scan Design scan cells by applying CK
after exactly one clock
cycle.
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Low-Power Scan Architectures
Serial Scan Design
Advantage:
– Low routing overhead
Disadvantages:
– Scan cells cannot be controlled or observed without affecting
□ in the same scan chain
the values of other scan cells
– High switching activities during shift and capture can cause
excessive shift (or test) power dissipation
Low-Power Scan Design
Test power is related to dynamic power, and is proportional
to VDD2f
– VDD is the supply voltage
– f is the switching frequency of the circuit node under test
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Example Low-Power Scan Architectures
Reduced-Voltage Low-Power Scan Design
Reduce the supply voltage
Reduced-Frequency Low-Power Scan Design
Slow down the shift clock frequency but increase test
application time
Multi-Phase Low-Power Scan
□ Design
Split the shift clock into a number of nonoverlapping clock
phases but increase routing overhead and complexity
during clock tree synthesis
Bandwidth-Matching Low-Power Scan Design
Use pairs of serial-in/parallel-out shift register and parallel-
in/serial-out shift register for bandwidth matching
Hybrid Low-Power Scan Design
Combine any of the above-mentioned low-power scan
designs
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Multi-Phase Low-Power Scan Design
X1 Y1 The clock CK is split into
PI X2 PO three clock phases CK1,
X3 Combinational logic Y2
CK2, and CK3.
PPI PPO
Using this scheme, a 3X
reduction in shift power
□ can be achieved,
assuming each clock
SFF1 SFF2 SFF3 drives an equal number of
scan cells.
SI
DI
SI Q . DI
SI Q . DI
SI Q . SO
SE SE SE
SE
CK1
. .
CK2
CK3
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 19
Bandwidth-Matching Low-Power Scan Design
SI1 SIm
Each scan chain is
... split into 4 sub-scan
.
ck1
Clock
chains with the SI and
TDDM Controller SO ports of each 4
Full-Scan
Circuit
s10 s11 s12 s13 ... sm0 sm1 sm2 sm3 sub-scan chains
connected to a serial-
... ck2 in/parallel-out shift
□ register and a parallel-
t10 t11 t12 t13 . . . tm0 tm1 tm2 tm3 in/serial-out shift
register, respectively.
TDM
...
SO1 SOm
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At-Speed Scan Architectures
Synchronous Design
A scan design if the active edges of all
capture clocks controlling the clock
domains can be aligned
□ precisely or
triggered simultaneously
Asynchronous Design
A scan design if not synchronous
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At-Speed Scan Architectures
Two basic schemes for test multiple clock domain at-speed
Skewed-load (Launch-on-shift)
– Use the last shift clock pulse followed immediately by a capture
clock pulse to launch the transition and capture the output
response
Double-capture (Launch-on-capture or Broad-side)
– Use two consecutive capture clock pulses to launch the
transition and capture the output test response
Similarity
Can test path-delay faults and transition faults. The second capture
clock pulse must be running at the domain’s operating frequency or
at-speed.
Difference
Skewed-load requires the domain’s SE to switch value between the
launch and capture clock pulses making SE act as a clock signal.
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Basic At-Apeed Test Schemes
Capture
Capture
Launch
Launch
CK CK
SE SE
Shift Shift Last Shift Shift Shift Dead Shift
Shift Cycles
Skewed-load Double-capture
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Clock grouping
Can reduce test application time and
test data volume during automatic test
pattern generation (ATPG)
Is a process used to analyse all data
paths in the scan design in order to
determine all independent or
noninteracting clocks that can be
grouped and applied simultaneously
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Clock grouping example
CK1 CD2 and CD3 are independent
CD1
from each other; hence their
related clocks can be applied
CCD1 CCD2
simultaneously during test as
CK2 CK2.
CD2 CD3 CCD5
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Clock schemes
One-hot clocking
Apply only one grouped clock during each capture operation
Produce the highest fault coverage but generate most test
patterns
Simultaneous clocking
Mask off unknown values at the originating scan cells or
receiving scan cells across clock domains
Generate the least number of patterns but may result in high
fault coverage loss
Staggered clocking
Grouped clocks are applied sequentially
Generate pattern count close to simultaneous clocking and
fault coverage close to one-hot clocking
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At-speed Clocking Scheme for Testing Two
Interacting Clock Domains
(One-hot clocking)
Shift Window Capture Window Shift Window Capture Window Shift Window
C1 C2
CK1 … … …
C3 C4
CK2 … … …
GSE
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 27
At-speed Clocking Scheme for Testing Two
Interacting Clock Domains
(Simultaneous clocking)
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At-speed Clocking Scheme for Testing Two
Interacting Clock Domains
(Staggered clocking)
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 29
How to Generate Shift and Capture Clocks
Supplied from the Tester
Increase test cost
Limited high-frequency channels
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 30
Pipelined Scan Enable (SE) Design
SE1 for positive-edge
scan cells
SE2 for negative-edge
scan cells
SE D Q D Q
CK CK D Q
CK CK
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On-Chip Clock Controller
Shift Register The clock-gating
scan_en
cell makes sure
D Q
that no glitches or
Q1 Q2 Q3 Q4 Q5 spikes appear on
clk_out.
scan_clk
hs_clk_en
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On-Chip Clock Controller - Waveform
scan_clk
scan_en
pll_clk
hs_clk_en
cgc_clk_out
clk_out
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Logic Built-In Self-Test (BIST)
Test Pattern Generator
The logic BIST
(TPG) controller provides a
pass/fail indication
once the BIST
Logic
operation is complete.
BIST Circuit Under Test
Controller (CUT)
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Logic Built-In Self-Test
TPG
Constructed from linear feedback shift register
(LFSR) or cellular automata
Exhaustive testing – all possible 2n test patterns
Pseudo-random testing – a subset of 2n test
patterns
Pseudo-exhaustive testing – 2w or 2k-1 test
patterns, where w < k < n
ORA
Constructed from multiple-input signature register
(MISR)
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Logic BIST Architectures
Test-per-Scan BIST
Hardware overhead is low
Test-per-Clock BIST
Execute tests faster than Test-per-Scan
BIST
More hardware overhead
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Example Logic BIST Architectures
Self-Testing Using MISR and Parallel SRSG
(STUMPS)
Based on test-per-scan BIST
Integrate with traditional scan architecture
Linear phase shifter and linear phase compactor is
often used
Lose some fault coverage
CUT
CUT
(C)
(C)
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B1 B2 Operation mode
- 0 Normal
CBILBO 1 1
0 1
Scan
Test Generation and Signature Analysis
Y0 Y1 Y2
B1
Scan-Out
0
D Q D Q D Q
1
1 1D 1D 1D
2D Q 2D Q 2D Q
0 SEL SEL SEL
Scan-In B2 SCK X0 X1 X2
MISR
Combinational
TPG
CBILBO CBILBO
CUT
CBILBO
MISR
MISR
MISR
TPG
CC1
CC2
TPG
TPG
CBILBO
(a) For testing a finite-state machine (b) For testing a pipelined-oriented circuit
CBILBO Architectures
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Coverage-Driven Logic BIST Architectures
Approaches to Enhance logic BIST
Fault Coverage
In-field coverage enhancement
– Weighted Pattern Generation
– Test Point Insertion
– Mixed-Mode BIST
Manufacturing Coverage Enhancement
– Hybrid BIST
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Weighted Pattern Generation
Employ an LFSR
1 0 0 0
Insert a combinational
circuit between the output
of LFSR and the CUT
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Test Point Insertion
Observation point Observation point
0
Control point
Control point 1
BIST_mode BIST_mode
(a) Test point with a multiplexer (b) Test point with AND-OR gates
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Example of Inserting Test Points to Improve
Detection Probability
X1 X1 X4
X2 X2 X5
X3 Y
X3 X6
Y
X4
X5 Control point
X6 Observation point
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Test Point Insertion
Test Point Placement
Use fault simulation
Use testability measures to guide them
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 45
Mixed-Mode BIST
ROM Compression
Store deterministic patterns in ROM
LFSR Reseeding
Generate deterministic patterns by
reseeding LFSR with computed seeds
Embedding Deterministic Patterns
Transform the “useless” patterns into
deterministic patterns
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 46
Hybrid BIST
Perform top-up ATPG for the faults not
detected by BIST
Store the patterns directly on the tester
Store the patterns on the tester in a
compressed form and make use of the
existing BIST hardware to decompress
them
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Low-Power Logic BIST Architecture
Low-Transition BIST Design
Insert an AND gate and a toggle flip-flop at
the scan input of the scan chain
Advantages:
– Less design intrusive
– no performance degradation
– Low hardware overhead
Disadvantages:
– Low fault coverage
– Long test sequence
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Low-Power Logic BIST Architecture
Test-Vector-Inhibiting BIST Design
Inhibit the LFSR-generated pseudo-
random patterns which do not contribute to
fault detection from being applied to the
CUT
Advantages:
– Reduce test power
– No fault coverage loss as the original LFSR
Disadvantage:
– High hardware overhead
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Low-Power Logic BIST Architecture
Modified LFSR Low-Power BIST Design
Use two interleaved n/2-stage LFSRs
Advantages:
– Shorter test length
– High percentage of power reduction
– No performance degradation
– No test time increase
Disadvantage:
– Require constructing special clock trees
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At-Speed Logic BIST Architectures
Single-capture
One-hot single-capture
Staggered single-capture
Skewed-load
One-hot skewed-load
Aligned skewed-load
Staggered skewed-load
Double-capture
One-hot double-capture
Aligned double-capture
Staggered double-capture
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One-Hot Single-Capture
Shift Window Capture Window Shift Window Capture Window Shift Window
C1
… … …
CK1
d1 d2
C2
… … …
CK2
GSE
Advantages:
No need to worry about clock skews between clock domains
Can be used for slow-speed testing
Use a global scan enable (GSE) signal – compatible with Scan
Disadvantage:
Long test time
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Staggered Single-Capture
Shift Window Capture Window Shift Window
C1
CK1 … …
d1 d2 d3
C2
CK2 … …
GSE
Advantage:
Can detect inter-clock-domain delay faults within two clock domains
Disadvantage:
May cause some structural fault coverage loss if the sequence
order of the capture clocks is fixed.
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One-Hot Skewed-Load
Shift Window Capture Window Shift Window Capture Window Shift Window
S1 C1
CK1 … … …
d1
SE1
S2 C2
CK2 … … …
d2
SE2
Advantage:
Can be used for at-speed testing of intra-clock-domain delay faults
Disadvantages:
Cannot be used for testing of inter-clock-domain delay faults
Long test time
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 54
Aligned Skewed-Load
S1 C S
S2 Capture Window
S3
C1 S1
CK1 CK1
SE1 SE1
C2
CK2 CK2
SE2 SE2
C3
CK3 CK3
SE3 SE3
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Staggered Skewed-Load
Shift Window Capture Window Shift Window
S1 C1
CK1 … …
d1
SE1
d3 S2 C2
CK2 … d2
…
SE2
Advantage:
All intra-clock-domain and inter-clock-domain faults can be
tested in both synchronous and asynchronous clock
domains.
Disadvantage:
Complicated physical implementation
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One-Hot Double-Capture
Shift Window Capture Window Shift Window Capture Window Shift Window
C1 C2
CK1 … … …
d1
C3 C4
CK2 … … …
d2
GSE
Advantage:
Can be used for true at-speed testing of intra-clock-domain delay
faults
Disadvantages:
Cannot be used for testing of inter-clock-domain delay faults
Long test time
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 57
C1
Aligned Double-Capture C
C2 C
C3
Capture Window
C1 C4
CK 1
CK1
C2
CK 2 CK2
C3
CK3
CK 3
GSE
GSE
Advantages:
Ease physical implementation
Integrate logic BIST with scan/ATPG
Disadvantage:
May cause fault coverage loss due to the ordered
sequence of capture clocks.
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Summary of Industry Practices for
At-Speed Logic BIST
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Test Compression
Decompressor
Add some additional on-chip hardware before the
scan chains to decompress the test stimulus
Use lossless compression
Compactor
Add some additional on-chip hardware after scan
chains to compact the response
The compaction is lossy
Advantages:
Reduce ATE memory
Reduce test data volume and test application time
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Test Compression Architecture
D Stimulus Response
Compressed e C Compacted
c o
o m
Low-Cost Stimulus m Scan-Based p Response
p a
ATE r Circuit c
e t
s (CUT) o
s r
o
r
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Circuits for Test Stimulus Compression
Linear-Decompression-Based Schemes
Combinational linear decompressors
Sequential linear decompressors
Broadcast-Scan-Based Schemes
Broadcast scan
Illinois scan
Multiple-input broadcast scan
Reconfigurable broadcast scan
Virtual scan
Comparison
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Linear-Decompression-Based Schemes
Linear Decompressor Concept
Consists of only XOR gates and Flip-Flops
Its output space is a linear subspace that is spanned by a
Boolean matrix.
Combinational Linear Decompressor
Consists of only XOR gates
Sequential Linear Decompressor
Consists of XOR gates and Flip-Flops
Flip-flops provides additional free variables for state encoding.
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Example of symbolic
X1
Z9 Z5 Z1
decompressor
X2
Z10 Z6 Z2
X3
Z11 Z7 Z3
+
X4
Z12 Z8 Z4
X10 X8 X6 +
Z9 = X1 X4 X9 Z5 = X3 X7 Z1 = X2 X5
Z10 = X1 X2 X5 X6 Z6 = X1 X4 Z2 = X3
Z11 = X2 X3 X5 X7 X8 Z7 = X1 X2 X5 X6 Z3 = X1 X4
Z12 = X3 X7 X10 Z8 = X2 X5 X8 Z4 = X1 X6
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0 1 0 0 1 0 0 0 0 0 Z1
0 0 1 0 0 0 0 0 0 0 X1 Z2
1 0 0 1 0 0 0 0 0 0 X2 Z3
1 0 0 0 0 1 0 0 0 0 X3 Z4
0 0 1 0 0 0 1 0 0 0 X4 Z5
1 0 0 1 0 0 0 0 0 0 X5 Z6
1 1 0 0 1 1 0 0 0 0 X6 = Z7
0 1 0 0 1 0 0 1 0 0 X7 Z8
1 0 0 1 0 0 0 0 1 0 X8 Z9
1 1 0 0 1 1 0 0 0 0 X9 Z10
0 1 1 0 1 0 1 1 0 0 X10 Z11
0 0 1 0 0 0 1 0 0 1 Z12
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Combinational Linear Decompressor
Advantage:
Simpler hardware and control because only XOR
gates are used
Disadvantages:
Low Encoding Efficiency
– Because no free variables are used
– Can be improved by dynamically adjusting the
number of scan chains that are loaded in each
clock cycle.
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Sequential Linear Decompressor
Based on linear finite-state machines
Examples: LFSRs, cellular automata, ring generators
Advantages:
Allow free variables from earlier clock cycles
Much greater flexibility than combinational linear decompressor
Two classes
Static reseeding
– Drawbacks
The tester is idle while the LFSR is running in autonomous
mode.
The LFSR must be at least as large as the number of
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Typical Sequential Linear Decompressor
Linea r
b Cha nnels
fr om Test er S
R
Sca n Cha in n (m bit s)
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Broadcast-Scan-Based Schemes
Broadcast scan
Illinois Scan
Multiple input broadcast scan
Reconfigurable broadcast scan
Virtual scan
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Broadcast Scan
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Illinois Scan
Consists of two modes of operations
Broadcast mode
Serial scan mode
Main Drawback
No test compression in serial scan mode
Ways to reduce number of patterns
Multiple-Input broadcast scan
Reconfigurable broadcast scan
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 72
Illinois Scan Architecture
Scan In
Segment 1
Segment 2
MISR
Segment 3
Scan Out
Segment 4
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 73
Multiple-input broadcast scan
Use more than one channel to drive all
scan chains
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 74
Reconfigurable Broadcast Scan
Reduce the number of required channels
compared to multiple-input broadcast scan
Provide the capability to reconfigure the set of
scan chains
Two possible reconfiguration schemes
Static reconfiguration
Dynamic reconfiguration
– Need more control information versus static
reconfiguration
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 75
Pin Pin Pin Pin Control Line
1 2 3 4
0 Scan Chain 1
1
0 Scan Chain 2
1
0
Scan Chain 3
1
0 Scan Chain 4
1
Scan Chain 5
Scan Chain 6
0
Scan Chain 7
1
Scan Chain 8
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 77
Example Virtual Scan Broadcaster
Using an XOR Network
External Scan Input Ports VirtualScan Inputs
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 78
Example Virtual Scan Broadcaster
Using a MUX Network
External Scan Input Ports VirtualScan Inputs
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 79
Comparison
100.0
Illinois
MUX-Separate
80.0
MUX-Combined
2-input XOR
Percent Encodable
3-input XOR
60.0
40.0
20.0
0.0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Specified Bits
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 81
Space Compaction
Space compactor is combinational
Inverse procedure of linear expansion
Compaction Techniques
X-Compact
X-Blocking
X-Masking
X-Impact
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 82
X-tolerant Response Compaction
SC1 SC2 SC3 SC4 SC5 SC6 SC7 SC 8
XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 83
X-compactor
Theorem 2.1
If only a single scan chain produces an error at any scan-out
cycle, the X-compactor is guaranteed to produce errors at
the X-compactor outputs at that scan-out cycle, if and only if
no row of the X-compact matrix contains all 0’s.
Theorem 2.2
Errors from any one, two, or an odd number of scan chains
at the same scan-out cycle are guaranteed to produce errors
at the X-compactor outputs at that scan-out cycle, if every
row of the X-compact matrix is nonzero, distinct, and
contains an odd number of 1’s.
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 84
X-Blocking (X-Bounding)
Block X’s before reaching the response
compactor
Scan design rule checker for identifying
potential X-generators
Impact
No X’s will be observed
Fault coverage loss
Add area overhead
May impact delay due to the inserted logic
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 85
X-Masking
Mask off X’s right before the response compactor
Scan Out 1
Mask Bit 1
Scan Out 2
Mask Bit 2
Compactor
Scan Out 3
Mask Bit 3
Mask
Controller
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 86
X-Impact
SC1
? a G1
.
G7 p
? b SC2
? c G2
G3
1
1
d
e G4 .
f1 SC3
X f G8 q
G5 SC4
? g G6
? h
Handling of X-Impact
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 87
X-Impact
a SC1
? G1
.
G7 p
0 b SC2
1 c f 2 G2
G3
1 d SC3
G4
1 e
f G8 q
G5 SC4
g G6
h
Handling of Aliasing
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 88
Time compaction
Uses sequential logic to compact test
response
No unknown (X) values are allowed to reach
the compactor; otherwise X-bounding, X-
masking must be employed.
MISR is most widely used
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 89
Mixed Time and Space Compaction
Combine the advantages of a time compactor
and a space compactor but with high area
overhead
Examples of mixed time and space
compactors
OPMISR
Convolutional Compactor
q-compactor
– No feedback path
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 90
q-compactor
inputs
output
D D D D D
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 91
Low-Power Test Compression Architectures
Low-Power architectures
The Bandwidth-match low-power scan design can be used
for test compression
An Example – The UltraScan Architecture
Time-Division Demultiplexer (TDDM)
Time-Division Multiplexer (TDM)
Clock Controller
The TDDM/TDM circuit operates at 10 MHz and slow down
the shift clock frequency to 1 MHz resulting in 10X reduction
in shift power dissipation
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 92
ATE
Test Responses
Expected Responses
Test Patterns
VirtualScan
ESI 1 ESIn Inputs
...
ck1 Clock
TDDM
Controller
VirtualScan SI 1 ... SI m
Circuit
Broadcaster
Full-Scan
Circuit
s10 s11 s12 s13 ... sm0 sm1 sm2 sm3
... ck2
TDM ck1
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 93
Summary of Industry Practices for Test
Compression
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 94
Summary of Industry Practices for
At-Speed Delay Fault Testing
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 97
Traditional RAS Architecture
Access to a scan cell by
PI Combinational logic PO decoding a full address with a
row decoder (X) and a column
decoder (Y)
SC SC … SC
Row (X) decoder
CK
SC SC … SC SI
SCK
…
…
SO
SC SC … SC
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 98
Traditional RAS Scan Cell
Q
D DI Q . Q
D DI Q . PO
0 SI
SI
SI 1 SE Q
TM SE CK
..
AS CK
AS
Traditional Scan Cell Design Toggle Scan Cell Design
Broadcast the external SI port to Require a clear mechanism to
all scan cells, cause routing reset all scan cells prior to testing
problem
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 99
PRAS Design In normal mode, RE is set to 0, forcing
each scan cell to act as a normal D
flip-flop.
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 100
PRAS Design
Sense-amplifiers & MISR PO
… Rows are enabled in a fixed
… order. It is only necessary to
Row enable shift register
SC SC SC
Combinational logic
supply a column address to
… specify which scan cell in an
SC SC SC
enabled row to access.
…
…
SC SC … SC …
…
TM Test Column line drivers PI
SI/SO control …
CK logic Column address decoder
CA
PRAS Architecture
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 101
PRAS Test Procedure
for each test vector vi (i = 1, 2, …, N) {
/* Test stimulus application */
/* Test response compression */
enable TM;
for each row rj (j = 1, 2, …, m) {
read all scan cells in rj / update MISR;
for each scan cell SC in rj
/* v(SC): current value of SC */
/* vi(SC): value of SC in vi */
if v(SC) vi(SC)
update SC;
}
/* Test response acquisition */
disable TM;
apply the normal clock;
}
scan-out MISR as the final test response;
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 102
STAR Design SO
SC SC SC
All rows are enabled (selected) in a
Combinational logic
fixed order one at a time by
SC SC … SC rotating a 1 in the row enable shift
register.
…
…
…
… SC When a row is enabled, all columns
SC SC
(or scan cells) associated with the
… enabled row are selected at the same
TM Test Column line drivers PI time.
control …
CK logic Buffers
SI
STAR Architecture
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 103
STAR Test Procedure
for each test vector vi (i = 1, 2, …, N) {
/* Test stimulus application */
/* Test response compression */
enable TM;
for each row rj (j = 1, 2, …, m) {
read all scan cells in rj / update MISR;
/* Update selected rows */
update all scan cells in rj;
}
/* Test response acquisition */
disable TM;
apply the normal clock;
}
scan-out MISR as the final test response;
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 104
Test Compression RAS Architecture
RAS design is effective in reducing shift
power dissipation
RAS is achieved power reducing at the
cost of increased area and routing
overhead
RAS cannot reduce test data volume
and test application time significantly
Test compression schemes are
applicable for RAS design
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 105
STAR Compression Architecture
SO
A decompressor is used to
Compactor PO decompress the ATE-supplied
… stimuli.
Row enable shift register
Combinational logic
SC SC SC
A compactor is used to compact
the test responses.
SC SC … SC
…
…
SC SC … SC
…
TM Test Column line driver PI
control …
CK logic Decompressor
SI
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 106
Reconfigured STAR Compression
SO
The multiplexer allows transmitting
Compactor scan-in stimulus from one column to
… PO
another column.
Combinational logic
SC SC SC
scan-out test response on the column
SC SC … SC
to be fed to the compactor in serial
scan mode.
…
…
SC SC … SC
…
Column line drivers PI
TM Test …
control
CK logic 0 1 0 1 0 1
Decompressor
SI
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 107
At-Speed RAS Architectures
Major advantages of RAS design
Significant shift power reduction
Facilitating fault diagnosis
Additional benefit for at-speed delay fault testing
Launch-on-shift (a.k.a. skewed-load)
Launch-on-capture (a.k.a. double-capture)
Enhanced-scan based at-speed RAS Design
Maximize delay fault detection capability
Long vector count problem
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 108
At-Speed RAS Architectures
Approaches to overcoming long vector count problem
Using Enhanced-scan-based at-speed RAS architecture
Using Conventional launch-on-capture schemes
Launch-on-capture based at-speed RAS architecture
Allow multiple transitions on the initialization vector; thereby
reducing the vector count.
Hybrid at-speed RAS architecture
First generate transition fault tests using launch-on-capture
Then supplement the tests using enhanced scan
Faster-than-at-speed RAS architecture
To catch small delay defects that escape traditional transition fault
tests.
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System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 109
Concluding Remarks
Scan and Logic built-in self-test (BIST) are two most widely
used DFT techniques
ATPG can no longer guarantee adequate product quality;
at-speed delay testing and test compression become a
requirement for 90-nanometer designs and below.
Physical failures can escape detection of ATPG; logic BIST
and low-power testing are gaining more industry
acceptance in VLSI designs at 65-nanometer and below.
Challenges lie ahead whether pseudo-exhaustive testing
will become a preferred BIST pattern generation technique
and random-access scan will be a promising DFT
technique for test power reduction.
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