Internship Training Program

on
FPGA DESIGN TECHNIQUES
USING Quartus/Xilinx FRONT END
TOOL
Presented by
Dr.R.UMA
 Day – 18
Design and performance of multiplier topology
Array Multiplier
 Coding
module arraymul(p,a,b); assign w[12]=a[3]&b[0];
input [3:0] a,b; assign w[13]=a[3]&b[1];
output [7:0] p; assign w[14]=a[3]&b[2];
wire [15:0] w; assign w[15]=a[3]&b[3];
assign w[0]=a[0]&b[0]; fa x9(p[3],c9,s6,w[12],1'b0);
assign w[1]=a[0]&b[1]; fa x10(p[4],c10,s7,c9,w[13]);
assign p[0]=w[0];
assign w[2]=a[0]&b[2]; fa x11(p[5],c11,s8,c10,w[14]);
wire s1,s2,s3,s4,c1,c2,c3,c4;
assign w[3]=a[0]&b[3]; fa x12(p[6],p[7],c11,c8,w[15]);
fa x1(p[1],c1,w[1],w[4],1'b0);
endmodule
fa x2(s2,c2,w[2],w[5],c1);
assign w[4]=a[1]&b[0]; fa x3(s3,c3,w[3],w[6],c2);
assign w[5]=a[1]&b[1]; fa x4(s4,c4,w[7],1'b0,c3);
assign w[6]=a[1]&b[2];
assign w[7]=a[1]&b[3]; wire s5,s6,s7,s8,c5,c6,c7,c8;
fa x5(p[2],c5,s2,1'b0,w[8]);
assign w[8]=a[2]&b[0]; fa x6(s6,c6,w[9],c5,s3);
assign w[9]=a[2]&b[1]; fa x7(s7,c7,w[10],c6,s4);
assign w[10]=a[2]&b[2]; fa x8(s8,c8,w[11],c7,c4);
assign w[11]=a[2]&b[3];
module arraymul_test;
reg [3:0] a; Test Bench
reg [3:0] b;
wire [7:0] p;
arraymul uut (
.p(p),
.a(a),
.b(b)
);

initial begin
a=4'b1000;b=4'b1000;
#10 a=4'b1001;b=4'b0110;
#10 a=4'b1010;b=4'b0010;
#10 a=4'b0011;b=4'b0010;
#10 a=4'b1111;b=4'b1111;
end
initial
$monitor($time,"a=%d,b=%d,p=%d\n",a,b,p);
initial #50 $stop;
endmodule
 Output

0a= 8,b= 8,p= 64

10a= 9,b= 6,p= 54
20a=10,b= 2,p= 20
30a= 3,b= 2,p= 6
40a=15,b=15,p=225
 Performance

Timing constraint: Default path analysis

Total number of paths / destination ports: 382 / 8
-------------------------------------------------------------------------
Delay: 11.680ns (Levels of Logic = 7)
Source: a<1> (PAD)
Destination: p<7> (PAD)

Data Path: a<1> to p<7>

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 8 1.328 1.399 a_1_IBUF (a_1_IBUF)
LUT6:I0->O 2 0.254 1.181 x4/Mxor_s_xo<0>1 (s4)
LUT6:I0->O 2 0.254 1.181 x7/cout1 (c7)
LUT6:I0->O 2 0.254 0.726 x8/Mxor_s_xo<0>1 (s8)
LUT6:I5->O 2 0.254 1.002 x11/cout1 (c11)
LUT4:I0->O 1 0.254 0.681 x12/cout1 (p_7_OBUF)
OBUF:I->O 2.912 p_7_OBUF (p<7>)
----------------------------------------
Total 11.680ns (5.510ns logic, 6.170ns route)
(47.2% logic, 52.8% route)
Wallace
module wallace( coding
output [7:0] p,
input [3:0] a, assign w[12]=a[3]&b[0];
input [3:0] b assign w[13]=a[3]&b[1];
); assign w[14]=a[3]&b[2];
assign w[15]=a[3]&b[3];
wire [15:0] w;
assign w[0]=a[0]&b[0]; assign p[0]=w[0];
assign w[1]=a[0]&b[1]; fa x1(p[1],c1,w[1],w[4],1'b0);
assign w[2]=a[0]&b[2]; fa x2(s2,c2,w[2],w[5],w[8]);
assign w[3]=a[0]&b[3]; fa x3(s3,c3,w[3],w[6],w[9]);
fa x4(s4,c4,w[7],w[10],1'b0);
assign w[4]=a[1]&b[0];
assign w[5]=a[1]&b[1]; fa x5(p[2],c5,s2,c1,1'b0);
assign w[6]=a[1]&b[2]; fa x6(s6,c6,s3,c2,w[12]);
assign w[7]=a[1]&b[3]; fa x7(s7,c7,s4,c3,w[13]);
fa x8(s8,c8,w[11],c4,w[14]);
assign w[8]=a[2]&b[0]; fa x9(p[3],c9,s6,c5,1'b0);
assign w[9]=a[2]&b[1]; fa x10(p[4],c10,s7,c6,c9);
assign w[10]=a[2]&b[2]; fa x11(p[5],c11,s8,c7,c10);
assign w[11]=a[2]&b[3]; fa x12(p[6],p[7],c11,c8,w[15]);

endmodule
module wallace_test; Test Bench
reg [3:0] a;
reg [3:0] b;
wire [7:0] p;
wallace uut (
.p(p),
.a(a),
.b(b)
);

initial begin
a=4'b1000;b=4'b1000;
#10 a=4'b1001;b=4'b0110;
#10 a=4'b1010;b=4'b0010;
#10 a=4'b0011;b=4'b0010;
#10 a=4'b1111;b=4'b1111;
end
initial
$monitor($time,"a=%d,b=%d,p=%d\n",a,b,p);
initial #50 $stop;
endmodule
 Output

0a= 8,b= 8,p= 64

10a= 9,b= 6,p= 54
20a=10,b= 2,p= 20
30a= 3,b= 2,p= 6
40a=15,b=15,p=225
 Performance

Timing constraint: Default path analysis

Total number of paths / destination ports: 263 / 8
-------------------------------------------------------------------------
Delay: 10.739ns (Levels of Logic = 6)
Source: a<1> (PAD)
Destination: p<6> (PAD)

Data Path: a<1> to p<6>

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 10 1.328 1.284 a_1_IBUF (a_1_IBUF)
LUT4:I0->O 2 0.254 1.181 x4/Mxor_s_xo<0>1 (s4)
LUT6:I0->O 2 0.254 1.156 x7/cout1 (c7)
LUT5:I0->O 2 0.254 1.181 x11/cout1 (c11)
LUT6:I0->O 1 0.254 0.681 x12/Mxor_s_xo<0>1 (p_6_OBUF)
OBUF:I->O 2.912 p_6_OBUF (p<6>)
----------------------------------------
Total 10.739ns (5.256ns logic, 5.483ns route)
(48.9% logic, 51.1% route)
Dadda
 Coding
module dadda(
output [7:0] p,
input [3:0] a,
input [3:0] b
);
wire y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,y13,y14,y15;
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,xx;
wire s1,s2,s3,s4,s5,s6;
assign p[0]=a[0]&b[0]; assign y1=a[0]&b[1]; assign y2=a[1]&b[0]; ha x1(p[1],c1,y1,y2);
assign y3=a[0]&b[2]; assign y4=a[1]&b[1]; assign y5=a[2]&b[0]; fa x2(s1,c2,y3,y4,y5);
assign y6=a[0]&b[3]; assign y7=a[1]&b[2]; assign y8=a[2]&b[1]; fa x3(s2,c3,y6,y7,y8);
assign y9=a[1]&b[3]; assign y10=a[2]&b[2]; assign y11=a[3]&b[1]; fa x4(s3,c4,y9,y10,y11);
assign y12=a[2]&b[3]; assign y13=a[3]&b[2];
ha x5(s4,c5,y12,y13);
ha x6(p[2],c6,s1,c1);
ha x7(s5,c7,s2,c2);
ha x8(s6,xx,s3,c3);
assign y14=a[3]&b[0];
fa x9(p[3],c8,c6,s5,y14);
fa x10(p[4],c9,c8,c7,s6);
fa x11(p[5],c10,c4,s4,c9);
assign y15=a[3]&b[3];
fa x12(p[6],p[7],c10,c5,y15);
endmodule
 Test bench

module dadda_test;
reg [3:0] a;
reg [3:0] b;
wire [7:0] p;
dadda uut (
.p(p),
.a(a),
.b(b)
);
initial begin
a=4'b1000;b=4'b1000;
#10 a=4'b1001;b=4'b0110;
#10 a=4'b1010;b=4'b0010;
#10 a=4'b0011;b=4'b0010;

end
initial
$monitor($time,"a=%d,b=%d,p=%d\n",a,b,p);
initial #50 $stop;
endmodule
 Output

0a= 8,b= 8,p= 64

10a= 9,b= 6,p= 54
20a=10,b= 2,p= 20
30a= 3,b= 2,p= 6
40a=15,b=15,p=225
 Performance

Timing constraint: Default path analysis

Total number of paths / destination ports: 270 / 8
-------------------------------------------------------------------------
Delay: 12.433ns (Levels of Logic = 7)
Source: a<2> (PAD)
Destination: p<5> (PAD)

Data Path: a<2> to p<5>

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 10 1.328 1.463 a_2_IBUF (a_2_IBUF)
LUT6:I0->O 3 0.254 1.221 x2/cout1 (c2)
LUT6:I0->O 2 0.254 1.181 x7/Mxor_s_xo<0>1 (s5)
LUT6:I0->O 2 0.254 1.181 x9/cout1 (c8)
LUT6:I0->O 3 0.254 1.196 x10/cout1 (c9)
LUT6:I1->O 1 0.254 0.681 x11/Mxor_s_xo<0>1 (p_5_OBUF)
OBUF:I->O 2.912 p_5_OBUF (p<5>)
----------------------------------------
Total 12.433ns (5.510ns logic, 6.923ns route)
(44.3% logic, 55.7% route)
Vedic Mul 2x2
Coding
Test Bench:
module vedic2x2_test;
module vedic2x2(p,a,b); reg [1:0] a;
input [1:0] a,b; reg [1:0] b;
output [3:0] p; wire [3:0] p;
wire w1,w2; vedic2x2 uut (.p(p),.a(a),.b(b));
assign p[0]=a[0]&b[0]; initial begin
assign w1=b[1]&a[0]; a=2'b00;b=2'b00;
assign w2=b[0]&a[1]; #10 a=2'b01;b=2'b01;
assign p[1]=w1^w2; #10 a=2'b10;b=2'b10;
assign c1=w1&w2; #10 a=2'b11;b=2'b10;
assign w3=b[1]&a[1]; #10 a=2'b11;b=2'b11;
assign p[2]=c1^w3; end
assign p[3]=c1&w3; initial
endmodule $monitor($time,"a=%d,b=%d,p=%d\n",a,b,p);
initial #50 $stop;
endmodule
 Output

0a=0,b=0,p= 0
10a=1,b=1,p= 1
20a=2,b=2,p= 4
30a=3,b=2,p= 6
40a=3,b=3,p= 9
Vedic 4x4
Example
 Coding
module vedic4x4(p,a,b);
input [3:0] a,b;
output [7:0] p; assign p[0]=pp[0];
wire [15:0] pp; assign p[1]=pp[1];
vedic2x2 d1(pp[3:0],a[1:0],b[1:0]); fa x7(p[2],w1,s1,pp[8],1'b0);
vedic2x2 d2(pp[7:4],a[1:0],b[3:2]); fa x8(p[3],w2,w1,s2,pp[9]);
vedic2x2 d3(pp[11:8],a[3:2],b[1:0]); fa x9(p[4],w3,w2,s3,s4);
vedic2x2 d4(pp[15:12],a[3:2],b[3:2]); fa x10(p[5],w4,w3,pp[7],s5);
fa x11(p[6],w5,w4,s6,1'b0);
wire s1,s2,s3,s4,s5,s6,c1,c2,c3,c4,c5,c6; fa x12(p[7],w6,w5,pp[15],1'b0);
fa x1(s1,c1,pp[2],pp[4],1'b0); endmodule
fa x2(s2,c2,pp[3],pp[5],c1);
fa x3(s3,c3,pp[6],c2,1'b0);

fa x4(s4,c4,pp[10],pp[12],1'b0);
fa x5(s5,c5,pp[11],pp[13],c4);
fa x6(s6,c6,pp[14],c5,1'b0);
 Test bench

module vedic4x4_test;
reg [3:0] a;
reg [3:0] b;
wire [7:0] p;
vedic4x4 uut (.p(p),.a(a),.b(b));
initial begin
a=4'b1000;b=4'b1000;
#10 a=4'b1001;b=4'b0110;
#10 a=4'b1010;b=4'b0010;
#10 a=4'b0011;b=4'b0010;
#10 a=4'b1111;b=4'b1111;
end
initial
$monitor($time,"a=%d,b=%d,p=%d\n",a,b,p);
initial #50 $stop;
endmodule
 Output

0a= 8,b= 8,p= 64

10a= 9,b= 6,p= 54
20a=10,b= 2,p= 20
30a= 3,b= 2,p= 6
40a=15,b=15,p=225
 Performance

Timing Details:
---------------
All values displayed in nanoseconds (ns)

==================================================================
=======
Timing constraint: Default path analysis
Total number of paths / destination ports: 77 / 37
-------------------------------------------------------------------------
Delay: 6.395ns (Levels of Logic = 3)
Source: a<0> (PAD)
Destination: p<1> (PAD)

Data Path: a<0> to p<1>

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 8 1.328 1.220 a_0_IBUF (a_0_IBUF)
LUT4:I0->O 1 0.254 0.681 d1/Mxor_p<1>_xo<0>1 (p_1_OBUF)
OBUF:I->O 2.912 p_1_OBUF (p<1>)
----------------------------------------
Total 6.395ns (4.494ns logic, 1.901ns route)