Department of BES-II

Digital Design and Computer Architecture 23EC1202

Topic:
MULTIPLEXERS AND DE-MULTIPLEXERS

Session No: 05
 AIM OF THE SESSION

To familiarize students with the basic concept of multiplexers and demultiplexers.

INSTRUCTIONAL
OBJECTIVES

This Session is designed to:

1. Demonstrate multiplexers, truth tables and its application.
2. Describe the demultiplexers, truth tables and its application.
3. Analyze how demultiplexers are used for data distribution.

LEARNING OUTCOMES

At the end of this session, you should be able to:

1. Interpret and create truth tables for different multiplexer, demultiplexer configurations, demonstrating an
understanding of how input lines are selected based on control inputs.
2. Apply the concepts of multiplexer and demultiplexer for data selection and distribution.
 SESSION INTRODUCTION : MULTIPLEXER

• A multiplexer is a combinational circuit that has M selection lines, 2 N input lines and a single output line.
• It is also called a data selector and control inputs are termed select inputs.
 2X1 MULTIPLEXER

a) Block Diagram b) Truth Table c) Logic Diagram

𝐼0
S Y
𝐼0 2x1 Y
𝐼1 0 Y
MUX 𝐼1
1
S
S
Boolean Expression,
Y=+
 4X1 MULTIPLEXER

a) Block Diagram b) Truth Table c) Logic Diagram

𝐼0
Y
𝐼0 𝐼1
𝐼1 4x1 Y
0 0
𝐼2
𝐼2 MUX 0 1
Y
𝐼3 𝐼3
1 0
𝑆 1𝑆 0 1 1
𝑆 1𝑆 0
Boolean Expression,
Y = +++
 Implementation of Boolean Function using Multiplexers

Ex.1) Implement the function using suitable MUX

Solution: A B C F (A,B,C)
𝑉 𝑐𝑐 0
0 0 0 1 𝑉 𝑐𝑐 1
0 0 1 1 GND 2
0 1 0 0
GND 3 8X1 𝐹
𝑉 𝑐𝑐 4
0 1 1 0 GND 5
1 0 0 1 𝑉 𝑐𝑐 6
𝑉 𝑐𝑐 7
1 0 1 0
1 1 0 1 = Logic 1
1 1 1 1 GND = Logic 0 𝐴𝐵𝐶
Ex.2) Implement the function using 4X1 MUX considering C as Input line and A, B as
selection lines.

Solution:
a) Implementation Table b) Logic Diagram
Ex.3) Develop an Arithmetic Logic Unit (ALU) by using a 4-to-1 Multiplexer.

Solution:
 Ex.4) Design a 8x1 multiplexer using two 4*1 multiplexer and one 2x1 multiplexer.

Solution:
APPLICATIONS OF A
MULTIPLEXER

2
0
1
 APPLICATIONS OF A MULTIPLEXER

MEMORY ADDRESS
MEMORY UNIT

Block 1
Block 2
Block 3
Block 4
MUX CPU
Block 5
Block 6
Block 7
Block 8
 De-multiplexer

• A De-multiplexer is a combinational circuit that has only 1 input line and 2M = N output lines and M
selection lines.

• Demultiplex means one into many. By applying control signals, we can steer the input signal to one
of the output lines.

Data De- N Output

Input MUX Lines

M Selection Lines
 1 x 2 DEMULTIPLEXER

a) Block Diagram b) Truth Table c) Logic Diagram

D
Input S 𝑌0
1x2 𝑌0
D
DEMUX 𝑌1 D 0 D 0
D 1 0 D 𝑌1
S
S

Boolean Expression,
=D
=D
 DEMULTIPLEXER : 1X4

a) Block Diagram b) Truth Table c) Logic Diagram

Input D
𝑌0 𝑌0
1x4 𝑌1 D 0 0 D 0 0 0
D 𝑌2
DEMUX 𝑌1
𝑌3 D 0 1 0 D 0 0
D 1 0 0 0 D 0
𝑆0 𝑆1 𝑌2
D 1 1 0 0 0 D
𝑌3
Boolean Expressions,
=D 𝑆 0𝑆 1
=D
=D
=D
APPLICATIONS OF DEMUX
 SELF-ASSESSMENT QUESTIONS

1. What is a multiplexer?

A. It is a type of decoder which decodes several inputs and gives one output
B. A multiplexer is a device which converts many signals into one
C. It takes one input and results into many output
D. It is a type of encoder which decodes several inputs and gives one output

2. A 4-to-1 MUX has ________ input lines and ________ select lines.

A. 2, 1
B. 4, 2
C. 8, 2
D. 1, 4
 SELF-ASSESSMENT QUESTIONS

3. What is the output configuration of a Demultiplexer (DEMUX)?

A. One input, multiple outputs

B. Multiple inputs, one output
C. Multiple inputs, multiple outputs
D. One input, one output

4. In a 4-to-1 MUX, if the select lines are 01, which input line will be selected?

A. Input 0
B. Input 1
C. Input 2
D. Input 3
 TERMINAL QUESTIONS

Short answer questions:

1. Provide the symbol and truth table for a 4-to-1 multiplexer.
2. In a 2-to-1 multiplexer, how many input lines are there, and how many control lines are required to select one of the inputs?

Long answer questions:

1. Design the function F(A,B,C)=∑m(1,4,5,7) using 4X1 MUX considering “A” as Input line and B, C as selection lines.
2. Describe and draw how 8:1 multiplexer can be designed using 4:1 mux and 2:1 mux.
3. Design an Arithmetic Logic Unit (ALU) by using a 4-to-1 Multiplexer.
4. Provide a thorough description of the architecture of a 1:4 de-multiplexer, including its input lines, control lines, and output.
 REFERENCES FOR FURTHER LEARNING OF THE
SESSION

Reference Books:
1. Computer System Architecture by M. Moris Mano
2. Fundamentals of Digital Logic with Verilog HDL by Stephen Brown and ZvonkoVranesic

Sites and Web links:

1. https://unacademy.com/content/jee/difference-between/multiplexer-and-demultiplexer/
2. https://www.electronicshub.org/multiplexer-and-demultiplexer/
 THANK YOU

Team – Digital Design & Computer Architecture