STA - Static Timing Analysis

Static Verification Flow

What is Static Verification?

● Static verification:

- Verifies timing and functionality

- STA and equivalence checking

- Is exhaustive

- Uses formal, mathematical techniques instead of vectors

- Does not use dynamic logic simulation

Static Timing Analysis Flow
Required Input Files
Components of a Master Run Script
Read and Constrain
# Comment scripts
# Include all libraries - technology and IP model libraries set link_path “* my_tech_lib.db
memory_lib.db”

# Read all gate-level design files

read_verilog my_full_chip.v

# Read libraries and link the design

link_design MY_FULL_CHIP

# Set up bc_wc analysis with 2 SDF. Wait for checks later

read_sdf –analysis_type bc_wc –max_type sdf_max –min_type sdf_min

# Apply chip-level constraints for pre or post layout analysis

source MY_FULL_CHIP_CONST.tcl
Recall: Components of a Master Run Script
Validate Complete and Correct Constraints

report_design Analysis Type

report_clock Clocks

report_annotated_delay
report_annotated_check Complete SDF

check_timing Complete Constraints

Validate Complete and Correct Constraints

Read one SDF delay for setup

OR hold analysis

Read two SDF delays for setup

and hold analysis

Min and Max SDF represent a

small variation across a die
Ready to Analyze STA Reports
Report All Violations
report_constraint –all_violators

max_delay/setup ('Clk1' group)

The Number of Violations
report_analysis_coverage
More Details: Path Timing Reports
pt_shell> report_timing

Default: Returns the worst path for max analysis for:

● Each clock
● Recovery checks
● Clock gating checks

Customize with MANY different switches:

● Setup versus hold reports
● Increase the significant digits
● Focus on specific paths
● Increase the # of generated reports
● Include net fanout
● Expand the calculated clock network delay
Clock Network Reports
report_clock_timing –type skew

For each clock, report

REAL skew
Bottleneck Analysis
Identify cells involved in multiple violations.
Use the results to determine cells to buffer or upsize.
Specify Timing Assertions (1)
Example:
» Set up the basic timing assertions for the design. Start with the clock information.

pt_shell> create_clock -name CLK -period 30 [get_port CLOCK]

pt_shell> set_clock_uncertainty 0.5 [all_clocks]
pt_shell> set_clock_latency -min 3.5 [get_clocks CLK] pt_shell> set_clock_latency -max 5.5
[get_clocks CLK] pt_shell> set_clock_transition -min 0.25 [get_clocks CLK] pt_shell>
set_clock_transition -max 0.3 [get_clocks CLK]

For post layout clock tree:

set_propagated_clock <clock_object_list>
or
set timing_all_clocks_propagated true
Specify Timing Assertions (2)

Reference clock waveform

Reference clock waveform

with uncertainty

Reference clock waveform

with latency

Reference clock waveform

with transition

Reference clock waveform

with uncertainty, latency,
and transition
Advanced Timing Analysis
● Analysis Modes

● Data to Data Checks

● Case Analysis

● Multiple Clocks per Register

● Minimum Pulse Width Checks

● Derived Clocks

● Clock Gating Checks

● Netlist Editing

● Report_clock_timing

● Clock Reconvergence
Pessimism

● Worst-Arrival Slew Propagation

● Debugging Delay Calculation

Back-Annotation - Parasitics, Reduced and Distributed Parasitic Files

● Reduced format annotates an RC pi model, and computes the effective capacitance.

● Distributed format enables PrimeTime to annotate each physical segment of the

routed netlist (most accurate form of RC back- annotation)
 PrimeTime Timing Models Support

PrimeTime offers the following timing models to address STA needs for IP, large
hierarchical designs, and custom design:

● Quick Timing Model (QTM)

● Extracted Timing Model (ETM)
● Interface Logic Model (ILM)
● Stamp Model
Timing Model Usage Scenario in PrimeTime
Quick Timing Models (QTMs)

● Provide means to quickly and easily create a timing model of an unfinished block for
performing timing analysis

● Should later be replaced with gate-level netlists or equivalent models

● Created with PrimeTime commands - no compiling needed!

● Can contain:
1. Port specs for the block
2. Setup and hold constraints for inputs
3. Clock-to-output delays
4. Input-to-output delays

● Benefits
1. accurate specs generated with a lot less effort
2. apply chip level timing constraints and time the whole design
3. discover violators up front
Quick Timing Models - What are they?

● QTM is a set of interactive PrimeTime commands - not a language

● Like all PrimeTime commands, QTM can be saved in a script

● QTM model can be saved in db or Stamp format

 Extracted Timing Models (ETM)

● Enable IP Reuse and interchange of timing models between EDA tools

● Compact black-box timing models
» contain timing arcs between external pins
» Internal pins only for generated/internal clocks
» models written out in Stamp, .lib ,or db formats
» context independent
» Exceptions and latches supported
» Provide huge performance improvements
Interface Logic Models (ILM)
● Enable Hierarchical STA
- Reduce memory and CPU usage for chip-level analysis
- Offer big netlist reduction if block IOs are registered
- Back-annotation and constraint files for interface logic are written out along with
netlist
● Benefits:
- High accuracy because interface logic is not abstracted
- Fast model generation time
- Context independent
- Can change load, drive, operating conditions, parasitics, SDF, constraints without re-
generating the model
 Interface Logic Models (ILM)
ILMs can be used in SDF and parasitics based flows

pt_shell> write_ilm_[sdf/parasitics] <output_file>

Support for Hierarchical SI analysis

pt_shell> create_ilm –include {xtalk_pins}

Support for Model Validation

pt_shell> compare_interface_timing <ref_file> <cmp_file>

-slack 0.2 -include slack
 Stamp Modeling
● Generally created for transistor-level designs, where there is no gate-level
netlist. Stamp timing models are usually created by core or technology
vendors, as a compiled db.

● Capabilities include the ability to model:

- pin-to-pin timing arcs
- setup and hold data
- pin capacitance and drive
- mode information
- tri-state outputs
- internally generated clocks

● Stamp models co-exist with the Library Compiler

.lib models
Chip-Level Verification using Models

● Using ILMs and ETMs to address capacity and timing issues in multi- million
gate design
Does Your Design Meet Timing?
pt_shell> report_analysis_coverage
Are You Finished?

❖ What else is there?

- Are the violations real?

- Can you explain warnings in the log files?

- What are your suggestions for resolution?

- You have a special situation – what are the issues?

Timing Verification of Synchronous Designs
Static Timing Verification of FF2: Setup
PrimeTime Terminology
Four Sections in a Timing Report
The Header
Data Arrival Section
Data Required Section
Summary - Slack
Static Timing Verification of FF2: Hold
Which Edges are Used in a Timing Report?
PrimeTime Terminology
Example Hold Timing Report
Negedge Triggered Registers: Setup Time
What About Hold Time?
Which Edges are Used in a Timing Report?
Timing Report for Hold
 Setup Definition - Summary
Data must become valid and stable at least one setup time before being captured
by flip-flop.
 Hold Definition - Summary
Data remains stable for a minimum time as required by capture flip-flop. (Hold
Check)
Timing Models
● Timing models are cells with many timing arcs:
- “Flip-flop” with setup and hold timing checks
- “Delay cell” included along the data arrival time
Example Timing Report
Asynchronous Clear/Reset Pins
Timing Report Recovery
Estimating Rnet and Cnet Pre-layout
● Extraction data of already routed designs are used to build a lookup table
called the wire load model

● WLM is based on the statistical estimates of R and C based on “Net Fanout”

Cell Delay Calculation
● Cell delays are calculated from a Non Linear Delay Model (NLDM) table in
the technology library

● Tables are indexed by input transition and total output load for each gate
Net Delay Calculation
● Net delay is the “time-of-flight” due to the net’s RC

● Net’s RC is obtained from wire load model for pre-layout design

Output Transition Calculation
● There is another NLDM table in the library to calculate output transition

● Output transition of a cell becomes the input transition of the next cell
down the chain
What About Pre and Post Layout STA?
Pre or Post Layout Timing Report
What About Negedge Triggered Registers?
What About Multi-Frequency Clocks?
What About Interface Paths: Input Ports?
What About Interface Paths: Output Ports?
Interface Paths in a Timing Report: Output
Other Timing Checks Verified by STA
Introduction to Digital VLSI Design

STA Part 2
What

● Fast and Exhaustive

● Independent of functionality or stimulus

● Spice accurate

● Implement and Verify

When
Components
Delay Calculation Timing Arcs
Delay Calculation NLDM Library
Delay Calculation NLDM Library (contd.)
Delay Calculation ECSM Library
Delay Calculation Interconnect

● IEEE Standard format – SPEF

- Distributed RC
Delay Calculation Analysis Corners

● Gate or Transistor
- P – Process (Slow, Typical, Fast)
- V – Supply Voltage
- T – Temperature

● Interconnect
- P – Process (Wide, Narrow, Tall, Short, K)
- T - Temperature
Delay Calculation Thresholds
Delay Calculation
Constraint Checking Introduction
Constraint Checking Constraint Types

● Conditions that need to be met

- Clocks
- Max allowed transition time
- Max allowed load or capacitance
- Max allowed Delay

● Boundary Settings
- Input transition time
- Output loading
- Logic settings

● Exceptions to the single cycle rule

- False paths
- Multicycle paths
Clocks

● Synchronous Designs

● Default single cycle of operation

- Launch Edge and Capture Edge

● Properties
- Period
- Waveform
- Rise/Fall Transition Time
- Skew or Uncertainty

● Generated Clocks
- Derived from a master
- Synchronous by definition
- Definite edge relationship
Virtual Clocks

● Virtual Clocks do not have any physical existence

● Virtual Clocks are used as a reference to module for input and output delays

● Virtual Clocks are local to module design

● Properties
- Period
- Waveform
Input Arrival Time
Output Required Time
Global Constraints

● Specifying min-max Cap Range

- This specification ensures that circuits used in design work within library characterization
limits

● Specifying max Transition

- This specification ensures that transition thus propagated doesn’t give rise to a bad
propagation delays

● Specifying driver-load on ports

- This specification ensures that standard load value is modeled at ports

● Specifying Input and Output Delays at Ports

Check Types

● Setup

● Hold

● Recovery

● Removal

● Clock Gating

● Min Pulse Width

● Data-to-Data
Timing Checks Setup Time and Hold Time
Timing Checks Setup Check

Data Launched by Launch Edge of FF1 Captured by Intended Capture Edge of FF2
Data launched by launch edge of FF1 should arrive at the data input of FF2 latest by
“Capture Edge Time – Setup Time of FF2”
Timing Checks Hold Check

Data launched by Launch Edge of FF1 should not be captured by an edge preceding
the intended Capture Edge of FF2, OR
Data launched by edge following Launch Edge of FF1 should not be captured by the
intended Capture Edge of FF2
Data should reach the data input of FF2 no earlier than the hold time of FF2
Timing Checks Recovery and Removal
Timing Checks Min Pulse Width

Minimum Clock Pulse Width

● Minimum High pulse width: The amount of time, after the rising edge of a clock, that the
clock signal of a clocked device must remain stable.

● Minimum Low pulse width: The amount of time, after the falling edge of a clock, that the
clock signal of a clocked device must remain stable.
Timing Checks Glitch Detection
Timing Checks Clock Gating Checks
Clock getting Checks

● Setup and hold checks are performed for the gating signal to ensure glitch-free clock.

● The clock-gating relationship depends on the functionally of the gate which is gating the
clock
Timing Checks Data-to-Data Checks
Why Data to Data Checks are required

● Constraints on asynchronous or self-timed circuit interfaces

● Constraints on signals with unusual clock waveforms that cannot be easily
specified with the create_clock command
● Constraints on skew between bus lines
● Recovery and removal constraints between asynchronous preset and clear input
pins
● Constraints on handshaking interface logic
Timing Exceptions
False Paths
- Timing Paths that are invalid
- Paths between asynchronous clocks
- Paths that are static for a particular timing mode

Multicycle Paths
- Non-default cycle operation

Logic Setting
- Pins or nets that are tied to 1/0 for a particular timing mode

Disable Timing
- Timing Arcs that are disabled
Advanced Topics
● Timing Models
- Extracted Timing Models
- Interface Logic Models
- Quick Timing Models

● Statistical Timing Analysis

Problem
Given corner data below, which combinations are expected to lead to worst and best
gate delays?

Process
Slow
Typical
Fast

Voltage
0.9V
1.0V
1.1V

Temperature
-20C
27C
105C
Introduction to Digital VLSI Design

STA Part 3
Overview
● In this era of high performance electronics, timing continues to be a top priority
and designers are spending increased effort addressing IC performance.

● Two Methods are employed for Timing Analysis:

- Dynamic Timing Analysis
- Static Timing Analysis
Dynamic Timing Analysis
● Traditionally, a dynamic simulator has been used to verify the functionality and
timing of an entire design or blocks within the design.

● Dynamic timing simulation requires vectors, a logic simulator and timing

information. With this methodology, input vectors are used to exercise functional
paths based on dynamic timing behaviors for the chip or block.

● Dynamic simulation is becoming more problematic because of the difficulty in

creating comprehensive vectors with high levels of coverage.

● Time-to-market pressure, chip complexity, limitations in the speed and

capacity of traditional simulators are all motivating factors for migration towards
static timing techniques.
Static Timing Analysis (STA)
● STA is an exhaustive method of analyzing, debugging and validating the timing
performance of a design.

● First, a design is analyzed, then all possible paths are timed and checked against
the requirements.

● Since STA is not based on functional vectors, it is typically very fast and can
accommodate very large designs (multimillion gate designs).

● STA is exhaustive in that every path in the design is checked for timing violations.

● STA does not verify the functionality of a design. Also, certain design styles are not
well suited for static approach. For instance, dynamic simulation may be required
for asynchronous parts of a design and certainly for any mixed-signal portions.
Static Timing Analysis (STA)
● STA consists of three major steps:
- Break down the design into timing paths (R-R, PI-R,PI-PO & R-PO).
- Delay of each path is calculated
- All path delays are checked against timing constraints to see if it is met.

● STA advantage
- Speed (orders of magnitude faster than dynamic simulation)
- Capacity to handling full chip
- Exhaustive timing coverage
- Vectors are not required

● STA disadvantage
- It is pessimistic (too conservative)
- Reports false paths

● Flow Inputs:
- Gate-level Verilog.
- Constraints (SDC)
- Extracted nets (SPEF)
- Libraries (liberty format - .lib)
Timing Closure
● Timing Closure is the ability to detect and fix timing problems in the design flow as
early as possible.

● This is done by checking the correctness of intermediate results through Static

Timing Analysis (STA) and also by dynamic timing simulation with SDF back
annotation.

● In case of failure - which means that the timing goals have not been achieved -
modification of timing constraints must be done through well defined loops, re-
synthesis and in worst case re-design.
Cell Timing Characterization
● Delay tables
- Generated using a detailed transistor-level circuit simulator SPICE
(differential-equations solver)

- Simulate the circuit of the cell for a number of different input slews and load
capacitances
Propagation time (50% Vdd at input to 50% at output)
Output slew (10% Vdd at output to 90% Vdd at output)
NLDM
● Cell Delay (Non-linear) = f (CL, Sin) and Sout = f (CL, Sin)
- Interpolate between table entries
- Interpolation error is usually below 10% of SPICE
Delay Calculation
Timing Path Definition
● STA tool does not report delays by net or by cell. Instead it reports by timing
paths with constraint.

● Valid timing paths:

- Primary input to Register
- Register to register
- Register to primary output
- Input to output

● Valid start of a timing path

- Clock pins of FF
- Primary inputs

● Valid end of a timing path

- Data pins of FF
- Primary output ports
- Control pin of gated clock
Path Delays
When delay paths are added, the following factors affect the delays:

- Slew propagation – Ideally, the slew propagation should be timing path specific. However,
the STA does not do this. It uses either “worst_slew” or “worst_arrival”.

- “worst_slew” – refers to using the slowest transition for signals arriving at a multi-input cell
output (fastest transition for min delay mode).
This is CTE default pessimistic behavior

- “worst_arrival” – refers to using the input signal that arrives the latest (using the earliest for
min delay mode).
Analysis Modes
● Semiconductor device parameters can vary with conditions such as fabrication
process, operating temperature, and power supply voltage.

● The STA tool supports three analysis modes:

- Single operating condition – single set of delay parameters is used for the whole circuit,
based on one set of process, temperature, and voltage conditions.

- Min-Max (BC-WC) operating condition – simultaneously checks the circuit for the two
extreme operating conditions, minimum and maximum. For setup checks, it uses maximum
delays for all paths. For hold checks, it uses minimum delays.

- On-chip-variation mode - conservative analysis that allows both minimum and maximum
delays to apply to different paths at the same time. For a setup check, it uses maximum
delays for the launch clock path and data path, and minimum delays for the capture clock
path. For a hold check, it uses minimum delays for the launch clock path and data path, and
maximum delays for the capture clock path.
Single Operating Condition
● Single set of delay parameters for the whole circuit, based on one set of process,
temperature, and voltage conditions.
Best case/Worst case Analysis
● Simultaneous checks of extreme operating conditions, minimum and maximum.

● For setup checks, it uses maximum delays for all paths.

● For hold checks, it uses minimum delays for all paths.

On-Chip Variation Analysis
● Conservative analysis that allows both minimum and maximum delays to apply to
different paths at the same time.

● For a setup check, it uses maximum delays for the launch clock path and data
path, and minimum delays for the capture clock path.

● For a hold check, it uses minimum delays for the launch clock path and data path,
and maximum delays for the capture clock path.
Derating
● Minimum and Maximum delays can be adjust by specified factors to model the
effects of operating conditions. This adjustment of calculated delays is called
derating.

● Derating affects the delay and slack values reported by report_timing.

setTimingDerate –max –early 0.8 –late 1.0
setTimingDerate –min –early 1.0 –late 1.1
Clock Reconvergence Pessimism Removal (CRPR)

● When launching and capturing clock share common path, the common path min
delay and max delay will add additional pessimism to both setup and hold
analysis.
- CRPR can be used to remove this pessimism.

setAnalysisMode –crpr –onChipVariation

set_global timing_remove_clock_reconvergence_pessimism true
Timing exceptions

● Timing exception includes the following:

- False Path- Use the set_false_path command to specify a logic path that exists in the
design but should not be analyzed. Setting a false path removes the timing constraints on
the path.

- Multiple Cycle Path - Use the set_multicycle_path command to specify the number of
clock cycles required to propagate data from the start to the end of the path.

- Min/Max Delay - Use the set_max_delay and set_min_delay commands t override the
default setup and hold constraints with specific maximum and minimum time values.
Setup/Hold Analysis (in the absence of timing exceptions)

- Setup check - verifies that the data launched from FF1 at time=0 arrives at the D input of
FF2 in time for the capture edge at time=10. If the data takes too long to arrive, it is
reported as a setup violation.

- Hold check - verifies that the data launched from FF1 at time 0 does not get propagated so
soon that it gets captured at FF2 at the clock edge at time 0. If the data arrives too soon, it
is reported as a hold violation.
Multiple Cycle Setup
● If data is launched every 3 cycles, then setup is checked against the third rising
edge (9.75) and hold is checked against next rising edge (which is CLKg1 at 6.50).

● STA tool verifies that the data launched by the setup launch edge is not captured
by the previous capture edge. So the default hold check for multi-cycle setup is
capture edge minus one.
Multiple Cycle Hold
● The number after the -hold option specifies the number of cycles to move the hold
check backward from the default position implied by the setup check.
A positive number moves the check backward by the specified number of cycles.
Specifying zero does not change the hold check time.
Recovery/Removal check
● Timing checks which are related to asynchronous input pin of a flip flop.

● Although a flip-flop is asynchronously set or clear , the negation from its reset
state is synchronous .

● A recovery timing check specifies a minimum amount of time allowed between the
release of a asynchronous signal from the active state to the next active clock
edge .

● A removal timing check specifies the minimum amount of time between an active
edge and the release of an asynchronous control signal.
Case Analysis
● Case analysis allows timing analysis to be performed using logic constants or logic
transitions (rising or falling) on ports or pins, to limit the signal propagated
through the design.

● Case analysis is a path-pruning mechanism and is most commonly used for timing
the device in a given operational configuration or functional mode. For example,
case analysis can be used to compare normal circuit operation against scan or
BIST operation.
Timing Models
● Timing extraction plays an important role in hierarchical top-down flow and
bottom-up IP authoring flow by reducing the complexity of timing verification and
by providing a level of abstraction which hides the implementation details of IP
blocks.

● Three most desired features in timing extraction are accuracy, efficiency, and
usability. The model must preserve the timing behavior of the original circuit and
produce accurate results.

● Three types of models can be generated:

Quick Timing Model (QTM)
Extracted Timing Model (ETM)
Interface Logic Model (ILM)
QTM
● A temporary model used early in the design cycle for a block that has no netlist
available. QTM creation is faster than writing ad-hoc model . The model contains
both min and max time arc for setup and hold checks.

● Check consistency between blocks’ constraints and updates boundary

constraints (after each iteration of synthesis) The netlist used for
QTM generation can be easily generated (low effort RTL mapping) since
existence or absence of timing arc is independent from the logic/physical design.

● Inputs
- Constraints (SDC)
- Configuration file
- Header file

● The QTM model is generated using Black Box commands.

Using this command set allows to define timing arcs and electrical data (i.e. output
driver, input load,…)
ILM
● ILMs embody a structural approach to model generation, where the original gate-
level netlist is replaced by another gate-level netlist that contains only the
interface logic of the original netlist.

● Interface logic contains all circuitry leading from I/O ports to edge- triggered
registers called interface registers. The clock tree leading to interface registers is
preserved in an ILM. Logic that is only contained in register-to-register paths on a
block is notin an ILM.
ETM
● Extracted timing models differ from
ILMs in that the interface logic for a
block is replaced by context-
independent timing relationships
between pins on a library cel

● The extracted library cell contains

timing arcs between external pins.
Internal pins a introduced only when
there are clocks defined on internal
pins of the design
Analysis Modes
Analysis Modes