Module 3

Combinational Logic Circuits

 SYLLABUS
Module - 3
Design Procedure & Implementation of combinational logic
circuits, Binary adders and Subtractors
Binary Parallel adder
Carry look ahead adder
BCD adder
Code converter
Magnitude comparator
Decoder – Demultiplexer
Encoder – Multiplexer
Parity generator/Checker
 INTRODUCTION
• Logic circuits are electronic circuits that use logical operations
to process information.
• They are basic building blocks of digital electronics, including
computers and other digital devices.
• Logic circuits can be used for a wide range of tasks, such as
data processing, control, and communication.
• There are several different types of logic circuits, including
Boolean logic circuits, combinational logic circuits, and
sequential logic circuits.
• Boolean logic circuits use logical operators such as AND, OR,
and NOT to process information.
 Introduction

• A combinational circuit consists of logic gates whose outputs

at any time are determined directly from the present

combination of inputs without regard to previous inputs.

• A combinational circuit performs a specific information-

processing operation fully specified logically by a set of

Boolean functions.
 Introduction

• Sequential circuits employ memory elements (binary cells) in

addition to logic gates. Their outputs are a function of the

inputs and the state of the memory elements. The state of

memory elements, in turn, is a function of previous inputs.

• As a consequence, the outputs of a sequential circuit depend

on present inputs as well as past inputs, and the circuit

behavior must be specified by a time sequence of inputs and

internal states.
 Block diagram of a combinational circuit

• Both input and output data are represented by binary signals, i.e., they exist in two
possible values, one representing logic-l and the other logic-0.
• Input – Excitation; Output - Responses
 Design Procedure
• The design of combinational circuits starts from the
verbal outline of the problem and ends in a logic
circuit diagram or a set of Boolean functions from
which the logic diagram can be easily obtained.
• A truth table for a combinational circuit consists of
input columns and output columns. The l's and O's in
the input columns are obtained from the 2 n binary
combinations available for n input variables.
• The binary values for the outputs are determined from
examination of the stated problem.
• An output can be equal to either 0 or 1 for every valid
input combination. However, the specifications may
indicate that some input combinations will not occur.
These combinations become don't-care conditions.
• The output functions specified in the truth table give
the exact definition of the combinational circuit.
• It is important that the verbal specifications be
interpreted correctly into a truth table. Sometimes the
designer must use intuition and experience to arrive at
the correct interpretation.
• Any wrong interpretation that, results in an incorrect
truth table produces a combinational circuit that will
not fulfill the stated requirements
• The output Boolean functions from the truth table are simplified
by any available method, such as algebraic manipulation, the map
method, or the tabulation procedure.
• Usually, there will be a variety of simplified expressions from
which to choose.
• However, in any particular application, certain restrictions,
limitations, and criteria will serve as a guide in the process of
choosing a particular algebraic expression.
• A practical design method would have to consider such constraints
as
(I) minimum number of gates,
(2) minimum number of inputs to a gate,
(3) minimum propagation time of the signal through the circuit,
(4) minimum number of interconnections, and
(5) limitations of the driving capabilities of each gate.
A combinational circuit that perform the addition of 2 bits is called half adder.
(Adding 2 1-bit numbers)
The one that perform addition of 3 bits are called full adder.
Using Only NAND gate
Using Only NOR Gates
The full adder adds the bits A and B and the carry from the previous column called carry in C in
Using AOI Gates
 Using Half Adders
S = A’B’Cin + A’BC’in + AB’C’in + ABCin
= Cin (A’B’ + AB) + C’in (A’B + AB’)
=Cin (A’B + AB’)’ + C’in (A’B + AB’)
=Cin (A B )’ + C’in (A B )
C (A B )
= in
 Using Half Adders
• C= A’BCin + AB’Cin + ABC’in + ABCin
= Cin (A’B + AB’) + AB(C’in + Cin)
=Cin (A B ) + AB
Using Half Adders
 Disadvantage
• Even though, a full adder can be constructed
using two half adders, the disadvantage is that
the bits must propagate through several gates
in succession, which makes the total
propagation delay greater than that of the full
adder circuit using AOI logic
A combinational circuit that perform the subtraction of 2 bits is called half
subtractor.(Difference of 2 1-bit numbers)
The one that perform subtraction of 3 bits are called full subtractor.
 Binary Parallel adder
• The Parallel binary adder is a combinational circuit that adds two
binary numbers in parallel form and produces the arithmetic sum of those
numbers in parallel.

• It consists of full adders connected in a chain. with the output carry from
each full-adder connected to the input carry of the next full-adder in the
chain.

• The number of full adders in a parallel binary adder depends on the number
of bits present in the number for the addition.

• If 2-bits numbers are to be added, then there will be 2-full adder in the
parallel binary adder.
 Addition of 2 -bit
• When one binary number is added to another, each
column generates a sum bit and a 1 or 0 carry bit to
the next column to the left.
• To add two binary numbers, a full-adder (FA) is
required for each bit in the numbers.
• for 2-bit numbers, two adders are needed; for 4-bit
numbers, four adders are used; and so on.
 Addition of 2 -bit
The carry output of each adder is connected to the carry input of
the next higher-order adder

Notice that either a half-adder can be used for the least significant
position or the carry input of a full-adder can be made 0
(grounded) because there is no carry input to the least significant
bit position.
 Exercise 1
• Determine the sum generated by the 3-bit
parallel adder and show the intermediate
carries when the binary numbers 101 and 011
are being added.
4- bit Parallel Adder
 4- bit Parallel Adder
• The interconnection of four full-adder (FA) circuits to provide a 4-bit
parallel adder.

• The augend bits of A and addend bits of B are designated by subscript

numbers from right to left, with subscript 1 denoting the lower –order bit.
• The carries are connected in a chain through the full-adders. The input
carry to the adder is C0 and the output carry is C4.
• The Σ output along with the last carry, C4 generates the required sum bits.
 Binary Parallel adder- Another
Representation

C out
 4-bit Full-adder
• When the 4-bit full-adder circuit is enclosed within an IC
package, it has four terminals for the augends bits, four
terminals for the addend bits, four terminals for the sum
bits, and two terminals for the input and output carries.
 Types of Parallel Adders
• The parallel adders can be placed into two categories
based on the way in which internal carries from stage to
stage are handled.
• Ripple carry and look-ahead carry(Carry look-ahead
adder).
• Externally, both types of adders are the same in terms of
inputs and outputs.
• The difference is the speed at which they can add
numbers.
• The carry look-ahead adder is much faster than the ripple
carry adder.
 RIPPLE CARRY ADDER:
• In the parallel adder, the carry –out of each stage is connected to the carry-in of the
next stage.
• The sum and carry-out bits of any stage cannot be produced, until sometime after the
carry-in of that stage occurs.
• This is due to the propagation delays in the logic circuitry, which lead to a time delay
in the addition process.
• The carry propagation delay for each full adder is the time between the
application of the carry-in and the occurrence of the carry-out.
• The parallel adder in which the carry-out of each full-adder is the carry-in
to the next most significant adder is called a ripple carry adder.
• The greater the number of bits that a ripple carry adder must add, the greater the time
required for it to perform a valid addition.
• If two numbers are added such that no carries occur between stages, then the add
time is simply the propagation time through a single full-adder.
 RIPPLE CARRY ADDER

Full-adder 1 (FA1) cannot produce a potential output carry until an input carry is
applied. Full-adder 2 (FA2) cannot produce a potential output carry until FA1
produces an output carry and so on.
 Why Ripple Carry Adder is Called So?

• In Ripple Carry Adder, the carry out produced

by each full adder serves as carry-in for its
adjacent most significant full adder.
• Each carry bit ripples or waves into the next
stage.
• That’s why, it is called as “Ripple Carry
Adder”.
 Disadvantages of Ripple Carry Adder-

• Ripple Carry Adder does not allow to use all the full
adders simultaneously.
• Each full adder has to necessarily wait until the carry bit
becomes available from its adjacent full adder.
• This increases the propagation time.
• Due to this reason, ripple carry adder becomes extremely
slow.
 Carry Look ahead Adder
• Carry Look Ahead Adder is an improved version of the
ripple carry adder.
• It generates the carry-in of each full adder simultaneously
without causing any delay.
• It examines all the input bits simultaneously and also
generates the carry-in bits for all the stages simultaneously.
• The look-ahead carry adder anticipates the output carry of
each stage, and based on the inputs, produces the output
carry by either carry generation or carry propagation.
• Carry generation occurs when an output carry is produced (generated) internally
by the full-adder. A carry is generated only when both input bits are 1s. The
generated carry, Cg, is expressed as the AND function of the two input bits, A and
B.
Cg = AB
• Carry propagation occurs when the input carry is rippled to become the output
carry. An input carry may be propagated by the full-adder when either or both of
the input bits are 1s. The propagated carry, Cp, is expressed as the OR function of
the input bits.
Cp = A B

• The conditions for carry generation and carry propagation are illustrated in Figure
6–15. The three arrowheads symbolize ripple (propagation).
Illustration of conditions for carry generation and carry
propagation
 propagate

• The output carry of a full-adder can be expressed in terms of both the

generated carry (Cg) and the propagated carry (Cp).
The output carry (Cout) is a 1 if the generated carry is a 1 OR if the
propagated carry is a 1 AND the input carry (Cin) is a 1. In other words,
we get an output carry of 1 if it is generated by the full-adder (A = 1 AND
B = 1) or if the adder propagates the input carry (A = 1 OR B = 1) AND
Cin = 1. This relationship is expressed as

Cout = Cg + CpCin
• For each full adder, the output carry is dependent on the
generated carry (Cg), the propagated carry (Cp), and its
input carry (Cin).
• The Cg and Cp functions for each stage are immediately
available as soon as the input bits A and B and the input carry
to the LSB adder are applied because they are dependent only
on these bits.
• The input carry to each stage is the output carry of the
previous stage.
• Based on this analysis, we can now develop expressions for
the output carry, Cout, of each full-adder stage for the 4-bit
example.
• Advantages of Carry Look-ahead Adder
• In this adder, the propagation delay is reduced.
• The carry output at any stage is dependent
only on the initial carry bit of the beginning
stage.
• Using this adder it is possible to calculate the
intermediate results. This adder is the fastest
adder used for computation.
 BCD Adder

• The digital systems handles the decimal number in

the form of binary coded decimal numbers (BCD).
• A BCD Adder Circuit that adds two BCD digits and
produces a sum digit also in BCD.
• Each BCD digit is represented as a 4-bit binary
number.
• BCD numbers use 10 numbers, 0 to 9 which are
represented in the binary form 0 0 0 0 to 1 0 0 1.
• eg of BCD
• BCD cannot be greater than 9.
• The addition of two BCD numbers, considering the
three cases that occur
– 1. Sum Equals 9 or less, with carry 0

The addition is carried out as in normal binary addition

• Sum greater than 9 ,with carry 0

The sum 1 1 1 0 is an invalid BCD number. This has occurred because the
sum of the two digits exceeds 9. Whenever this occurs the sum has to be
corrected by the addition of six (0110) in the invalid BCD number,
Sum equals or less than 9, with carry 1
• Let us consider addition of 8 and 9 in BCD

To get the correct BCD result correction factor of 6 has to be added to the least significant digit
sum,
• we can summarize the BCD addition procedure as
follows :
– Add two BCD numbers using ordinary binary addition.
– If four-bit sum is equal to or less than 9, no correction is
needed. The sum is in proper BCD form.
– If the four-bit sum is greater than 9 or if a carry is
generated from the four-bit sum, the sum is invalid.
– To correct the invalid sum, add 01102 to the four-bit sum.
If a carry results from this addition, add it to the next
higher-order BCD digit.
• Thus to implement BCD Adder Circuit we require :
– 4-bit binary adder for initial addition
– Logic circuit to detect sum greater than 9 and
– One more 4-bit adder to add 01102 in the sum if sum is
greater than 9 or carry is 1.
K- Map for sum>9

The above equation represents the condition when sum >9. When we add C out to this sum
, we get the representation for both the invalid choices.(i.e. sum>9 and carry =1)

Y= S3S2 + S3S1 + Cout

With this design information we can draw the BCD Adder Block Diagram
0110
• the two BCD numbers, together with input carry, are first added in the top 4-bit binary adder to produce a binary sum.
When the output carry is equal to zero (i.e. when sum ≤ 9 and Cout = 0) nothing (zero) is added to the binary sum.

When it is equal to one (i.e. when sum > 9 or Cout = 1), binary 0110 is added to the binary sum through the bottom 4-bit binary adder.
The output carry generated from the bottom binary adder can be ignored, since it supplies information already available at the
output-carry terminal.
 Binary to Gray Code Converter

• What is Gray Code?

– Also known as Cyclic Code, Reflected Binary Code (RBC),
Reflected Binary.
– each incremental value can only differ by one bit.
– two adjacent code numbers differ from each other by
only one bit.
– it is not suitable for arithmetic operations.
– applications in analog to digital converters, as well as
being used for error correction in digital communication.
How to Convert Binary to Gray Code
• The MSB (Most Significant Bit) of the gray code will be
exactly equal to the first bit of the given binary number

• The second bit of the code will be exclusive-or (XOR) of the

first and second bit of the given binary number, i.e if both
the bits are same the result will be 0 and if they are
different the result will be 1.(Counting of bits from MSB to
LSB)

• The third bit of gray code will be equal to the exclusive-or

(XOR) of the second and third bit of the given binary
number. Thus the binary to gray code conversion goes on.
Example
Step 1: Draw the conversion table(truth table) showing
relationship between inputs and outputs
Step 2: For each output variable, draw the K-map to
determine the simplified Boolean expression.
Simplified Boolean Expressions
 Step 3: realize the code converter using the logic gates

• The logical circuit which converts the binary code to

equivalent gray code is known as binary to gray
code converter.
 Gray to Binary Code Converter

• The input is gray code and output is its equivalent

binary code.
• Gray Code to Binary Conversion
• The MSB of the binary number will be equal to the
MSB of the given gray code.
• Now if the second gray bit is 0, then the second binary
bit will be the same as the previous or the first bit. If
the gray bit is 1 the second binary bit will alter. If it
was 1 it will be 0 and if it was 0 it will be 1.
• This step is continued for all the bits to do Gray code
to binary conversion.
• Application of Gray Code
– The main applications include being used in analog to
digital converters, as well as being used for error
correction in digital communication.
– Gray code is used to minimize errors in converting
analog signals to digital signals.
The gray code to binary converter circuit
binary to BCD code converter
• 10- 0001 0000
• 11-0001 0001
• 12 -0001 0010
• 13- 0001 0011
• 14 -0001 0100
• 15 0001 0101
 4-bit BCD to Excess-3 Code Converter

• The excess-3 code (or XS3) is a non-weighted code

used to express code used to express decimal
numbers.
• The Excess-3 code can be calculated by adding 3.
• You can add 0011 to each four-bit group in binary
coded decimal number (BCD) to get desired excess-
3 equivalent.
• There are the following steps to convert the
binary number into Excess-3 code:
• Convert the binary number into decimal.
• Add 3 in each digit of the decimal number.
• Find the binary code of each digit of the newly
generated decimal number.
• Example 1: Convert (11110)2 to Excess-3 using binary
• First, convert the given binary number into a decimal
number.
• BCD Number: (0011 0000)2 =30
• 2. Now, we add 3 in each digit of the decimal number.
• The decimal number is 30. Now, we will add 3 into the
decimal number 30.
• = 30+33 = 63
• Now, we find the binary code of each digit of the decimal
number 63.
(0110)2 (0011)2 =(01100011)Excess-3
Truth Table
• Using the Truth Table the boolean expressions
obtained are
• A > B : AB'
A < B : A'B
A = B : A'B + AB’
 PARITY GENERATOR OR CHECKER
• What is Parity Bit
– The parity generating technique is one of the most
widely used error detection techniques for the data
transmission.
– In digital systems, when binary data is transmitted and
processed, data may be subjected to noise so that such
noise can alter 0s (of data bits) to 1s and 1s to 0s.
• a Parity Bit is added to the word containing data in
order to make number of 1s either even or odd.
• The message containing the data bits along with
parity bit is transmitted from transmitter to the
receiver.
• At the receiving end, the number of 1s in the
message is counted and if it doesn’t match with the
transmitted one, it means there is an error in the
data. Thus, the Parity Bit it is used to detect errors,
during the transmission of binary data.
 Parity Generator and Checker
• Parity Generator is a combinational logic circuit
that generates the parity bit in the transmitter.
• a circuit that checks the parity in the receiver is
called Parity Checker.
• Even Parity and Odd Parity
– The sum of the data bits and parity bits can be even or
odd.
– In even parity, the added parity bit will make the total
number of 1s an even number
– in odd parity, the added parity bit will make the total
number of 1s an odd number.
• The basic principle involved in the implementation
of parity circuits is that sum of odd number of 1s is
always 1 and sum of even number of 1s is always
0.
• Parity Generator
– Parity Generator
• It is combinational circuit that accepts an n-1 bit data and
generates the additional bit that is to be transmitted with the
bit stream.
• This additional or extra bit is called as a Parity Bit.
– In even parity bit scheme, the parity bit is ‘0’ if there
are even number of 1s in the data stream and the parity
bit is ‘1’ if there are odd number of 1s in the data
stream.
• In odd parity bit scheme, the parity bit is ‘1’ if there
are even number of 1s in the data stream and the
parity bit is ‘0’ if there are odd number of 1s in the
data stream.
• Even Parity Generator
– Let us assume that a 3-bit message is to be transmitted
with an even parity bit.
– Let the three inputs A, B and C are applied to the circuit
and output bit is the parity bit P.
– The total number of 1s must be even, to generate the
even parity bit P.
the truth table of even parity generator
 Odd Parity Generator
• Let us consider that the 3-bit data is to be
transmitted with an odd parity bit.
• The three inputs are A, B and C and P is the output
parity bit.
• The total number of bits must be odd in order to
generate the odd parity bit.
P = A ⊕ (B ⊕ C)
 Parity Check

• It is a logic circuit that checks for possible errors

in the transmission.
• This circuit can be an even parity checker or odd
parity checker depending on the type of parity
generated at the transmission end.
• When this circuit is used as even parity checker,
the number of input bits must always be even.
 Even Parity Checker

• Consider that three input message along with even

parity bit is generated at the transmitting end.
• These 4 bits are applied as input to the parity
checker circuit, which checks the possibility of
error on the data.
• Since the data is transmitted with even parity, four
bits received at circuit must have an even number
of 1s.
• If any error occurs, the received message consists
of odd number of 1s. The output of the parity
checker is denoted by PEC (Parity Error Check).
• The below table shows the truth table for the Even
Parity Checker in which PEC = 1 if the error occurs,
i.e., the four bits received have odd number of 1s
and PEC = 0 if no error occurs, i.e., if the 4-bit
message has even number of 1s.
truth table can be simplified using K-map
 logic expression for the even parity checker can be implemented by
using three Ex-OR gates as shown in figure. If the received message
consists of five bits, then one more Ex-OR gate is required for the even
parity
 Odd Parity Checker
• Consider that a three bit message along with odd
parity bit is transmitted at the transmitting end.
• Odd parity checker circuit receives these 4 bits and
checks whether any error are present in the data.
• If the total number of 1s in the data is odd, then it
indicates no error, whereas if the total number of 1s
is even then it indicates the error since the data is
transmitted with odd parity at transmitting end.
 Applications of Multiplexers

• Communication System
– A communication system has both a communication
network and a transmission system. By using a
multiplexer, the efficiency of the communication
system can be increased by allowing the transmission of
data, such as audio and video data from different
channels through single lines or cables.
• Computer Memory
– Multiplexers are used in computer memory to maintain
a huge amount of memory in the computers, and also to
reduce the number of copper lines required to connect
the memory to other parts of the computer.
• Telephone Network
– In telephone networks, multiple audio signals are
integrated on a single line of transmission with the help
of a multiplexer.
 Demultiplexer
• The data distributor, known more commonly as
a Demultiplexer or “Demux” for short, is the exact
opposite of the Multiplexer .
• The demultiplexer takes one single input data line
and then switches it to any one of a number of
individual output lines one at a time.
 1-to-2 Demultiplexer

• A 1-to-2 demultiplexer consists of one input line,

two output lines and one select line.
• The signal on the select line helps to switch the
input to one of the two outputs.
• When the select input is LOW, then the input will be
passed to Y0 and if the select input is HIGH, then
the input will be passed to Y1.
1-to-8 Demultiplexer
• Applications of Demultiplexer
• Communication System
– Mux and demux both are used in communication
systems to carry out the process of data transmission. A
De-multiplexer receives the output signals from the
multiplexer and at the receiver end, it converts them
back to the original form.
• Arithmetic Logic Unit
– The output of the ALU is fed as an input to the De-
multiplexer, and the output of the demultiplexer is
connected to multiple registers. The output of the ALU
can be stored in multiple registers.
• Serial to Parallel Converter
– This converter is used to reconstruct parallel data. In this
technique, serial data is given as an input to the De-
multiplexer at a regular interval, and a counter is
attached to the demultiplexer at the control input to
detect the data signal at the output of the demultiplexer.
When all data signals are stored, the output of the
demux can be read out in parallel.
 Solved problem #1
Implement the Boolean expression F(A, B, C) = ∑ m(2,
3, 6, 7) using a multiplexer.
• Solution:
• There are 3 variables in the given expression, hence
2n = 23 = 8 : 1 multiplexer. So, the mux has 8 input
lines, 3 selection lines, and one output.
• The inputs, corresponding to the minterms (2, 3, 6,
7) are connected to logic 1 and the remaining terms
to logic 0(grounded).
Implementation of 2 input AND gate using 2 : 1 Mux
• Or
C
D0

D1
D2 4:1

D3

S0 S1
A B C
Binary to octal converter
Questions
1. Implementation of OR gate using 2 : 1 Mux using “n-1”
selection lines.
2.use mux to implement the logic function
F= A⊕ B ⊕C
3.Use a de mux to implement the function f1=Σ(1,5,7) f2
=Σ(3,6,7)
4.Implement the function f(w,x,y,z)=Σ(1,4,6,7,8,9,10,11,15)
using 8:1 mux