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Introduction Verilog - MODULE 4

The document discusses the history and structure of Verilog, a hardware description language. It describes how Verilog modules are structured, including ports, operators, data types and provides examples of each.

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rohitrajww4
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21 views

Introduction Verilog - MODULE 4

The document discusses the history and structure of Verilog, a hardware description language. It describes how Verilog modules are structured, including ports, operators, data types and provides examples of each.

Uploaded by

rohitrajww4
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Introduction verilog

Hardware Description Language(HDL)


• It is a computer-aided design tool for the modern design
and synthesis of digital systems.
• The advances in semiconductor technology continue to
increase the power and complexity of digital systems.
• Due to their complexity, such systems cannot be realized
using discrete integrated circuits.
• They are realized using high density, programmbale chip
such as Application-specific integrated circuits (ASICs) and
Field-Programmable Gate Arrays (FPGA) and require
sophisticated CAD tools.
Hardware Description Language
• HDL is an integral part of such tools
• HDL offers the designer a very efficient tool for
implementing and synthesizing design on chips.
• Debugging the design is easy, since HDL packages
implement simulators and test benches.
• Two widely used Hardware description languages
are:
1. VHDL
2. Verilog
History of Verilog
• Gateway Design Automation developed a
hardware description language for its newly
introduced logic simulator, Verilo-XL.
• Cadence made verilog available as public
domain, with the intention that it should
become a standard, nonproprietary language.
• Verilog HDL becomes the standard IEEE
version.
Structure of HDL Module
• HDL module follows the general structure of
software languages such as C.
• The module has a source code that is written
in high level language style.
• Entity: Example Half_Adder is a name defined
by the user nad does not convey any
information about the system.
Structure of Verilog Module
• The verilog module has a declaration and a
body.
• In the declaration name, inputs and outputs of
the module are listed.
• The body shows the relationship between
inputs and outputs.
• Verilog is case sensitive.
Structure of Verilog Module
• Example:
Structure of Verilog Module
Structure of Verilog Module
Verilog ports
• Verilog ports can be any one of the following three
modes:
1. input: It is an input port. This port should appear
only on the right-hand side of the statement.(i.e the
port is read)
2. output: It is an output port. The output port can
appear on either side of the assignment statement.
3. inout: This port can be used as both inptu and
output. It represents the bidirectional bus.
OPERATORS
• Logical: AND, OR and XOR
• Relational: Express relation between the
objects. It includes equality, Inequality, less
than, less than or equal, greater than or
greater than or equal.
• Arithmetic
• Shift: To move the bits of an object in a certain
direction, right or left
Verilog Bitwise Logical Operators
Verilog Boolean logical operators
• Opeartor: &&, ||
• Operation: AND, OR
• Number of operands: two
• These operators operate on two operands and
the result is false (0) and true(1)
• !x… ! Negation operator
Relational Operators
• Compare the values of two objects
• These operators operate on two operands and
the result is false (0) and true(1)
Verilog Relational Operators
Verilog Arithmetic Operators
Verilog Shift Operators
Verilog Data Types
• Nets:
It is declared by the predefined word wire.
It supports 4 values
Value Definition Example:
0 Logic 0 (false)
wire sum;
1 Logic 1 (true)
X unknown wire S1 = 1’b0;
z High impedance
Verilog Data Types
Registers:
• It store values until they are updated.
• It is a data storage elements.
• It is declared by the predefined word reg.
• It supports 4 values of register.
Value Definition
0 Logic 0 (false)
1 Logic 1 (true)
X unknown
z High impedance
Verilog Data Types
• Vectors:
• Vectors are multiple bits
• Register or net can be declared as a vector
• Vectors are declared by brackets
Examples:
Wire [3:0]a=4’b1010;
Reg[7:0]total=8’d12;
Verilog Data Types
Integers:
• It is defined by a predefined word integer.
Real:
• Real (floating-point) numbers are declared
with predefined word real.
• Example:
1. 2.4,56.3 and 5e12(5*10^12)

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