Engineering Science:

Sequential logic
Author: David Martínez Antón
Contact
Email: [email protected]
 Sequential logic: introduction
Sequential logic can be described as a type of logic circuits whose outputs depends not only on the
present values of its inputs signals but also on the sequence of past outputs. This is in contrast to
combinational logic, whose outputs depends only of the present inputs. This means that sequential
logic has state (memory) while combinational does not:
Basic sequential
Basic combinational logic scheme
logic scheme
 S-R and R-S Latches:
Latches are a temporal storage device of two states that can remain in any of their two states thanks
to their “feedback”, due to the fact that each of their outputs are connected to their inputs. Flip-
flops and latches can be considered as the building blocks of computer memory.
SR and RS latches, can be thought of a “1 bit memory”. The circuits remember the state until it is
triggered by another input pulse or until the power is removed, this is why this type of circuits are
known as a bistable latch. In order to understand this type of devices we must first remember the
behavior of an or gate and an and gate and their truth tables:

Or gate truth And gate truth

table table
To consider:
A B Output A B Output
R-S stands for
0 0 0 0 0 0 “Reset-Set”
0 1 1 0 1 0
1 0 1 1 0 0
1 1 1 1 1 1
 S-R and R-S Latches (II):
If we add a negated logic gate to each of these two, we can swap the “0” in the output into ones
and vice versa. Remember that these combination of logic gates already exist, they have their own
name and their own truth table: NOR and NAND gates.

NOR gate truth NAND gate

table truth table
A B Output A B Output
0 0 1 0 0 1
0 1 0 0 1 1
1 0 0 1 0 1
1 1 0 1 1 0

To consider: the S-R and R-S latches

can be build using either NOR or
NAND gates
 R-S latch: how it works
An R-S latch can be built out of NOR gates. The output of each NOR gated is connected in such a
way that it is also the input of the other, which results in a positive feedback. The R-S latch has two
inputs, “R” and “S” and the output “Q”. The Output “” is going to be the opposite of the output “Q”.
The starting state here is that “R” and “S” are “0”, and “Q” is “1” so “” is “0”:
Starting state:
NOR gate truth
table
A B Output
0 0 1
0 1 0
1
1 0 0
1 1 0

To consider: because “Q”

Let’s consider an “starting is “1”, the latch is currently
state” like this one: “S” and “R” storing “1”
“0” and “Q” being “1”
 R-S latch: how it works (II), resetting the
latch
Now let’s consider that we apply a pulse to “R”. Since in the truth table of a “NOR” gate, the input
“1” implies that the output is going to forcibly be “0”. This “0” is feed back into the lower gate,
resulting in a “1” output for “”. The output of “” is feed back into the upper gate, but it does not
change the output, it is still “0”. The pulse that was applied to reset the “R-S latch” is now removed,
but the output of the top “NOR” gate remains the same, with the value “0”, but the output “Q” is
now “0” so the latch is now storing a “0”:

NOR gate truth

table
A B Output 2 3
0 0 1
0 1 0
1 0 0
1 1 0
 R-S latch: how it works (III), setting the latch
In order to set the output “Q” to the value “1” again, we must apply a pulse to the “S” input. Pay
attention at how the changes are propagated through the entire circuit. Remember that an input
“1” in a R-S latch built from “NOR” gates, is going to force the corresponding output to be a “0”. The
set pulse is now removed and as we can see the circuit is now latched into a set state, storing a “1”
again in the output “Q”:

Remember: “S” stands

for “Set” and “R” for
reset
4 5

To consider: to better understand

these propagations, check the
truth table of the “NOR” gate
 R-S latch: how it works (IV)
Notice that if another “Set” pulse is applied, it has no effect on the circuit, the outputs remain the
same. Applying a set pulse for “S” will always force the latch into a “set state” regardless of the
previous state of the latch. Similarly, applying a pulse for “R” will always force the latch into a “reset
state”. Notice that “R” and “S” are never left high at the same time. The latch is controlled by
pulses only. Then we have the following truth table: when both “S” and “R” are set to “0”, the
outputs may be “1” or may be “0”, depending on the previous state of the circuit. The “reset” pulse
is applied

7 8
6
 R-S latch: how it works (V)
Now the “Reset” pulse is removed, the latch is currently storing a “0” for “Q”, both “R” and “S” are
“0” again, and output “Q” remains in “0” and its inverse “” is “1”. A set pulse is applied, “S” is “1”
and “R” is “0”, the output “Q” becomes “1” and “” becomes “0”.

10
9 11
 R-S latch: how it works (VI), forbidden state
The set pulse is removed, “Q” is “1” and “” is “0”. The only circumstance that have not been
considered is when both inputs “R” and “S” are set to “1” at the same time. If this will to occur, we
will be telling the latch to set the value “1” and “0” simultaneously, but in reality “Q” will become
“0” and “” will also become “0”. This will sort itself out if one of the inputs fell to “0” before the
other, for example, if “R” fell to “0” first with “S” still “1” then “Q” will become “1”again. If however,
both inputs are at “1” and both fell to “0” at the same time, we have what it is known as a race
condition between the two gates, since they will be racing each other to feed back their new
output, being impossible to know which one will “win”.

Forbidden state for R-S latch

To consider:
S R Q if both inputs
0 1 are high, the
0 0 next state can’t be
1 0
determined. This
0 1 0 1
is a state that the
1 0 1 0 latch should never
1 1 0 0 be in
 R-S latch: how it works (VII) summary
To consider: so this type of R-S latch is known as an “active-high SR latch”, because the normal condition
for inputs “S” and “R” is low, and a high pulse at one of these inputs is required to change the
state of the latch:
NOR gate truth
“Active-high” SR latch table
S R Q
0 1 A B Output
0 0
1 0 0 0 1
0 1 0 1 0 1 0
1 0 1 0 1 0 0
1 1 0 0 1 1 0

Remember:
S=1 and R=1 To consider:
is the invalid state • Normal condition
for an R-S latch • Forbidden state
 S-R latch: how it works
The wiring of an S-R latch is the same as the R-S latch, but now it is build out of “NAND” gates and
the “S” input is located at the top while the “R” is at the bottom. Notice that the output truth table
now is different from the one in the “R-S latch”. In this type (“S-R latch”), “S” and “R” are kept high
most of the time.
NAND gate
“Active-low” SR latch truth table
A B Output S R Q

0 0 1 0 0 1 1

0 1 1 0 1 1 0

1 0 1 1 0 0 1
1 1 0 0 1
1 1
1 0

To consider: To consider: now the “prohibited

• Normal condition state” for this type of latch
• Forbidden state is when both inputs “S” and “R”
are 0
 S-R latch: how it works (II) setting the latch
Let’s consider a starting state where both inputs “S” and “R” are “1” and output “Q” is “0”. Now
when input “S” is made low momentarily, in other words, when it becomes “0”, the output “Q” is
forcibly going to be “1” (check the “NAND” gate truth table if you have doubts), so the latch is now
storing a “1” since the output “Q” is now storing a “1”. “S” now returns to its normal high state “1”
and the output “Q” and “” and the input “R” remain with the same value:
Starting state:

3
1 2
 S-R latch: how it works (III) resetting the
latch
When “R” is set low momentarily, the output “” is forcibly going to be a “1”, this is feed back into
the inputs of the top “NAND” gate, being the output “Q” “0”. “R” can then return to its normal high
value and the latch is now storing a “0” again

To consider: an “S-R latch”

built from “NAND” gates is
4 5 more explicitly known as
“active-low S-R latch”
 S-R latch: how it works (IV) forbidden state
An “S-R latch” also has a forbidden state, it occurs when both “S” and “R” are simultaneously “0”,
which will result in an illegal state in which both “Q” and its complement “” are “1”

To consider: Forbidden state for S-R latch

S-R and R-S latches are said
to be level-sensitive, which
means that it will respond S R Q
to a valid change in either 0 0 1 1
“S” or “R”, regardless of the
0 1 1 0
duration of the input pulse.
It is the level, high or low 1 0 0 1
that matters, not how long 0 1
it is applied for 1 1
1 0
 S-R latches: application, “switch-bounce
suppression”
When a mechanical switch is pressed, it may generate several electrical signals in a fraction of a
second, when only one signal is required. This effect is known as “switch-bounce” These produce
some signal voltage peaks that may be unacceptable on a digital system. An S-R latch can be used
to suppress this effect then. It can be used to allow a clean interfacing between for example a
mechanical switch and the digital circuit that is controlling:

2
1 To consider: then the S-R
latch will ignore any
further set signals after it
has already been set
To consider: when the switch connects
input “S” to earth, it will make it low
3
thereby changing the output “Q” of the
S-R latch from low to high
 S-R latch: chronogram exercise
Provided the following “time-chart” (chronogram), find the corresponding square wave of the
output “Q”. Consider the starting state of “Q” as “0”:

Q
 S-R latch: chronogram exercise solution
S-R latch circuit scheme

Since it is an “S-R latch”, it

is going to be build out of
NAND gate “NAND” gates
truth table
A B Output
0 0 1
0 1 1 S
1 0 1
1 1 0
R

Q
Gated R-S latch: introduction and application
A gated set-reset latch is an SR latch that can only change state while it is enabled. Application: an
application of the “gated SR latch” could be for example used in an air conditioning system in a
building, each room could have its own cooling unit controlled independently by its own SR latch,
coming from a temperature sensor the “Set” and “Reset” signals, or a humidity sensor in the room.
Since these are gated SR latches, a control panel could be used to enable or disable the switching
“on” and “off” of these units on a room-by-room basis:
To consider: the input
Abstraction symbol Gated R-S latch “E” can be used to enable
of a “gated S-R latch” or disable the latching
effect.

Remember: an “AND” gate

will only have a high output
if both inputs are high
 Gated S-R latch: introduction
By connecting an extra para of NAND gates to the circuit, we have created a third input “E”, and
now we have a new circuit in which the normal states of “S” and “R” are “0”, and high pulses are
required to set or reset the latch.

To consider: then our “NAND-based-latch”

has been changed from an “active-low-latch”
into an “active-high-latch”.
These additional gates on a basic SR latch
are sometimes referred to as “steering gates”

To consider: we are going to use a chronogram to show

the changes in inputs or outputs on a chart showing
changes in voltage against time. Remember that
everything occurs very quickly in an digital circuits (time
intervals in this chart have a duration of micro-second).
Low voltage (0 volts) represents binary value “0”, and
high voltage (5 volts) represents binary value “1”
 Gated S-R latch: chronogram examples
We are going to use a chronogram to describe the behavior of the latch. Remember that we are
going to used a “gated S-R latch”, which is fully build out of “NAND” gates
NAND gate
truth table

To consider: for the following A B Output

exercises, it does not take any time 0 0 1
from voltage to change from low
0 1 1
to high or for high to low. In reality
this transitions takes a few 1 0 1
nanoseconds. But for these examples, 1 1 0
we are going to consider that changing
from high to low and vice-versa is
instantaneous, which produces
a classic square wave
 Gated S-R latch: chronogram example (II)
The starting state for the output “Q” as we can check is low, being “S” and “R” both low but “E” is
high, so the latch is enabled. Actually, in this diagram, the latch is always enabled, so it is going to
behave exactly like a simple “S-R latch” without steering gates. Remember that since it is a latch,
when “S” goes low again, the output “Q” remains the same. Analyze the chronogram and try to
reproduce it step by step:

NAND gate
truth table
A B Output
0 0 1
0 1 1
1 0 1
1 1 0
 Gated S-R latch: chronogram example 2
Now let’s examine an example where input “E” varies. The starting state here is “0” for “Q”, and
because “E” is low, the latch is disabled, so as we can check, if “S” goes “high”, it has no effect on
the output “Q” since input “E” is disabled. Remember that input “S” and “R” are only going to
affect the latch if “E” is enabled, but being “E” enabled does not imply that “S” and “R” change the
output “Q”:

NAND gate
truth table
A B Output
0 0 1
0 1 1
1 0 1
1 1 0
 Gated S-R and gated R-S latches: summary
An R-S latch (the one built from “NOR” gates), can be turned into a “gated R-S latch” by adding a par
of “AND” gates to it. An S-R latch (the one built from “NAND” gates) can be turned into a “gated S-R
latch” by adding a pair of “NAND” gates to it. This changes the “S-R latch” from an “active-low S-R
latch” to an “active-high S-R latch”
Gated S-R latch
Gated R-S latch Logic symbol

Remember: a gated S-R/R-S latch has an extra

input “E” which must be high before the latch
responds to any changes in “S” or “R”
 Gated D latch: introduction
Gated D latch are a “1 bit memory device”, where “D” stands for data. They are also referred as just
“D latch”. D-latches can be build from a gated S-R latch. With this type of construction, we avoid a
problem that S-R latches have. Remember that a S-R latch can be constructed from NAND gates,
being as we know, an “active-high” S-R latch, which means that normally S and R are normally set at
low voltage (representing “0”), and a “positive pulse” (“1”) is required in order to set or reset the
latch. The problem that we have with this type of circuit (“gated S-R”) is that it exists the possibility
that “S” and “R” are made high simultaneously, and as we known, this is a forbidden state. But in
reality both “Q” and “” would become high.
Gated S-R latch
Logic symbol problematic
Remember: a gated S-R latch
has a third input, named “E”,
which when high, enables
the latch

Remember: if both “S” and

“R” fell to “0” at the same
time, the “raise condition
event” will occur, making the
nest state unpredictable
 Gated D latch: solving “gated S-R latch”
problematic
Since this kind of unpredictability in an electronic circuit is unacceptable, we can solve it by making
“S” and “R” the opposite just adding a single NOT gate, so the forbidden state where “S” and “R”
are both equal to “1” can never occur. We then rename the input “D” for data, having then a 1
input gated S-R latch.
Gated D latch Gated D latch renamed for simplicity
 Gated D latch: how it works
While the “enable input” “E”, if “D” is also high, then so is “Q”. While “E” is high, if “D” changes to
low, then so does “Q”. You can notice that while “E” is high, “Q” is always the same as “D”.
Remember that since we are using a NOT gate it is impossible for the latch to finish in the forbidden
state like an S-R latch might. As you can see, if “E” falls to “0”, output “Q” will retain its previous
value.

1 2

3 4
Gated D latch: how it works (II) and rewiring
the circuit
As you can see, the latch now will not respond to changes in input “D”, since input “E” is not
enabled, so it is locked in its current state.

5 6

D latch rewired

Now we can rewire the for NAND gates,

building a D latch in a different way, and these
circuits do exactly the same, but since
we are using less components, this version
is then more efficient and cheaper to make
 Gated D latch: NOT gate and rewired version
comparison
As we can see, the new version (the one in the bottom) is taking advantage that the output of the
top NAND gate is the inverse of the input “D”, as long as the latch is enabled, so the output is feed
back into the lower NAND gate. As we can see this new version behaves in the same way as the old
one (the one using the NOT gate) does. Let’s check an example considering the following starting
state:
Starting state:

Newer one 1

Old version 2
 Gated D latch rewired: how it works (I)
Let’s continue checking how the states evolves depending on the changes that we apply. Now “E”
goes low and the output “Q” remains with the same value, “0”. “E” is still low, “D” becomes high,
but there is no change in the output “Q” since the latch is still disabled. Now “E” becomes high
again, being “D” already high, so output “Q” goes high

4
3

Remember: since it is
a “gated” latch, input “E”
must be enabled so as to 5
the input “D” can affect
the circuit
 Gated D latch: chronogram example
Let’s try to analyze the following example of a chronogram for a gated D latch. Remember that since
“” is the opposite of the output “Q”, is not going to be consider in the chronogram:

Let’s consider “Q” = 0 as the starting state

D latch “abstraction NAND gate
symbol” truth table
A B Output
0 0 1
0 1 0
1 0 0
Remember: both of the
two types of “gated D latches” 1 1 0
behave exactly in the same way.
The one using the NOT gate, and
the “rewired one”. So the chronogram Remember: input “E” should be enabled
is exactly the same for both (“high”, value = 1) for the input “D” to
affect the circuit
 Gated D latch: chronogram exercise
Provided the following “time-chart” (chronogram), find the corresponding square wave of the
output “Q”. Consider the starting state of “Q” as “0”:
Gated D latch: chronogram exercise solution

NAND gate
truth table
A B Output
Remember: the D latch can be implemented either 0 0 1
with the “NOT gate” circuit or with the “rewired one” 0 1 0
1 0 0
1 1 0
 Gated D latch: summary and applications
“Gated D latches” or just “D latches” can be built from a “gated S-R latch”, either including a NOT
gate or by rewiring the existing NAND gates. Its behavior can be described as that the output “Q”
follows the input “D” while the latch is enabled, that is, while input “E” is high. If the latch is
disabled, it retains its current state. It can be used to store 1 bit of data, so it is a 1 bit memory
device:
D latch “abstraction
D latch using a “NOT” gate D latch rewired symbol”

To consider: an application of the D latches is using them to convert parallel

data into serial data. A group of D latches can hang on to several bits of data
while a multiplexer accesses them one at a time an places them onto a serial
transmission line. D latches are normally found in input/output ports
 Flip-flops: introduction to synchronous
sequential logic
Flip-flops are synchronous electronic devices of two states, they are also known as bistable
multivibrators. “Synchronous” implies that the output only changes with the signal of the clock, normally
named as “clk”. This clock signal is also normally referred as “control input”. To sum up, the changes in
the output occur synchronously with the clock signal. Flip-flops (from now on will be referred as just
“FF”), changes with the raising edge (when clock signal goes from low to high, that is, from “0” to “1”), or
it can also change with the falling edge (when the clock signal goes from high to low, that is, from “1” to
“0”). So we then have the following logic symbols abstraction for the principal types of FF that are used
in digital electronics: S-R flip-flops, D-flip-flops and J-K flip-flops:
J-K flip-flop To consider: we can
S-R flip-flop D flip-flop
distinguish vs the
raising edge set mode
and the falling edge
“raising-edge
mode by the different
mode”
symbols that we have
for the clock input.
The falling edge mode
has a small ball in the
“falling-edge clock input
mode”
 Flip-flops: implementation of the raising edge
So know, how can we implement the “raising edge detector” for our flip-flops so they are only
triggered and thus changing the output of “Q” only at the moment with the clock signal changes
from low to high?. Since depending on the frequency of the clock, the “enabling input” (“E”), might
be high for maybe as much as 50 microsecond which is a lot for a data latch to be opened for
changes in “D”, and for some applications, especially for those whose output is fed back to the
input, we can avoid this problem by limiting the amount of time during each clock cycle that the
latch can change state. Increasing the frequency of the clock is not a practical solution given that a
computer contains a mixture of fast and slow components
To consider: with
Problem: input “E” the raising edge,
enabled for a lot the input “E” is
of time only enabled during
a few nanoseconds.
1 ns = 10-9 s
Solution: “raising
edge”. Making the
input “E” affecting To consider:
“Q” only during the 50 µs = 0,00005 segs
raising edge
 Flip-flops: implementation of the raising edge
(II)
So we want to build a latch (for example a “D latch”) that only responds in changes in input “D”
during the raising edge thus being the next changing in “D” ignored until the next raising edge. We
can implement this “raising edge detector” with just adding a “NOT” gate and an “AND” together.
To consider: similarly when the input
Normal behavior 1 Normal behavior 2 changes from high to low, there is
another brief period when both the
NOT gate and the input are “0” at the
same time, but this does not affect
the raising edge because this does not
affect the output of the AND gate

To consider: since the NOT gate

does not inverse its input instantly.
So when the input changes from low
to high, there is a brief moment when
the output of the AND gate is the same as
its input To consider: so we have implemented then a device that detects
the very brief instant at which an input raises from low to high, then
implementing the “raising edge”
 Flip-flops: implementation of the raising edge
(III), effect on the chronogram

1 2

3
To consider: as we can see
this effect of the NOT
gate “lagging” can be used
to implement the
raising edge
 Flip-flops: implementation of the raising edge (IV),
adding it to the circuit and chronogram example
We can finally add our “raise detector device” to our circuit . Let’s check an example to see how
it works:
D Flip flop
“abstraction
symbol”
triggered by
Final implementation raising edge
in a “D latch”
 Flip-flops: raising edge problematic and
falling edge detector implementation
One of the problem with using this particular “raising edge detector device” is that the pulse that it
produces may not be wide enough to open the latch an let data in. This actually depends on
several factors including the operating characteristics of the electronic components and the specific
voltage levels being applied. However, we can increase the delay of our edge detector and
therefore the pulse by adding several NOT gates.
D Flip flop
“abstraction NOR gate truth
To consider:
symbol” table
we need an odd
triggered by
number of not gate A B Output
falling edge
to invert the signal
0 0 1
0 1 0
Falling edge implementation
1 0 0
To consider: we can build a “falling edge
detector” using a NOR gate instead. 1 1 0
When both are momentarily low at the
negative edge of the clock cycle, we will
get a high output
 S-R flip flops: how it works
Now that we have learned how to implement the raising edge detector and the falling edge
detector, let’s see how it works in a S-R flip-flop. Remember than in flip-flops the input data “S” and
“R” are only transferred to the output only with the clock pulse. Let’s summarize the behavior of a
“triggered raising edge flip-flop” with the following table:
INPUT OUTPUT NOR gate truth
COMMENTS table
S R CLK Q
Remember: 0 0 X No change A B Output
“clk” stands 0 0 1
0 1 0 1 RESET
for “clock pulse”
1 0 1 0 SET 0 1 1

1 1 ? ? Invalid condition 1 0 1
1 1 0
To consider:
we can see flip flops also build De Morgan’s Laws
with “negative-OR” gates instead of with
NAND gates, since their = *
behavior and therefore truth table is the NAND Negative - OR
same since we can apply the DeMorgan’s = +
theorems
 S-R flip flops: how it works (II)
So the electronic scheme for an S-R flip flop could be the following one. Remember that the
“negative-OR” gates are equivalent to the NAND ones:
To consider: “R-E-D”
S stands for “Raising Edge
Q Device” and “F-E-D” stands
for “Falling Edge Device”
CLK R-E-D/
F-E-D
Remember: a flip-flop cannot
𝑄 change state except during
R the raising edge or the falling
edge. This implies also that inputs
“S” and “R” can change while the
Steering gates Latch
clock input is high and there will
be no change in the output “Q”,
except during a small period of time
S-R Flip-Flop during the clock transitions from
low to high or high to low
 S-R flip flops: chronogram example
Provided the following “time-chart” (chronogram), find the corresponding square wave of the
output “Q”. Consider the starting state of “Q” as “0”:

Raising – edge triggered

S – R flip flop
S-R flip flops: chronogram example solution
To consider: Since the “abstraction symbol”
indicates that it is a raising-edge
triggered, changes in the output “Q” will
occur only in this event

INPUT OUTPUT
COMMENTS
S R CLK Q
0 0 X No change
0 1 0 1 RESET
1 0 1 0 SET
Invalid
1 1 ? ?
condition
 S-R flip flops: chronogram example 2
Provided the following “time-chart” (chronogram), find the corresponding square wave of the output “Q”.
Consider the starting state of “Q” as “0”:

Falling – edge triggered

S – R flip flop
S-R flip flops: chronogram example 2
solution
To consider: Since the “abstraction symbol”
indicates that it is a falling-edge
triggered, changes in the output “Q” will
occur only in this event

INPUT OUTPUT
COMMENTS
S R CLK Q
0 0 X No change
0 1 0 1 RESET
1 0 1 0 SET
Invalid
1 1 ? ?
condition
 D flip flops: how it works
D flip flops are useful when we need to store only a 1 bit memory (1 or 0). The implementation of
this flip flop is done by adding a NOT gate to a S-R flip flop. The behavior of this flip flop can be
summarized with the following table:
Implementing a D flip flop
To consider: we can add our “raising edge” using an S-R flip flop
detector or our “falling edge” detector
to each of the 3 flip flops that
we are going to learn: S-R flip flop, D flip flop
and J-K flip flop

Summarized behavior for

D flip flop raising edge trigger

INPUT OUTPUT
COMMENTS
D CLK Q
1 1 0 SET (stores a “1”)
0 0 1 RESET (stores a “0”)
 D flip flops: chronogram example
Provided the following “time-chart” (chronogram), find the corresponding square wave of the
output “Q”. Consider the starting state of “Q” as “0”:

Raising – edge triggered

D flip flop
 D flip flops: chronogram example solution
To consider: Since the “abstraction symbol”
indicates that it is a raising-edge
triggered, changes in the output “Q” will Solution: output “Q” follows the value
occur only in this event of input “D”

INPUT OUTPUT
COMMENTS
D CLK Q
1 1 0 SET (stores a “1”)
0 0 1 RESET (stores a “0”)
 J-K flip flops: how it works
It is one of the more used flip flops. Its behavior is really similar to the S-R flip flop for the SET and
RESET operation as well as for the “no change” case. The main difference between this type of flip
flop and S-R ones is that the J-K flip flop does not have “invalid conditions”. As we can see, its
circuit implementation is exactly the same as the S-R ff but now the outputs are feed back to the
inputs, so we are going to use two “3 inputs” NAND gates: NAND gate
truth table
Remember: “Negative-OR” gates behaves
exactly in the same way as “NAND” ones A B C Output

0 0 0 1
R-E-D/ 0 0 1 1
F-E-D 0 1 0 1
NAND Negative - OR
0 1 1 1
1 0 0 1
Remember: “R-E-D”
Steering gates Latch 1 0 1 1
stands for “Raising Edge
Device” and “F-E-D” stands 1 1 0 1
for “Falling Edge Device” J-K Flip-Flop 1 1 1 0
 J-K flip flops: how it works (II)
Let’s check the following table that summarizes the behavior of the J-K flip flop. Now, the non-valid
condition of a S-R ff just changes to the opposite state of the ff for the outputs. This is known as
“toggle state”. Let’s check the following truth table that summarizes the behavior of this ff:

INPUT OUTPUT
COMMENTS
Remember: S R CLK Q
the main difference 0 0 No change
between the S-R ff
and the J-K is that 0 1 0 1 RESET
in the J-K there a 1 0 1 0 SET
are no invalid states 1 1 Toggle
 J-K flip flops: chronogram example
Provided the following “time-chart” (chronogram), find the corresponding square wave of the
output “Q”. Consider the starting state of “Q” as “0”. Also indicate all of the states in the changes:

Falling – edge triggered

J-K flip flop
 J-K flip flops: chronogram example solution

INPUT OUTPUT
COMMENTS
S R CLK Q
0 0 No change
0 1 0 1 RESET
1 0 1 0 SET
1 1 Toggle No
Toggle change Reset Set Set
Summary: synchronous vs asynchronous
sequential logic
Asynchronous Synchronous
Synchronous sequential circuits are Asynchronous sequential circuits
digital sequential circuits in which are digital sequential circuits in
Definition the feedback to the input for next which the feedback to the input for
output generation is governed by next output generation is not
clock signals. governed by clock signals.
The memory unit which is being get Unclocked flip flop or time delay is
Memory unit used for governance is clocked flip used as memory element in case of
flop. Asynchronous sequential circuits.
The states of Synchronous there are chances for the
sequential circuits are always Asynchronous circuits to enter into
predictable and thus reliable. a wrong state because of the time
State
difference between the arrivals of
inputs. This is called as race
condition.
S-R and R-S latches, Gated S-R S-R flip flops, D flipflops, J-K flip
Examples
latches, D latches flops
 Bibliography:
• Floyd, T. L. (2000). Fundamentos de Sistemas Digitales, 9ª. Edición,
Capítulo, 2, 2-10.