Unit 3-Computer Arithmetic

• The arithmetic and logic Unit.

• Integer representation.
• Integer arithmetic.
• Floating point representation.
• Floating point arithmetic.
• Introduction of arithmetic co-processor.
 The arithmetic and logic Unit
• ALU perform actual arithmetic and logical operation on data.
• All of the other elements of the computer system—control unit, registers, memory,
I/O—are there mainly to bring data into the ALU for it to process and then to take
the results back out.
• All electronic components in the computer, are based on the use of simple digital
logic devices that can store binary digits and perform simple Boolean logic
operations.
• Operands for arithmetic and logic operations are presented to the ALU input.
• Results of an operation are stored in temporary registers.
• The ALU also set/Reset flags ( update Flag Register) as the result of an
Arithmetic/Logical operation.
 The arithmetic and logic Unit
• ALU Connections
 The arithmetic and logic Unit
• ALU Block Diagram:
 The arithmetic and logic Unit

• How Digital Circuit is implemented inside ALU?

• Which Components are used ?
• What is the method to design those circuits?
• Lets Take an example of simple adder …which can add two bit
of data ……A and B
• 1. Truth table are developed
• 2. Boolean Equations are formed .
• 3. Boolean equations are implemented using logic gates.
 The arithmetic and logic Unit

• 1. Truth table are developed as per requirement.

• 2. Boolean Equations are formed .
• 3. Boolean equations are implemented using logic gates.
 The arithmetic and logic Unit

• 1. Truth table are developed

• 2. Boolean Equations are formed .
• 3. Boolean equations are implemented using logic gates.

Sum = a EX OR b
Carry = a AND b
 The arithmetic and logic Unit
• 1. Truth table are developed
• 2. Boolean Equations are formed .
• 3. Boolean equations are implemented using logic gates.
 The arithmetic and logic Unit

• Similarly all arithmetic and logical circuits are implemented

inside ALU..
• Such as .. Adder ( 8 Bit…16 bit ..as per the required size)
Subtractor
multiplier
divider
logical circuits and many more ……..
Integer representation:
• For purposes of computer storage and processing, we do not have the benefit of
special symbols for the minus sign and radix point.

• Only binary digits (0 and 1) may be used to represent numbers.

• If we are limited to nonnegative integers, the representation is straightforward.

• An 8-bit word can represent the numbers from 0 to 255, such as,

00000000 = 0
00000001 = 1
00101001 = 41
10000000 = 128
 Integer representation:
• Then How to represent NEGATIVE numbers in computer ?

• There are several alternative conventions used to represent negative as

well as positive integers,.

• All of which involve treating the most significant (leftmost) bit in the
word as a sign bit.

• If the sign bit is 0, the number is positive; if the sign bit is 1, the number
is negative.
SIGNED-MAGNITUDE representation
• The simplest form of representation that employs a sign bit is the
sign-magnitude representation.
• In an n-bit word, the leftmost bit (MSB) bits hold the Sign and
remaining bits holds the magnitude of the integer.
 Drawbacks of sign-magnitude representation:
• Addition and subtraction require a consideration of both the signs of
the numbers and their relative magnitudes to carry out the required
operation.
• There are two representations of 0

• Because of these drawbacks, sign-magnitude representation is

rarely used in implementing the integer portion of the ALU. Instead,
the most common scheme is twos complement representation.
 Two’s Complement Representation
• Like sign magnitude, twos complement representation uses the most
significant bit as a sign bit, making it easy to test whether an integer is
positive or negative.
• It differs from the use of the sign-magnitude representation in the way
that the other bits are interpreted.
 Two’s Complement Representation
• The number zero is identified as positive and therefore has a 0 sign bit and a magnitude of
all 0s.
• Range of positive integers that may be represented is from 0 (all of the magnitude bits are
0) through 2n-1 - 1 (all of the magnitude bits are 1).
• Example,
• If n=4, then positive number will be from 0000 to 0111(0,1,2,3,4,5,6,7).
• If n=3, then positive number will be from 000 to 011(0,1,2,3).

• Now, for a negative number A(A < 0), the sign bit, a n-1 is one.
• The remaining n - 1 bits can take on any one of 2 n-1 values. Therefore, the range of
negative integers that can be represented is from -1 to - 2n-1
• Example,
• If n=4, then negative number will be from 1000 to 1111(-8,-7,-6,-5,-4,-3,-2,-1).
• If n=3, then negative number will be from 100 to 111(-4,-3,-2,-1).
Two’s Complement Representation

2’s complement method facilitates the most important arithmetic operations,

addition and subtraction. For this reason, it is almost universally used as the
processor representation for integers.
Two’s Complement Representation: Value Box
 Two’s Complement Representation: Range
Extension
• Range Extension It is sometimes desirable to take an n-bit integer and
store it in m bits, where m > n.
• This expansion of bit length is referred to as range extension, because
the range of numbers that can be expressed is extended by increasing
the bit length.
 Two’s Complement Representation: Range
Extension
• The rule for twos complement integers is to move the sign bit to the
new leftmost position and fill in with copies of the sign bit.
• For positive numbers, fill in with zeros, and for negative numbers, fill in
with ones. This is called sign extension.

• The representations discussed above is referred to as fixed point.

• This is because the radix point (binary point) is fixed and assumed to be
to the right of the rightmost digit.
 Integer Arithmetic: Addition and Subtraction
• Overflow rule: If two numbers are added, and they are both positive or
both negative, then overflow occurs if and only if the result has the
opposite sign.
• In some instances, there is a carry bit beyond the end of the word
(indicated by shading), which is ignored.
• Addition:
 Integer Arithmetic: Addition and Subtraction
• Subtraction rule: To subtract one number (subtrahend) from another
(minuend), take the twos complement (negation) of the subtrahend and
add it to the minuend.
• Thus, subtraction is achieved using addition.
Integer Arithmetic: Hardware for Addition and
Subtraction
Integer Arithmetic: Multiplication- method
• unsigned integers:
• 1. Partial product.
• 2 Shift Partial product.
• 3 Add partial product to get final result.
• The multiplication of two n-bit binary integers results in a product of up to
2n bits in length (e.g., 11 * 11 = 1001).
Integer Arithmetic: Multiplication-Implementation
(H/W)
Integer Arithmetic: Multiplication-Booths Algorithm
Integer Arithmetic: Multiplication-Booths Algorithm
• 1-bit register placed logically to the right of the least significant bit (Q0) of the
Q register and designated Q-1.
• The results of the multiplication will appear in the A and Q registers
• A and Q-1 are initialized to 0
• control logic scans the bits of the multiplier one at a time. Now, as each bit is
examined, the bit to its right is also examined.
• If the two bits are the same (1–1 or 0–0), then all of the bits of the A, Q, and Q-
1 registers are shifted to the right 1 bit.
• If the two bits differ, then the multiplicand is added (0-1)to or subtracted(1-0)
from the A register.
• In any shift case, the right shift is such that the leftmost bit of A, namely An-1,
not only is shifted into An-2, but also remains in An-1. This is required to
preserve the sign of the number in A and Q. It is known as an arithmetic shift,
because it preserves the sign bit.
Integer Arithmetic: Division
Integer Arithmetic: Division
• The divisor is placed in the M register, the dividend in the Q register.
• At each step, the A and Q registers together are shifted to the left 1 bit.
• M is subtracted from A to determine whether A divides the partial remainder.
 An IEEE floating point representation
consists of

• A Sign Bit
• An Exponent
Floating • Mantissa (“Significand”), which is assumed to be
1.xxxxx (thus, one bit of the mantissa is implied as
Point 1)
• This is called a normalized representation

So a mantissa = 0 really is interpreted to

be 1.0, and a mantissa of all 1111 is
interpreted to be 1.1111
 Defined by IEEE Std 754-1985

Developed in response to divergence of

representations
• Portability issues for scientific code
Floating Point
Standard Now almost universally adopted

Two representations
• Single precision (32-bit)
• Double precision (64-bit)
IEEE Floating-Point Format
single: 8 bits single: 23 bits
double: 11 bits double: 52 bits
S Exponent Fraction

x  ( 1) S  (1 Fraction)  2(Exponent Bias)

• S: sign bit (0  non-negative, 1  negative)

• Normalize significand: 1.0 ≤ |significand| < 2.0
– Always has a leading pre-binary-point 1 bit, so no need to represent it
explicitly (hidden bit)
– Significand is Fraction with the “1.” restored
• Exponent: excess representation: actual exponent + Bias
– Ensures exponent is unsigned
– Single: Bias = 127; Double: Bias = 1203
 Exponents 00000000 and 11111111 reserved

Smallest value
Single- • Exponent: 00000001
Actual/True exponent = 1 – 127 = –126
Precision • Fraction: 000…00 means significand = 1.000….0000
• ±1.0 × 2–126
Range
Largest value
• exponent: 11111110
Actual/True exponent = 254 – 127 = +127
• Fraction: 111…11 means significand ≈ 2.0
• ±2.0 × 2+127
 • Exponents 0000…00 and 1111…11 reserved
• Smallest value
– Exponent: 00000000001
 actual/True exponent = 1 – 1023 = –1022
Double-Precision – Fraction: 000…00  significand = 1.0
– ±1.0 × 2–1022
Range • Largest value
– Exponent: 11111111110
 actual/True exponent = 2046 – 1023 = +1023
– Fraction: 111…11  significand ≈ 2.0
– ±2.0 × 2+1023
Representation of Floating Point
Numbers
• IEEE 754 single precision

31 30 23 22 0

Sign Biased exponent Normalized Mantissa (implicit 24th bit = 1)

Exponent Mantissa Object Represented

0 0 0
0 non-zero denormalized
(-1)s  F  2E-127 1-254 anything FP number
255 0 pm infinity
255 non-zero NaN
• Represent –0.75
– –0.75 = (–1)1 × 1.12 × 2–1
– S=1
– Fraction = 1000…002
– Exponent = –1 + Bias
• Single: –1 + 127 = 126 = 01111110 2
• Single(32 Bit): 1011111101000…00

Floating-Point Example
 Consider a 4-digit decimal example

• 9.999 × 101 + 1.610 × 10–1

1. Align decimal points

• Shift number with smaller exponent

• 9.999 × 101 + 0.016 × 101

Floating- 2. Add significands

Point
• 9.999 × 101 + 0.016 × 101 = 10.015 × 101
Addition
(Decimal 3. Normalize result & check for over/underflow
Add/Sub • 1.0015 × 102
examples)
4. Round and renormalize if necessary

• 1.002 × 102
 Now consider a 4-digit binary example

• 1.0002 × 2–1 + –1.1102 × 2–2 (0.5 + –0.4375)

1. Align binary points

• Shift number with smaller exponent

• 1.0002 × 2–1 + –0.1112 × 2–1
Floating-
2. Add significands
Point
• 1.0002 × 2–1 + –0.1112 × 2–1 = 0.0012 × 2–1
Addition
(Binary 3. Normalize result & check for over/underflow

add/Sub • 1.0002 × 2–4, with no over/underflow

example) 4. Round and renormalize if necessary

• 1.0002 × 2–4 (no change) = 0.0625

•
Floating point addition/Subtraction Start

1. Compare the exponents of the two numbers.

Shift the smaller number to the right until its
exponent would match the larger exponent

2. Add the significands

•
3. Normalize the sum, either shifting right and
incrementing the exponent or shifting left
and decrementing the exponent

Overflow or Yes
underflow?

No Exception

4. Round the significand to the appropriate

number of bits

No
Still normalized?

Yes

Done
Floating point Multiplication

•
Floating point Division

•
8087 Co Processor( FPU)

•
8087 Co Processor( FPU) features:

•
8087 Co Processor( FPU) : Its own instruction set