Instructions format

Three address instructions

Three Address Instructions
X=(A+B)*(C+D)
Add R1,A,B R1<-M[A]+M[B]
Three address instructions
Three Address Instructions
X=(A+B)*(C+D)
Add R1,A,B R1<-M[A]+M[B]
Add R2,C,D R2<-M[C]+M[D]
Three address instructions
Three Address Instructions
X=(A+B)*(C+D)
Add R1,A,B R1<-M[A]+M[B]
Add R2,C,D R2<-M[C]+M[D]
MUL X,R1,R2 M[X] <- R1 * R2
Two address instructions
Two address instructions
TWO Address Instructions
X=(A+B)*(C+D)
MOV R1,A R1<-M[A]
Two address instructions
TWO Address Instructions
X=(A+B)*(C+D)
MOV R1,A R1<-M[A]
Add R1,B R1<-R1+M[B]
Two address instructions
TWO Address Instructions
X=(A+B)*(C+D)
MOV R1,A R1<-M[A]
Add R1,B R1<-R1+M[B]
MOV R2,C R2<-M[C]
Two address instructions
TWO Address Instructions
X=(A+B)*(C+D)
MOV R1,A R1<-M[A]
Add R1,B R1<-R1+M[B]
MOV R2,C R2<-R2+M[C]
ADD R2,D R2<-R2+M[D]
Two address instructions
TWO Address Instructions
X=(A+B)*(C+D)
MOV R1,A R1<-M[A]
Add R1,B R1<-R1+M[B]
MOV R2,C R2<-R2+M[C]
ADD R2,D R2<-R2+M[D]
MUL R1*R2 R1<-R1*R2
Two address instructions
TWO Address Instructions
X=(A+B)*(C+D)
MOV R1,A R1<-M[A]
Add R1,B R1<-R1+M[B]
MOV R2,C R2<-M[C]
ADD R2,D R2<-R2+M[D]
MUL R1*R2 R1<-R1*R2
MOV X,R1 M[X]<-R1
ONE ADDRESS
INSTRUCTION
Two address instructions
ONE Address Instructions
X=(A+B)*(C+D)
LOAD A AC<-M[A]
Two address instructions
ONE Address Instructions
X=(A+B)*(C+D)
LOAD A AC<-M[A]
ADD B AC<-AC+M[B]
Two address instructions
ONE Address Instructions
X=(A+B)*(C+D)
LOAD A AC<-M[A]
ADD B AC<-AC+M[B]
STORE T M[T]<-AC
Two address instructions
ONE Address Instructions
X=(A+B)*(C+D)
LOAD A AC<-M[A]
ADD B AC<-AC+M[B]
STORE T M[T]<-AC
LOAD C AC<-M[C]
Two address instructions
ONE Address Instructions
X=(A+B)*(C+D)
LOAD A AC<-M[A]
ADD B AC<-AC+M[B]
STORE T M[T]<-AC
LOAD C AC<-M[C]
ADD D AC<-AC+M[D]

STORE X M[X]<-AC
Two address instructions
ONE Address Instructions
X=(A+B)*(C+D)
LOAD A AC<-M[A]
ADD B AC<-AC+M[B]
STORE T M[T]<-AC
LOAD C AC<-M[C]
ADD D AC<-AC+M[D]
MUL T AC<-AC*M[T]
STORE X M[X]<-AC
 Zero Address Instruction
• A stacked organization computer does not use an address field for the
instructions ADD and MUL.
• Firstly present in postfix notation.
 Zero Address Instruction
X=(A+B) *
X=(A+B)*(C+D)
(C+D)
PUSH A TOS<-A
 Zero Address Instruction
X=(A+B) *
X=(A+B)*(C+D)
(C+D)
PUSH A TOS<-A
PUSH B TOS<-B
 Zero Address Instruction
X=(A+B) *
X=(A+B)*(C+D)
(C+D)
PUSH A TOS<-A
PUSH B TOS<-B
ADD TOS<-(A+B)
 Zero Address Instruction
X=(A+B) *
X=(A+B)*(C+D)
(C+D)
PUSH A TOS<-A
PUSH B TOS<-B
ADD TOS<-(A+B)
PUSH C TOS<-C
 Zero Address Instruction
X=(A+B) *
X=(A+B)*(C+D)
(C+D)
PUSH A TOS<-A
PUSH B TOS<-B
ADD TOS<-(A+B)
PUSH C TOS<-C
PUSH D TOS<-D
 Zero Address Instruction
X=(A+B) *
X=(A+B)*(C+D)
(C+D)
PUSH A TOS<-A
PUSH B TOS<-B
ADD TOS<-(A+B)
PUSH C TOS<-C
PUSH D TOS<-D
ADD TOS<-C+D
 Zero Address Instruction
X=(A+B) *
X=(A+B)*(C+D)
(C+D)
PUSH A TOS<-A
PUSH B TOS<-B
ADD TOS<-(A+B)
PUSH C TOS<-C
PUSH D TOS<-D
ADD TOS<-C+D
MUL TOS<-(C+D)*(A+B)
 Zero Address Instruction
X=(A+B) *
X=(A+B)*(C+D)
(C+D)
PUSH A TOS<-A
PUSH B TOS<-B
ADD TOS<-(A+B)
PUSH C TOS<-C
PUSH D TOS<-D
ADD TOS<-C+D
MUL TOS<-(C+D)*(A+B)
POP X M[X]<-TOS
 RISC (Reduced instruction
set computer) Instructions
• Restricted to the use of load and store instructions when communicating
between memory and CPU.
• All other instructions are executed within the registers of the CPU without
referring to memory.
• A program consist of LOAD and STORE instructions that have one memory
and one register address , and computation-type instructions that have three
specifying processor registers.
 RISC (Reduced instruction
set computer) Instructions
Load instructions transfers the operands from memory to CPU registers.
Add and mul operations are executed with data in the registers without
accessing memory.
The result of the computation is then stored in meory with a store instruction.
 RISC Instructions
X=(A+B) *
X=(A+B)*(C+D)
(C+D)
LOAD R1,A R1<-M[A]
 RISC Instructions
X=(A+B) *
X=(A+B)*(C+D)
(C+D)
LOAD R1,A R1<-M[A]
LOAD R2,B R2<-M[B]
 RISC Instructions
X=(A+B) *
X=(A+B)*(C+D)
(C+D)
LOAD R1,A R1<-M[A]
LOAD R2,B R2<-M[B]
LOAD R3,C R3<-M[C]
 RISC Instructions
X=(A+B) *
X=(A+B)*(C+D)
(C+D)
LOAD R1,A R1<-M[A]
LOAD R2,B R2<-M[B]
LOAD R3,C R3<-M[C]
LOAD R4,D R4<-M[D]
 RISC Instructions
X=(A+B) *
X=(A+B)*(C+D)
(C+D)
LOAD R1,A R1<-M[A]
LOAD R2,B R2<-M[B]
LOAD R3,C R3<-M[C]
LOAD R4,D R4<-M[D]
ADD R1,R1,R2 R1<-R1+R2
 RISC Instructions
X=(A+B) *
X=(A+B)*(C+D)
(C+D)
LOAD R1,A R1<-M[A]
LOAD R2,B R2<-M[B]
LOAD R3,C R3<-M[C]
LOAD R4,D R4<-M[D]
ADD R1,R1,R2 R1<-R1+R2
ADD R3,R3,R4 R3<-R3+R4
 RISC Instructions
X=(A+B) *
X=(A+B)*(C+D)
(C+D)
LOAD R1,A R1<-M[A]
LOAD R2,B R2<-M[B]
LOAD R3,C R3<-M[C]
LOAD R4,D R4<-M[D]
ADD R1,R1,R2 R1<-R1+R2
ADD R3,R3,R4 R3<-R3+R4
MUL R1,R3 R1<-R1*R3
 RISC Instructions
X=(A+B) *
X=(A+B)*(C+D)
(C+D)
LOAD R1,A R1<-M[A]
LOAD R2,B R2<-M[B]
LOAD R3,C R3<-M[C]
LOAD R4,D R4<-M[D]
ADD R1,R1,R2 R1<-R1+R2
ADD R3,R3,R4 R3<-R3+R4
MUL R1,R1,R3 R1<-R1*R3
STORE X,R1 M[X]<-R1