Chapter five

Interfacing Memory and I/O

Memory Interface
 Interfacing
• Interfacing is the process of connecting / communicating a µ-p to
the rest of the circuit or the external devices like I/O ports,
(keyboard, display system) and some additional dedicated
peripheral devices like DMA controller, PIC (programmable
interrupt controller) etc...
• Since a processor without memory is meaningless, before
attempting to interface memory to the µ-p, it is essential to explain
the functions of the 4 common types of memory devices.
• ROM
• Flash memory (EEPROM)
• Static Random Access Memory (SRAM)
• Dynamic Random Access Memory (DRAM).
ROM (Read Only Memory)

• ROM permanently stores programs and data that are

resident to the system and the data stored will not
change even when power supply is disconnected.
(Non-Volatile).
• ROM is available in many different forms.
– PROM (Programmable ROM)
– EPROM (Erasable Programmable ROM).
– EEPROM(Electrically Erasable ROM)
Flash Memory
• Another type of Read-Mostly Memory (RMM) is called the
flash memory.
– It is often called an EEPROM (Electrically Erasable ROM),
EAROM (Electrically Alterable ROM) or a NOVRAM (Non-
volatile RAM).
• Flash memories are so called because of their rapid erase
and write times.
• These memory devices are electrically erasable.
• The flash memory device is used to store setup information
for systems such as video card in the computer.
 Static RAM (SRAM)
• SRAM devices retain data for as long as DC
power is applied. Because no special action
(except power) is required to retain stored data,
these devices are called static memory.
• They are also a volatile memory because they
will not retain data without power.
• SRAM, stores temporary data and is used when
the size of the read/write memory is relatively
small.
 Dynamic RAM (DRAM)

• DRAM is essentially the same as SRAM, except that it

retains data for only 2 or 4 ms on an integrated capacitor.
After 2 or 4 ms, the contents of the DRAM must be refreshed
(re-written) because the capacitors, which store a logic 1/0,
lose their charges.
• Refreshing also occurs during a write, a read etc….
• DRAM memory requires many address pins that the
manufacturer have decided to multiplex the address inputs.
 MEMORY PIN CONNECTIONS
Pin connections common to all memory devices are the address inputs, data outputs
(or input /outputs), some type of selection input and at least one control input used
to select a read /write operation.
Address Connections
• All memory devices will have address inputs that select a memory
location within the memory devices.
• Address inputs are almost always labeled from A0 to AN, where ‘N’ can
be any value(one less than the total no of address pins).
– For eg: a memory device with 10 address pin has its address pins
labeled from A0 to A9.
• The number of address pins found on a memory device is determined
by the number of memory locations found within it.
• A 1K memory device has 10 address pins (A0 to A9) therefore, 10
address inputs are required to select any of its 1024 memory location.
• A 2K (2048) memory device has 11 address connections (A 0 to A10)
• A 4K memory device has 12 connections and 8K memory device has
13 and so ……on.
• A device that contains 1MB locations requires 20 bit address (A 0-A19).
 Data Connection
• All memory devices have a set of data outputs or input/outputs.
• Nowadays many memory devices have bi-directional common
I/O pins.
• The data connections are the points at which data are entered for
storage or extracted for reading.
• Data pins on the memory devices are labeled D0 through D7 for
an 8-bit wide memory device.
• If a memory device has 8 I/O connections which means that the
memory device stores 8-bits of data in each of its memory
locations.
• Memory devices are often classified according to total bit
capacity. For ex: a 1K x 8 bit memory device is sometimes listed
as 8K memory device or a 32K x 8 memory is listed as a 256K
device.
 Selection Connections
• Each memory device has an input-sometimes more than
one- that selects or enables the memory device.
• This type of input is most often called a Chip Select (CS),
Chip Enable (CE) or simply Select (S) input.
• RAM memory generally has at least one CS or S input and
ROM has at least one CE.
• If CE, CS, or S input is active (a logic 0), the memory
device performs a read/write operation.
• If is inactive (a logic 1), the memory device cannot
performs a read/write operation or these pins are disabled.
• If more than one CS connection is present, all must be
activated to read or write data.
Control Connections
• All memory devices have some form of control input/inputs.
• A ROM usually has only one control input, while a RAM often has
one or two control inputs.
• The control input most often found on a ROM is the Output Enable
(OE) or Gate (G) connection, which allows data to flow out the ROM.
• If OE and CS both are active, the output is enabled.
• A RAM memory device has either one or two control inputs. If there
is only one control input, it is often called R/ W.
• This pin selects a read operation or a write operation only if the device
is selected by the CS (Selection Input).
• If the RAM has two control inputs, they are usually labeled WE (or
W) and OE (or G).
• WE (Write Enable) must be active to perform a memory write and
OE must be active to perform a memory read operation.
• Both WE and OE must never be active at the same time. If so, data are
neither written nor read.
 Address decoding
• In order to attach a memory device to the
microprocessor, it is necessary to decode the
address sent from the processor.
• When the 8088 (20-bit address bus and 8-bit external data bus)
microprocessor is connected with the 2716 EPROM
device (which has only 11 address pins), a difference in
the number of address connections is clear- The 2716
EPROM has 11 address connections and the µ-p has 20.
• This means that the processor sends out a 20-bit
memory address whenever it reads/writes data.
• Since the EPROM has only 11 address pins, there is a
mismatch that must be corrected.
• The decoder corrects this mismatch by decoding the
address pins that do not connect to the memory
component.
 Simple NAND decoder
• When a 2K x 8 EPROM is used, address connections
A10-A0 of the 8088 are connected to the address inputs
A10-A0 of the EPROM. The remaining 9 address pins
(A19-A11) are connected to the inputs of a NAND
decoder.
• The output of the NAND decoder is connected to the CE
input pin that selects (enables) the EPROM.
• The decoder selects the EPROM addressed by the
processor.
• The OE pin is activated by 8088’s RD signal.
Interfacing 8088 with 2716-EPROM using a NAND decoder
• NAND gates are rarely used to decode memory because each
memory device requires its own NAND decoders. Also, because of
the excessive cost of the NAND gate decoder and inverters (that
are often required), an alternate option should be required.
• For this purpose, 3-to-8 Line decoders (74LS138 decoder ) are
commonly used.
• The three enable inputs (G2A, G2B and G1) must be
active, to enable the 74LS138 decoder.
• Once it is enabled, the three address inputs (A, B, C)
selects which output pin goes LOW.
• Imagine there are eight 2764 EPROM devices. These
devices can be connected to a single 3-8 line decoder
• The diagram follows this slide, shows a circuit that
uses eight 2764EPROMs for an 8088 µ-p based
system.
• This is a very powerful device because it selects eight
different memory devices at the same time.
The addresses selected in this circuit are F0000H - FFFFFH
8086 (16 BIT) MEMORY INTERFACE

• 8086 has 16 bit data bus (D15-D0) and 20 bit address bus(A19-A0)
• The 16 bit data bus must be divided into two separate sections
(banks) that are 8 bits wide so that µ-p can write to either one half
(8-bit) or both halves(16 bit).
• One bank (low bank) holds all the even-numbered memory
locations, and the other bank(high bank) holds all the odd–
numbered memory locations.
• 8086 use the BHE (Bus High Enable) signal – for high bank and
the A0 address bit or BLE (Bus Low Enable) – for low bank to
select one or both banks of memory for the data transfer.
• The below table depicts the logic levels on BHE
and BLE (or A0) and the bank or banks selected.

BHE BLE Function

0 0 Both banks enabled for a 16-bit transfer.

0 1 High bank enabled for an 8-bit transfer.
1 0 Low bank enabled for an 8 bit transfer.
1 1 No banks enabled.
 The 8086 address & data bus concepts
• The 8086 memory space is physically implemented on
a 16-bit data bus by dividing the address space into
two banks.
• These banks can be selected by BHE and BLE (or A0)
as follows:-
• One bank is connected to D7-D0 and contain all even
addressed bytes(A0=0)
• The other bank is connected to D15-D8 and contains all
odd-addressed bytes (A0=1)
General block diagram of an 8086 memory array
As an example, consider the instruction MOV DH , [BX]

• Suppose the 20-bit physical address computed by

BX and DS is even.
• Then the 8086 outputs LOW on A0 and HIGH on
BHE. This will select the even-addressed bank.
• The content of the selected memory is placed on
the D7-D0 lines by the memory chip.
• The 8086 reads this data via D7-D0 and
automatically places it in DH.
Even Byte Transfer
Odd Byte Transfer
 Now consider the instruction MOV [BX] , CX
and assume [BX] = 0004H, DS = 2000H.

• The 20-bit physical address for the word is

20004H.
• 8086 outputs LOW on both BHE and A0, enabling
both the banks simultaneously.
• Then 8086 outputs CL to D7-D0 lines and CH to
D15-D8 lines with a LOW in WR pin.
• The enabled memory banks obtain the 16-bit data
and write to location 20004H and 20005H.
Even word transfer
Accessing an odd-addressed word transfer by the 8086.
For eg:- suppose 20-bit physical address computed by the 8086 is 20005H .
• The 8086 accomplishes this transfer in 2 bus cycles.
• In the first cycle, 8086 outputs HIGH on A0, LOW on
BHE and thus enables the odd-addressed bank.
• 8086 also outputs LOW on RD pin. In this cycle, the
odd-memory bank places the content of [20005H] on the
D15-D8 lines.
• In the second cycle, the 8086 outputs LOW on A0, HIGH
on BHE and thus enables the even-addressed bank.
• 8086 also outputs LOW on RD pin.
• The selected even-addressed memory bank places the
content of [20006H] on D7-D0 lines.
Odd word transfer
• Two bus cycles are needed for a word transfer from an
odd addressed location.
• During the first cycle, the byte of the word located in
the high bank is accessed over D15 through D8 line.
• Even though the data transfer uses data lines
D8 through D15 , to the processor it is the low byte of
the addressed data word.
• In the second cycle, the byte of the word located in the
low bank is accessed over D7 through D0 line.
I/O Interface
 Interfacing
• A microprocessor is great at solving problems, butt if it
cant communicate with outside world, it is of little worth.
• Using I/O ports, the µ-p communicates with the external
destinations.
• For a µ-p, the input activity is similar to READ operation
and output activity is similar to WRITE operation.
• Hence, IORD operation is related with reading a data from
an input device and IOWR operation means writing a data
to an output device.
 Steps in interfacing a general I/O device with a µ-p

• Decode the address of the device and use it as

chip select of the device.
• Connect the data bus of the µ-p system with the
data bus of the I/O device.
• Use a suitable control signal. ie, IORD or IOWR
to carry out the operations. That means, connect
IORD to RD input of the device if it is an input
device, otherwise connect IOWR to WR input of
the device.
• There are two methods of interfacing general I/O devices:-

-Port mapped I/O (I/O mapped I/O or standard I/O or isolated I/O)
-Memory mapped I/O

• 8086 can be interfaced to 8/16 bit I/O devices using

either Port mapped I/O or Memory-mapped I/O
• The port mapped I/O uses the instructions IN and OUT and
can transfer 8/16 bit data with a peripheral device.
• In the memory mapped I/O scheme, any instruction that
references memory can accomplish the transfer.
 Port mapped I/O

• The most common I/O transfer technique used in

Intel µ-p based systems is Port mapped I/O.
• The address for the I/O device; called the ports,
are accessed through some instruction only.
• In I/O mapped interfacing, all the available
address lines of a µ-p may not be used for
interfacing the devices.
• Port mapped I/O method will use commonly IN and
OUT instructions.
• The opcode IN refers to moving data from the I/O
device into the microprocessor and the opcode OUT
refers to moving data out of the microprocessor to the
I/O device.

The I/O port addressing can be done in either

directly or indirectly.
In indirect addressing, register DX is used to hold the port address.
 Memory mapped I/O

• In memory mapped I/O technique, the I/O devices are

viewed as memory locations and are addressed likewise.
• In memory mapped interfacing, all the available address
lines are used for address decoding.
• But memory mapped method is seldom used in 8086
programming, as memory-mapped I/O devices will
occupy a portion of the memory system for the I/O map.
This reduces the amount of memory available for other
applications.
One advantage of memory mapped I/O method is that,
it uses any instruction that transfers data between the
µ-p and the memory (like MOV) to access an I/O
device.

For ex: MOV [BX], AX and MOV AX,[BX] can be

used for outputting and inputting 8/16 bit data from or
to an 8/16 bit register addressed by the 20 bit memory-
mapped port location computed from DS and BX.
 I/O port address decoding
• I/O port address decoding is similar to the memory
address decoding.
• The main difference between memory mapped decoding
and isolated I/O decoding is the number of address pins
connected to the decoder.
• Normally decoding is done on A15-A0 lines (port address
bits) for the isolated I/O.
• In port mapped I/O, use of IORC and IOWC signals will
activate I/O devices for a read/write operation
respectively.
Basic I/O interfaces
• The basic input device interface uses a set
of tri-state buffers.
• The basic output device interface uses a set
of data latches.
The basic input interface

• The external data (eg: typed through a keyboard) are

connected to the inputs of the tri-state buffer. The
outputs of the buffer connects to the data bus.
• The exact data bus connections depend on the version
of the microprocessor.
• For eg: 8088 has data bus connections D 7 –D0, 8086 has
data bus connections D15 – D0 , 80486 has D31 – D0 , P4
has D63 – D0 etc….
The below circuit depicts how the microprocessor read the
contents of an input device.
• When the microprocessor executes an IN instruction,
the I/O port address is decoded to generate a logic 0 on
SEL.
• A zero placed on the output control inputs (1G & 2G) of
the 74ALS244 buffer causes the data input connections
(O) to be connected to the data output (D) connections.
• When a logic 1 is placed on the output control inputs
SEL, the device will be effectively disconnected from
the data bus.
• The basic circuit must appear any time that the input
data is interfaced to the microprocessor.
Interfacing 8086 with 74LS245 buffer
The basic output interface

• The basic output interface receives data from the

microprocessor and usually hold it for some external
device.
• A latch stores the data output by the microprocessor,
from the data bus.
• Without a latch, the viewer would never see the LEDs
illuminate.
• When the OUT instruction executes, the data from AL
or AX are transferred to the latch via the data bus.
The figure below shows, how a simple LED (Light Emitting Diode)
connect to the microprocessor through a data latch
• In the above figure D inputs of the latch connected to
the data bus is to capture the output data and the Q
outputs of the latch are attached to the LEDs.
• When a Q output becomes a logic 0 the LED lights.
• Each time that the OUT instruction executes, the SEL
signal to the latch activates, capturing the data from the
data bus.
• Thus, whenever the output instruction is executed in the
circuit, the data from the register appear on the LED.
• Normally, lots of hardware components are required to decode
the port address absolutely. Thus instead of decoding the address
completely, only a part of it may be decoded.
• For ex: instead of using 16 address lines(A15-A0),one may use
only A3-A0.
• This is mainly useful for only smaller systems containing small
I/O ports.
• The next diagram shows how 8086 is interfaced with 74LS373
latch.(It also shows the interfacing with input port 74LS245)
• The output from the 74LS373 output port is given to a BCD to
7-segment decoder for the purpose of display.
• The following circuit clearly depicts the flow from a switch to a
7-segment display
Interfacing 8086 with a buffer and a latch
Hand shaking
Many I/O devices accept or release information
at a much slower rate than the microprocessor.
A method of I/O control, called handshaking or
polling, synchronizes the I/O device with the
microprocessor.
The figure below depicts the synchronization process between a µ-p and a
printer
• BUSY indicates that the printer is busy and STB(Strobe)
is a clock pulse used to send data to the printer for
printing.
• The data to be printed by the printer are placed on the data
line and a pulse is then applied to the STB connection.
• The Strobe signal sends or clocks the data into the printer
so that it can be printed.
• As soon as the printer receives the data, it places a logic 1
on the BUSY pin, indicating that the printer is busy with
printing data.
• The microprocessor tests or polls the BUSY pin to
decide whether the printer is busy or not.
• If the printer is busy, microprocessor waits and if
the printer is not busy the microprocessor sends
the next ASCII character to the printer.
• This process of interrogating the external devices
(like printer) is called handshaking or polling.
ALL THE BEST

Thank you