Digital logic design by Abinet.

5. Analysis and Synthesis Combinational logic circuit

 The digital system consists of two types of circuits, namely
I. Combinational circuits and
II. Sequential circuits
 A combinational circuit consists of logic gates, where outputs are at any instant and
are determined only by the present combination of inputs.
 Sequential circuits contain logic gates as well as memory cells.
 Their outputs depend on the present inputs and also on the states of memory
elements.
 A combinational circuit consists of input variables, logic gates, and output variables.
 The logic gates accept signals from inputs and output signals are generated
according to the logic circuits employed in it.
 Figure below shows a block diagram of a combinational logic circuit.
 There are n number of input variables coming from an electric source and m
number of output signals go to an external destination.

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 Digital logic design by Abinet.A

THE UNIVERSAL PROPERTY OF NAND AND NOR GATES

The NAND Gate as a Universal Logic Element
• The NAND gate is a universal gate because it can be used to produce the NOT, the
AND, the OR, and the NOR functions.

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Digital logic design by Abinet.A

The NOR Gate as a Universal Logic Element

• Like the NAND gate, the NOR gate can be used to produce the NOT, AND. OR and
NAND functions.

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 Digital logic design by Abinet.A

COMBINATIONAL LOGIC USING NAND AND NOR GATES

a) NAND Implementation
 The NAND gate is said to be a universal gate because any digital system can be
implemented with it.
 To facilitate the conversion to NAND logic, it is convenient to use the two alternate
graphic symbols shown in Figure below.

FIGURE. Two graphic symbols for a NAND gate

 The AND-invert graphic symbol consists of an AND graphic symbol followed by a

small circle.
 The invert-OR graphic symbol consists of an OR graphic symbol that is preceded by
small circles in all the inputs.
 Either symbol can be used to represent a NAND gate.

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Digital logic design by Abinet.A
Cont..
• To obtain a multilevel NAND diagram from a Boolean expression, proceed as
follows:
a. From the given Boolean expression, draw the logic diagram with AND, OR, and
inverter gates. Assume that both the normal and complement inputs are
available.
b. Convert all AND gates to NAND gates with AND-invert graphic symbols.
c. Convert all OR gates to NAND gates with invert-OR graphic symbols.
d. Check all small circles in the diagram. For every small circle that is not
compensated by another small circle along the same line, insert an inverter
(one-input NAND gate) or complement the input variable.
 In general, the number of NAND gates required to implement a Boolean expression
is equal to the number of AND-OR gates except for an occasional inverter.
 Example: implement using only NAND gates.
a) F = A + (B’ + C)(D’ + BE’)
b) F = (CD + E)(A + B’)
c) F = BC’ + A(B + CD)
d) F = (AB' + CD')E + BC(A + B)
e) F = w(x + y + z) + xy;
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Digital logic design by Abinet.A
b) NOR implementation
• The two graphic symbols for the NOR gate are shown in Fig. below.

• The OR-invert symbol defines the NOR operation as an OR followed by a

complement.
• The invert-AND symbol complements each input and then performs an AND
operation.
• The two symbols designate the same NOR operation and are logically identical
because of DeMorgan's theorem.
• The procedure for implementing a Boolean function with NOR gates is similar to
the procedure outlined in the previous section for NAND gates.
a. Draw the AND-OR logic diagram from the given algebraic expression Assume
that both the normal and complement inputs are available.
b. Convert all OR gates to NOR gates with OR-invert graphic symbols.
c. Convert all AND gates to NOR gates with invert-AND graphic symbols.
d. Any small circle that is not compensated by another small circle along the
same line needs an inverter or the complementation of the input variable.
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Digital logic design by Abinet.A
Cont…
• Example: implement the following Boolean function using only NOR gates.
a. F = (AB + E)(C + D)
b. F = A + (B’ + C)(D’ + BE’)
c. F = (CD + E)(A + B’)
d. F = [(C + D)B' + A](B + C')
e. F = (AB' + CD')E + BC(A + B)
f. F = w(x + y + z) + xy;
 Convert the logic diagram the following to a multiple-level NAND and NOR circuit

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 Design of combinational logic circuits
Digital logic design by Abinet.A

a) HALF-ADDER
 The half-adder accepts two binary digits on its inputs and produces two binary
digits on its outputs, a sum bit and a carry bit.
 The Sout represents the least significant bit of the sum.
 The Cout represents the most significant bit of the sum.
 The Boolean functions for the two output from the truth table:
 S = x’y+ xy’ = x⊕y
 C = xy

Implementation of Half-Adder

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 b) The Full-Adder
Digital logic design by Abinet.A

 The full-adder accepts two input bits and an input carry and generates a sum
output and an output carry.
 The basic difference between a full-adder
and a half-adder is that the full-adder accepts an input carry.
 The Boolean functions for the two out put from the truth table:
 Using x-OR, S = x’y’z + x’yz’ + xy’z’ + xyz = x⊕y⊕z
C = x’yz + xy’z + xyz’ + xyz = xy + z(x ⊕y)
Implementation of Full Adder with Two Half
Adders and an OR Gate

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 c) Binary Parallel Adder
Digital logic design by Abinet.A

 A binary parallel adder is a digital circuit that produces the arithmetic sum of two
binary numbers in parallel.
 It consists of full-adders connected in a chain, with the output carry from each full-
adder connected to the input carry of the next full-adder in the chain.
 Figure below shows the interconnection of four full-adder (FA) circuits to provide a
 4-bit binary parallel adder.
 An n-bit parallel adder requires n full-adders.

 Example:
a) What are the sum outputs when 111 and 101 are added by the 3-bit parallel adder?
b) What are the sum outputs when 1110 and 1011 are added by the 4-bit parallel adder?

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 Digital logic design by Abinet.A
d) MAGNITUDE COMPARATOR
 The comparison of two numbers is an operation that determines if one number is
greater than, less than, or equal to the other number.
 A magnitude comparator is a combinational circuit that compares two numbers, A
and B, and determines their relative magnitudes.
 The outcome of the comparison is specified by three binary variables that indicate
whether A > B, A = B, or A < B.
 Algorithm
 A = A 3A 2 A 1 A 0 ; B = B 3 B 2B 1B 0
 A=B if A3=B3, A2=B2, A1=B1and A1=B1
 equality: xi= AiBi + Ai'Bi'
 (A=B) = x3x2x1x0
 If the corresponding digit of A is 1 and that of B is 0, we conclude that A > B.
 If the corresponding digit of A is 0 and that of B is 1, we have that A < B.
 (A>B) = A3B3‘ + x3A2B2‘ + x3x2A1B1‘ + x3x2x1 A0B0'
 (A<B) = A3'B3 + x3A2'B2 + x3x2A1'B1 + x3x2x1 A0'B0
 Implementation
 xi = (AiBi‘ + Ai'Bi)' 11
 .
Digital logic design by Abinet.A

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 e) DECODERS
Digital logic design by Abinet.A

 A decoder is a combinational circuit that converts binary information from n input lines to a
maximum of 2n unique output lines.
 If the n-bit decoded information has unused or don't-care combinations, the decoder output
will have fewer than 2n output.
 The decoders presented here are called n-to-m-line decoders, where m <= 2 n.
 Their purpose is to generate the 2n (or fewer) minterms of n input variables.
 The name decoder is also used in conjunction with some code converters such as a BCD-to-
seven segment decoder.
 Only one output can be active (high) at any times.

a) Truth table
b) Block diagram
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 Digital logic design by Abinet.A
Combinational Logic Implementation using decoder
 A decoder provides the 2n minterm of n input variables. Since any Boolean function can be
expressed in sum of minterms canonical form, one can use a decoder to generate the
minterms and an external OR gate to form the sum.
 In this way, any combinational circuit with n inputs and m outputs can be implemented with
an n-to-2n- line decoder and m OR gates.
 The procedure for implementing a combinational circuit by means of a decoder and OR gates
requires that the Boolean functions for the circuit be expressed in sum of minterms.
 Example:-Implement a full-adder circuit with a decoder and two OR gates.
 From the truth table of the full-adder, we obtain the functions for this combinational circuit
in sum of minterms:
S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)

Example: A combinational circuit is defined by the

following three Boolean functions.
Design the circuit with a decoder and external gates.
F1 = x'y'z' + XZ
F2 = xy'z' + x'y
F3 = x'y'z + xy

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 Decoder with enable input
Digital logic design by Abinet.A

 Normally every commercially available decoder ICs have a special input other than normal
working input variables called ENABLE.
 The use of this ENABLE input is that when activated the complete IC comes to the working
condition for its normal functioning.
 If ENABLE input is deactivated the IC goes to sleep mode, the normal functioning is
suspended, and all the outputs become logic 0 irrespective of normal input variables
conditions.
 Its function is build higher decoder from lower decoders.

E A B D0 D1 D2 D 3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1 Figure: 2-to-4 decoder with enable input E.

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 Cont…
Digital logic design by Abinet.A

 Example:- Construct a 3-to-8 line decoder with the use of a 2-to-4 line decoder.

 Example:- Construct a 4-to-16 line decoder with the use of a 2-to-4 line decoder.
 Example:- Construct a 5-to-32 line decoder with the use of a 3-to-8 line decoder.

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 j) Encoders
Digital logic design by Abinet.A

 An encoder is a digital circuit that performs the inverse operation of a decoder.

 An encoder has 2n (or fewer) input lines and n output lines.
 The output lines generate the binary code corresponding to the input value.
 It is assumed that only one input has a value of 1 at any given time; otherwise the
circuit has no meaning.
 The encoder can be implemented with OR gates whose inputs are determined
directly from the truth table.
 These conditions can be expressed by the following output Boolean functions:

Truth table of 8x3 encoder

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 Digital logic design by Abinet.A
MULTIPLEXERS OR DATA SELECTORS
 A digital multiplexer is a combinational circuit that selects binary information from one of
the 2n input channels and transmits to a single output line.
 That is why the multiplxers are also called data selectors.
 The selection of the particular input channel is controlled by a set of select inputs.
 Select binary information from one of many input lines and direct it to a single output line
 2n input lines, n selection lines and one output line

 e.g.: 2-to-1-line multiplexer

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 Cont..
Digital logic design by Abinet.A

 Example: a logic circuit, for 4x1 multiplexer

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 Cont.…
Digital logic design by Abinet.A

 As in decoders, multiplexer ICs may have an enable input to control the operation of the
unit.
 When the enable input is in a given binary state, the outputs are disabled, and when it is in
the other state (the enable state), the circuit functions as a normal multiplexer.
 The enable input (sometimes called strobe) can be used to expand two or more multiplexer
ICs to a digital multiplexer with a larger number of inputs.
 Example:- Construct a 8-to-1 multiplexer with the use of a 4-to-1 line multiplexer and
external gate.
 Example:- Construct a 16-to-1 multiplexer
with the use of only a 4-to-1 line multiplexer.

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 Demultiplexer
Digital logic design by Abinet.A

 A demultiplexer is a circuit that receives information from a single line and directs it to one
of 2n possible output lines.
 The selection of a specific output is controlled by the bit combination of n elected lines.
 The term “demultiplex” means one into many.

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 PARITY GEINERATOR AND CHECKER
Digital logic design by Abinet.A

 Whenever information is transmitted from one device (the transmitter) to another device
(the receiver), there is a possibility that errors can occur such that the receiver does not
receive the identical information that was sent by the transmitter.
 One of the simplest and most widely used schemes for error detection is the parity method.
 Parity Bit:- A parity bit is an extra bit that is attached to a code group that is being
transferred from one location to another.
 The parity bit is made either 0 or 1, depending on the number of is that are contained in the
code group. Two different methods are used.
 The even-parity method, and
 The odd-parity method.
 In the even-parity method, the value of the parity bit is chosen so that the total number of
1s in the code group (including the parity bit) is an even number.

 In the odd-parity method, the value of the parity bit is chosen so that the total number of 1s
in the code group (including the parity bit) is an odd number.

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 Cont…
Digital logic design by Abinet.A

 A parity generator is a combination logic system to generate the parity bit at the transmitting
side.
 Parity Checker:- The message bits with the parity bit are transmitted to their destination,
where they are applied to a parity checker circuit.
 The circuit that checks the parity at the receiver side is called the parity checker.
 The parity checker circuit produces a check bit and is very similar to the parity generator
circuit.
 If the check bit is 1, then it is assumed that the received data is incorrect. The check bit will
be 0 if the received data is correct.

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