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5-Harvard Architecture - CISC & RISC Architectures-10!01!2024

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40 views18 pages

5-Harvard Architecture - CISC & RISC Architectures-10!01!2024

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shashank.reddy5804
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BCSE205L - Computer Architecture

and Organization

Dr. R. Arumuga Arun,


Cabin : PRP 315(A&B)-19,
Mailid : [email protected].
Module 1:
Module:1 Introduction to computer architecture and
organization.

Overview of Organization and Architecture –


Functional components of a computer: Registers and
register files - Interconnection of components -
Overview of IAS computer function - Organization of
the von Neumann machine - Harvard architecture -
CISC & RISC Architectures
Topics
Harvard architecture
CISC & RISC Architectures
Von Neumann bottleneck
To enhance performance, we cannot get away from the
fact that instructions can only be done one at a time and
can only be carried out sequentially
Creates an inadequate rate of data transfer between
Memory and processor
Both of these factors hold back the competence of the CPU
This is referred to as the ‘Von Neumann bottleneck.
Harvard architecture
The Harvard architecture is a computer architecture with
physically separate storage and signal pathways for
instructions and data.
It was basically developed to overcome the bottleneck of Von
Neumann Architecture
The main advantage of having separate buses for instruction
and data is that the CPU can access instructions and
read/write data at the same time
Programs needed to be loaded by an operator the processor
could not initialize itself
In a Harvard architecture, there is no need to make the two
memories share characteristics
Harvard architecture
In particular, the word width, timing, implementation
technology, and memory address structure can differ
Instructions read-only memory
Data memory read-write memory
In some systems there is much more instruction memory
than data memory so instruction addresses are wider than
data addresses
Von-Neumann Vs Harvard
Modified Harvard Architecture
A modified Harvard architecture machine is very much like
a Harvard architecture machine, but it relaxes the strict
separation between instruction and data while still letting
the CPU concurrently access two (or more memory buses).
The most common modification includes separate
instruction and data caches backed by a common address
space
While the CPU executes from the cache, it acts as a pure
Harvard machine
When accessing backing memory, it acts like a von
Neumann machine
RISC Architecture
RISC :- Reduced Instruction Set Computer Processor
A microprocessor architecture with a simple collection and
highly customized set of instructions.
It is built to minimize the instruction execution time by
optimizing and limiting the number of instructions.
It means each instruction cycle requires only one clock
cycle, and each cycle contains three parameters: fetch,
decode and execute.
RISC chips require several transistors, making it cheaper
to design and reduce the execution time for instruction.
Features of RISC Processor
One cycle execution time: For executing each instruction in a
computer, the RISC processors require one CPI (Clock per
cycle).
Pipelining technique: The pipelining technique is used in the
RISC processors to execute multiple parts or stages of
instructions to perform more efficiently.
A large number of registers: RISC processors are optimized
with multiple registers that can be used to store instruction and
quickly respond to the computer and minimize interaction with
computer memory.
It supports a simple addressing mode and fixed length of
instruction for executing the pipeline.
Features of RISC Processor
It uses LOAD and STORE instructions to access the
memory location.
Simple and limited instruction reduces the execution time
of a process in a RISC.
RISC uses the Harvard memory model means it is Harvard
Architecture.
RISC Processor
CISC Architecture
CISC :- Complex Instruction Set Computer Processor
It has a large collection of complex instructions that range
from simple to very complex and specialized in the
assembly language level, which takes a long time to
execute the instructions.
CISC approaches reducing the number of instructions on
each program and ignoring the number of cycles per
instruction.
Each instruction set has an additional than 300 separate
instructions.
Maximum instructions are finished in two to ten machine
cycles.
CISC Architecture
CISC chips are relatively slower as compared to RISC
chips but use little instruction than RISC.
They achieve low-level processes, which makes it easier to
have huge addressing modes and additional data types in
the hardware of a machine
Features of CISC Processor
CISC or complex instructions may take longer than a single
clock cycle to execute the code.
Less instruction is needed to write an application.
It provides easier programming in assembly language.
Support for complex data structure and easy compilation of
high-level languages.
It is composed of fewer registers and more addressing
modes, typically 5 to 20.
Instructions can be larger than a single word.
It emphasizes the building of instruction on hardware
because it is faster to create than the software.
CISC Processor
C
CISC VS RISC
References
William Stallings “Computer Organization and
architecture”, Prentice Hall, 7th edition, 2006.

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