EE 382V Fall 2006

VLSI Physical Design Automation

Lecture 3. Circuit Partitioning

Prof. David Pan

[email protected]
Office: ACES 5.434

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 Survey # 1 Results
❁ Most of you prefer (2) and (3)
❁ Most of you plan to spend “much time” 
❁ Some suggestions (not much yet )
❁ examples
❁ provide industry perspectives
❁ can choose project topics

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System Hierarchy

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 Levels of Partitioning
System
System Level Partitioning

PCBs
Board Level Partitioning

Chips

Chip Level Partitioning

Subcircuits
/ Blocks
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Partitioning of a Circuit

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 Importance of Circuit Partitioning
❁Divide-and-conquer methodology
The most effective way to solve problems of high complexity
E.g.: min-cut based placement, partitioning-based test generation,…
❁System-level partitioning for multi-chip designs
inter-chip interconnection delay dominates system performance.
❁Circuit emulation/parallel simulation
partition large circuit into multiple FPGAs (e.g. Quickturn), or
multiple special-purpose processors (e.g. Zycad).
❁Parallel CAD development
Task decomposition and load balancing
❁In deep-submicron designs, partitioning defines local and global
interconnect, and has significant impact on circuit performance
…… ……

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 Some Terminology

Partitioning: Dividing bigger circuits into a small number of

partitions (top down)
Clustering: cluster small cells into bigger clusters (bottom up).
Covering / Technology Mapping: Clustering such that each
partitions (clusters) have some special structure (e.g., can be
implemented by a cell in a cell library).
k-way Partitioning: Dividing into k partitions.
Bipartitioning: 2-way partitioning.
Bisectioning: Bipartitioning such that the two partitions have the
same size.

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 Circuit Representation
• Netlist: B
– Gates: A, B, C, D A
– Nets: {A,B,C}, {B,D}, {C,D}

C D
• Hypergraph:
– Vertices: A, B, C, D
– Hyperedges: {A,B,C}, {B,D}, {C,D}
B
– Vertex label: Gate size/area A
– Hyperedge label:
Importance of net (weight)
C D
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Circuit Partitioning Formulation

Bi-partitioning formulation:
Minimize interconnections between partitions
c(X,X’)

X X’

❁Minimum cut: min c(x, x’)

❁minimum bisection: min c(x, x’) with |x|= |x’|
❁minimum ratio-cut: min c(x, x’) / |x||x’|

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 A Bi-Partitioning Example

a c 100 e
100 100
100 100
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min-cut
4

b 10 d 100 f

mini-ratio-cut min-bisection

Min-cut size=13
Min-Bisection size = 300
Min-ratio-cut size= 19

Ratio-cut helps to identify natural clusters

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Circuit Partitioning Formulation (Cont’d)

General multi-way partitioning formulation:

Partitioning a network N into N1, N2, …, Nk such that
❁ Each partition has an area constraint

∑a(v) ≤ A i
v ∈Ni

❁ each partition has an I/O constraint

c( Ni , N − Ni ) ≤ Ii

Minimize the total interconnection:

∑ c( N , N − N )
i i
Ni

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 Partitioning Algorithms

❁Iterative partitioning algorithms

❁Spectral based partitioning algorithms
❁Net partitioning vs. module partitioning
❁Multi-way partitioning
❁Multi-level partitioning
❁Further study in partitioning techniques
(timing-driven …)

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Iterative Partitioning Algorithms

❁Greedy iterative improvement method

[Kernighan-Lin 1970]
[Fiduccia-Mattheyses 1982]
[krishnamurthy 1984]

❁Simulated Annealing
[Kirkpartrick-Gelatt-Vecchi 1983]
[Greene-Supowit 1984]

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 Kernighan-Lin Algorithm
“An Efficient Heuristic Procedure for
Partitioning Graphs”
The Bell System Technical Journal
49(2):291-307, 1970

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 Restricted Partition Problem
• Restrictions:
– For Bisectioning of circuit.
– Assume all gates are of the same size.
– Works only for 2-terminal nets.

• If all nets are 2-terminal,

the Hypergraph is called a Graph.
B B
A A

Hypergraph Graph
Representation C D Representation C D

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 Problem Formulation
• Input: A graph with
– Set vertices V. (|V| = 2n)
– Set of edges E. (|E| = m)
– Cost cAB for each edge {A, B} in E.
• Output: 2 partitions X & Y such that
– Total cost of edges cut is minimized.
– Each partition has n vertices.

• This problem is NP-Complete!!!!!

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 A Trivial Approach
• Try all possible bisections. Find the best one.
• If there are 2n vertices,
# of possibilities = (2n)! / n!2 = nO(n)

• For 4 vertices (A,B,C,D), 3 possibilities.

1. X={A,B} & Y={C,D}
2. X={A,C} & Y={B,D}
3. X={A,D} & Y={B,C}

• For 100 vertices, 5x1028 possibilities.

• Need 1.59x1013 years if one can try 100M possbilities per
second.

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 Idea of KL Algorithm
• DA = Decrease in cut value if moving A
– External cost (connection) EA – Internal cost IA
– Moving node a from block A to block B would increase the value of
the cutset by EA and decrease it by IA

X B Y X B Y
C
C
A D A D

DA = 2-1 = 1
DB = 1-1 = 0
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 Idea of KL Algorithm
• Note that we want to balance two partitions
• If switch A & B, gain(A,B) = DA+DB-2cAB
– cAB : edge cost for AB

X B Y X B Y
C C
D
A A D
gain(A,B) = 1+0-2 = -1

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 Idea of KL Algorithm
• Start with any initial legal partitions X and Y.
• A pass (exchanging each vertex exactly once) is
described below:
1. For i := 1 to n do
From the unlocked (unexchanged) vertices,
choose a pair (A,B) s.t. gain(A,B) is largest.
Exchange A and B. Lock A and B.
Let gi = gain(A,B).
2. Find the k s.t. G=g1+...+gk is maximized.
3. Switch the first k pairs.
• Repeat the pass until there is no improvement (G=0).

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 Example
X Y X Y
1 4 4 1
2 5
2 5

3 6 3 6

Original Cut Value = 9 Optimal Cut Value = 5

A good step-by-step example in SY book

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 Time Complexity of KL
• For each pass,
– O(n2) time to find the best pair to exchange.
– n pairs exchanged.
– Total time is O(n3) per pass.
• Better implementation can get O(n2log n) time per
pass.

• Number of passes is usually small.

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 Recap of Kernighan-Lin’s Algorithm
❁Pair-wise exchange of nodes to reduce cut size
❁Allow cut size to increase temporarily within a pass
Compute the gain of a swap
Repeat
Perform a feasible swap of max gain u• v•
Mark swapped nodes “locked”;
v• u•
Update swap gains;
Until no feasible swap; locked
Find max prefix partial sum in gain sequence g1, g2,
…, gm
Make corresponding swaps permanent.

❁Start another pass if current pass reduces the cut

size
(usually converge after a few passes)
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 A Useful Survey Paper
• Charles Alpert and Andrew Kahng, “Recent Directions
in Netlist Partitioning: A Survey”, Integration: the VLSI
Journal, 19(1-2), 1995, pp. 1-81.

• Next lecture: more on partitioning

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