Basic Verilog FSM

Examples

(based on slides from Eric

Crabill SJSU / Xilinx)
 Finite State Machines

• A state machine is:

– A set of input events
– A set of output events
– A set of states
– A function that maps states and input to output
– A function that maps states and inputs to states
– A description of the initial state
 Finite State Machines
• A finite state machine is one that has a limited,
or finite, number of states.
• The machine state is described by a collection
of state variables.
• A finite state machine is an abstract concept,
and may be implemented using a variety of
techniques, including digital logic.
 Finite State Machines
• For an edge-triggered, synchronous FSM
implemented in digital logic, consider:
– A set of input events (input signals, including clock)
– A set of output events (output signals)
– A set of states (state variables are flip flops)
– A function that maps states and input to output
(this is the output logic)
– A function that maps states and inputs to states
(this is the next-state logic)
– A description of the initial state (initial flip flop value)
 Finite State Machines
• Consider this edge-triggered, synchronous
FSM to be implemented in digital logic:
– A set of states
restart or pause

– A set of input events

FIRST
– A function that maps
states and inputs to states !restart and !pause
restart or !pause

– A description of the restart

initial state
SECOND THIRD
!restart and !pause

!restart and pause

!restart and pause
 Finite State Machines
• Things that are not shown (yet):
– A set of output events
– A function that maps states
and input to output restart or pause

• For now, let’s work on FIRST

modeling the FSM !restart and !pause

restart or !pause

without the outputs

restart

and output logic. SECOND

!restart and !pause
THIRD

!restart and pause

!restart and pause
 Finite State Machines
• The state variables must be able to represent
at least three unique states for this FSM.
– A flip flop has two unique states.
– N flip flops can represent up 2N unique states.
– How many flip flops are required for three states?
• One flip flop is not enough.
• Two flip flops are minimally sufficient.
• More flip flops may be used, if desired.
 Finite State Machines
• Select a state encoding method:
– Binary
State Binary Gray Johnson One Hot

– Gray 0
1
3'b000
3'b001
3'b000
3'b001
4'b0000
4'b0001
8'b00000001
8'b00000010
2 3'b010 3'b011 4'b0011 8'b00000100

– Johnson 3
4
3'b011
3'b100
3'b010
3'b110
4'b0111
4'b1111
8'b00001000
8'b00010000
5 3'b101 3'b111 4'b1110 8'b00100000

– One Hot 6
7
3'b110
3'b111
3'b101
3'b100
4'b1100
4'b1000
8'b01000000
8'b10000000

– Custom
• Your encoding selection may require more than
the minimally sufficient number of flip flops.
 Finite State Machines
• Describe the state variables in Verilog.
• Provide a mechanism to force an initial state.
• Describe a function that maps inputs and
current state to a new, or next state.
– Literal transcription of excitation equations
– Behavioral description using case, if-else, etc…
• Some additional things to consider:
– Resets, synchronous or asynchronous?
– Unused states (error, or no resets) and recovery
 Finite State Machines
• Describe it in Verilog just like the block diagram!
• I have selected a custom state encoding.

NEXT STATE NEXT

STATE STATE
LOGIC STATE VARIABLES
INPUTS
(COMBINATIONAL) (SEQUENTIAL)

SYNC RESET ASYNC RESET

 Finite State Machines
module fsm (state, pause, restart, clk, rst);

input pause, restart, clk, rst;

• Two flip flops for state
• Note use of parameters;
output [1:0] state;

reg [1:0] state;

reg [1:0] next_state;

parameter [1:0] FIRST = 2'b11;

parameter [1:0] SECOND = 2'b01;
easy to change encoding
parameter [1:0] THIRD = 2'b10;

always_ff @(posedge clk or posedge rst) // sequential

begin
• Asynchronous reset is
implemented with state
if (rst) state <= FIRST;
else state <= next_state;
end

• Synchronous reset is
always_comb // combinational
begin
case(state)
FIRST: if (restart | pause) next_state = FIRST;
else next_state = SECOND;
SECOND: if (restart) next_state = FIRST;
else if (pause) next_state = SECOND;
implemented with logic
else next_state = THIRD;
THIRD: if (!restart & pause) next_state = THIRD;
else next_state = FIRST;
default: next_state = FIRST;
• Default clause covers the
one unused state
endcase
end

endmodule

• Explicit next state signal

 Finite State Machines
• You can also describe it in one procedural block.
– No access to “next state” signal (important?)
– More compact...

UNIFIED PROCEDURAL DESCRIPTION

NEXT STATE STATE STATE

LOGIC VARIABLES
INPUTS
(COMBINATIONAL) (SEQUENTIAL)

SYNC RESET ASYNC RESET

 Finite State Machines

module fsm (state, pause, restart, clk, rst);

• Two flip flops for state
input pause, restart, clk, rst;
output [1:0] state; • Note use of parameters;
easy to change encoding
reg [1:0] state;

parameter [1:0] FIRST = 2'b11;

parameter [1:0] SECOND = 2'b01;

• Asynchronous reset and

parameter [1:0] THIRD = 2'b10;

always_ff @(posedge clk or posedge rst) // sequential

begin
if (rst) state <= FIRST;
else
begin
synchronous reset both
implemented; distinction
case(state)
FIRST: if (restart | pause) state <= FIRST;
else state <= SECOND;
SECOND: if (restart) state <= FIRST;

THIRD:
else if (pause) state <= SECOND;
else state <= THIRD;
if (!restart & pause) state <= THIRD;
is made by sensitivity list
else state <= FIRST;
default: state <= FIRST;
endcase
end
• Default clause covers the
one unused state
end

endmodule

• Implicit next state signal

 Finite State Machines
• Now, let’s consider the following:
– A set of output events
– A function that maps states restart or pause

and input to output terminal = 0

FIRST
• Suppose there are three even = 0
odd = 1

desired outputs: !restart and !pause

terminal = 0
restart or !pause
terminal = 1
restart

– odd terminal = 0

SECOND THIRD
– even even = 1
odd = 0 !restart and !pause
even = 0
odd = 1
terminal = 0

– terminal !restart and pause

!restart and pause
terminal = 0

terminal = 0
 Finite State Machines
• The “odd” output is asserted
in FIRST and THIRD.
• The “even” output is restart or pause
terminal = 0

asserted in SECOND. FIRST

even = 0
odd = 1

• The “terminal” output !restart and !pause restart or !pause

is asserted to indicate
terminal = 0 terminal = 1
restart
terminal = 0

the FSM will transition SECOND even = 1

THIRD
even = 0

from THIRD to FIRST. odd = 0 !restart and !pause odd = 1

terminal = 0
!restart and pause

!restart and pause terminal = 0

terminal = 0
 Finite State Machines
• Outputs that require functions of only the
current state are Moore type outputs.
– This includes using state bits directly.
– Outputs “odd” and “even” are Moore outputs.
• Outputs that require functions of the current
state and the inputs are Mealy type outputs.
– Output “terminal” is a Mealy output.
• Consider the latency and cycle time tradeoffs.
 Finite State Machines
• Describe the output functions in Verilog,
just as shown in the block diagram...
EXPLICIT OR IMPLICIT DESCRIPTION

NEXT

NEXT STATE STATE

STATE STATE OUTPUT OUTPUTS

INPUTS
LOGIC VARIABLES LOGIC

SYNC RESET ASYNC RESET

 Finite State Machines
module fsm (state, odd, even, terminal, pause, restart, clk, rst);

• Started with the FSM

input pause, restart, clk, rst;
output [1:0] state;
output odd, even, terminal;

reg [1:0] state;

reg [1:0] next_state; described using explicit
next state logic, but could
parameter [1:0] FIRST = 2'b11;
parameter [1:0] SECOND = 2'b01;
parameter [1:0] THIRD = 2'b10;

always_ff @(posedge clk or posedge rst) // sequential

begin
if (rst) state <= FIRST;
have used the other one.
else state <= next_state;
end

always_comb // combinational
• Added three assignment
begin
case(state)
FIRST: if (restart | pause) next_state = FIRST;
else next_state = SECOND;
statements to create the
output functions.
SECOND: if (restart) next_state = FIRST;
else if (pause) next_state = SECOND;
else next_state = THIRD;
THIRD: if (!restart & pause) next_state = THIRD;
else next_state = FIRST;
default: next_state = FIRST;
endcase
end

// output logic described using continuous assignment

assign odd = (state == FIRST) | (state == THIRD);
assign even = (state == SECOND);
assign terminal = (state == THIRD) & (restart | !pause);

endmodule
 Finite State Machines
module fsm (state, odd, even, terminal, pause, restart, clk, rst);

input pause, restart, clk, rst;

output [1:0] state;
output odd, even, terminal; • Started with the FSM
described using implicit
reg [1:0] state;
reg odd, even, terminal;

parameter [1:0] FIRST = 2'b11;

parameter [1:0] SECOND = 2'b01;
parameter [1:0] THIRD = 2'b10; next state logic, but could
have used the other one.
always_ff @(posedge clk or posedge rst) // sequential
begin
if (rst) state <= FIRST;
else

• This describes the same

begin
case(state)
FIRST: if (restart | pause) state <= FIRST;
else state <= SECOND;

output logic as before, but

SECOND: if (restart) state <= FIRST;
else if (pause) state <= SECOND;
else state <= THIRD;

uses a procedural block

THIRD: if (!restart & pause) state <= THIRD;
else state <= FIRST;
default: state <= FIRST;
endcase

to create the outputs.

end
end

// output logic described using procedural assignment

always_comb
begin
odd = (state == FIRST) | (state == THIRD);
– Could have used case…
even = (state == SECOND);
terminal = (state == THIRD) & (restart | !pause);
end – Could have used if-else...
endmodule