EMBEDDED SYSTEMS

UNIT iV
COMMUNICATIONS
1. The MSP430 contains built-in features for both parallel and
serial data communication.
2. The communication modules available for the MSP430
family of microcontrollers are USART (Universal
Synchronous/Asynchronous Receiver/Transmitter), USCI
(Universal Serial Communication Interface) and USI
(Universal Serial Interface).
3. These provide asynchronous data transmission between the
MSP430 and other peripheral devices when configured in
UART mode.
4. They also support data transmission synchronized to a
clock signal through a serial I/O port in Serial Peripheral
Interface (SPI) and Inter Integrated Circuit (I2C) modes.
5.1 INTRODUCTION

An important feature of modern microprocessor based systems

is their communication capability, that is, their ability to
exchange information with other systems in the surrounding
environment. The communications interfaces can be used for
firmware update or loading local parameters. At a higher level,
these interfaces can be used to exchange information in
applications with distributed processes.
5.2 COMMUNICATIONS SYSTEM MODEL

Any digital communication system has three devices:

Transmitter: Has the task of processing the information into the

appropriate format for subsequent transmission;

Receiver: Is in charge of collecting the information and extracting

the original data;

Communication medium: Provides the physical medium through

which the information flows and is commonly implemented as
twisted pair wire, optical fibre cable or radio frequency network.

DTE: Data Terminal Equipment;

DCE: Data Communications Equipment.
Character ASCII “W” parallel transmission.
 In serial communications, the physical transmission medium
needs only one signal line. The information is sent by the
transmitter as a sequence of bits, at a common rate established
between the transmitter and the receiver. Additional
information is needed to enable synchronization between the
communication participants:

 Start bit: Added to the beginning of the information

transmitted, the function of which is to the identify the
beginning of a new word;

 Stop bit: Indicates completion of the transfer and is added to

the end of the information transmitted.
 Character ASCII “W” serial transmission
The two communication modes both have their advantages and
disadvantages (see Table 5-1), but the parallel communication medium has
been losing importance to serial communication. Serial communications,
due to technological advances, have now achieved high transmission rates,
making them more attractive for the most applications.

Characteristic Parallel Serial

One line
Bus line One line per bit
Sequence of bits
All bits of one word
Sequence simultaneously
Transmission Low
rate High
Short and long distance
Bus length Short Distances
Low
Cost High
Asynchronous transmission
needs start and stop bits
Synchronous transmission
Critical Synchronization between the needs some other
characteristics different bits is demanding synchronisation
5.4 SYNCHRONOUS AND ASYNCHRONOUS SERIAL
COMMUNICATIONS
 Serial communications may be:
 Asynchronous: Where the transmission rate (baud rate) is fixed by the
transmitter. The receiver must know this rate and synchronize itself to the
transmitter when the start bit is detected;
 Synchronous: Where there is a synchronization clock signal between the
receiver and the transmitter.
 In synchronous communication, there is one unit that assumes the role of
master and one or more units that assume the role(s) of slave. The clock signal
generated by the master is used by the slave units to carry out the
loading/unloading of TX and RX registers. In this communication mode, it is
possible to transmit and receive simultaneously. In synchronous
communications, both the sender and receiver are synchronized with a clock or
a signal encoded into the data stream.
 Asynchronous communication requires nothing more than a transmitter, a
receiver and a wire. It is thus the simplest of serial communication protocols,
and the least expensive to implement. As the name implies, asynchronous
communication is performed between two (or more) devices which operate on
independent clocks. Therefore, even if the two clocks agree for a time, there is
no guarantee that they will continue to agree over extended periods.
COMPARISON BETWEEN ASYNCHRONOUS AND SYNCHRONOUS TRANSMISSION FORMATS

SNO ASYNCHRONOUS SERIAL SYNCHRONOUS SERIAL

COMMUNICATION COMMUNICATION
1. Transmitters and receivers are not Transmitters and receivers are
synchronized by clock. synchronized by clock.
2. Bits of data are transmitted at constant rate. Data bits are transmitted with
synchronisation of clock.
3. Characters may arrive at any rate at Character is received at constant
receiver. rate.
4. Data transfer is character oriented. Data transfer takes place in blocks.
5. Start and stop bits are required to establish Start and stop bits are not required to
communication of each other. establish communication of each
charcater. However, synchronisation
bits are required to transfer the data
block.
6. Used in low-speed transmission at about Used in high-speed transmissions.
speed less than 20kbps.
7. Example: UART, USB Example: SPI, I2C
 Types of serial Channels

 Serial channels are said to be simplex, half duplex, or full-duplex, depending

on their type of connectivity.

 A simplex serial channel transmits permanently in only one direction over a

dedicated link.
Examples: radio and TV broadcasts channels, printers and displays, or read-
only devices.

 A half-duplex serial channel features a single link that allows communication

in either direction, but only in one direction at a time. It is a serial transceiver.
Eg: Walkie – talkie

 Full Duplex: This type of data transmission allows data transfer in both
directions simultaneously.
Eg: Telephone line
5.5 ASYNCHRONOUS (UART) COMMUNICATIONS
PROTOCOL

As shown in Figure 3, the start bit identifies the

beginning of a transfer and is generated by a high-to-low
transition on the bus. Following the start bit there are the
seven or eight data bits (in this example, the ASCII code
for the text transfer uses seven bits). The verification bit
(parity bit) is sent after the data bits. To terminate the
transmission, one or two stop bits are used.
 5.5.1 Parity bit
 The parity bit verifies the integrity of information transmitted. The bit is added by
the transmitter and indicates whether the total number of bits at level "1" in the
message data are odd or even. The transmissions can be configured for odd or even
parity.
 Figure 4. Odd or even parity.

7 bit ASCII code Parity bit Parity bit

odd Even
Bit 1 2 3 4 5 6 7

B 0 1 0 0 0 0 1 1 0
Q 1 0 0 0 1 0 1 0 1
3 1 1 0 0 1 1 0 1 0
Z 0 1 0 1 1 1 1 0 1
5.5.2 BAUD RATE
 The transmission of the ASCII character "W" 7-bit character
requires eleven bits to be sent, with four additional bits being
used for control. This corresponds to a baud value of 11. If the
character transmission rate is 10 characters per second, it will
give a baud rate of 10x11 = 1100 baud/second.

 The baud rate is a basic parameter in serial asynchronous

communications. After the master and slave are synchronized
through the start bit, they must use the same baud rate in order
to know the appropriate moments to write (master) and read
(slave) the various bits of the word transmitted.

 Figure 5. Example: Sub-multiples of the unit’s clock source.

The most commonly used baud rates are shown in Table 5-2. The usual problem is that these
baud rates are not generally sub-multiples of the unit’s clock sources. The example in Figure
-5 illustrates this problem and shows how to solve it. The correct bit timing is obtained in two
steps:
•Clock initial division through the counter;
•Using a method to correct the problem of the inexact integer division of the clock signal by
the baud rate.
 5.6 SERIAL PERIPHERAL INTERFACE (SPI) COMMUNICATION PROTOCOL

 The SPI (Serial Peripheral Interface) bus is a standard for synchronous serial
communication developed by Motorola, which operates in full duplex mode. The
devices have a master/slave relationship and the communication is always initiated
by the master.
 Figure 6. Typical SPI communication system.

The SPI communications system shown in Figure 6 only supports one master, but can
support more than a slave. The distance between units should be minimized, ideally
limited to a single PCB. Special attention should be given to the polarity and phase of
the clock signal.
5.7 I2C (INTER-INTEGRATED CIRCUIT) PROTOCOL

 The I2C protocol is a multi-master synchronous serial computer bus developed by

Philips Semiconductors, with the main objective of establishing links between
integrated circuits and to connect low-speed peripherals.
 The protocol is based on hardware using two bi-directional open-drain bus lines
pulled up with resistors:
 SDA: Serial Data; SCL: Serial clock.
 Typical voltages used are +5.0 V or +3.3 V, although systems with other voltages are
possible.
 Figure 7. Typical I2C
communication system.
 The communications are always initiated and completed by the
master, which is responsible for generating the clock signal. In
more complex applications, the I2C system can operate in
multi-master mode. The slave selection by the master is made
by the seven-bit address of the target slave.

 The master (in transmit mode) sends a start bit followed by the
7-bit address of the slave it wishes to communicate with,
followed by a single bit representing whether it wishes to write
(0) to or read (1) to/from the slave. The target slave will
acknowledge its address.
5.8 UNIVERSAL SERIAL BUS (USB) PROTOCOL

 USB is a wired high speed serial bus for data communication. The
USB communication system follows star topology with a USB
host at centre and one or more peripherals connected to it.
 A USB host can support up to 127 slave peripheral devices and
other USB hosts.
 USB transmits data in packet format. The USB communication is a
host initiated one.
 The USB host controller is responsible for controlling the data
communication, establishing connectivity, packetizing and
formatting the data.
 The USB standard uses two different types of connector at the ends
of the USB cable. Type A connector is used for upstream
connection (connection with host, ex: PC, laptop) and Type B
connector is used for downstream connection (connection with
slave device).
• USB interface has the ability to carry power to the connecting devices
(GND and VBUS pins).

• Each USB device contains a product ID (PID) which is embedded in to the USB chip
by the manufacturer and vendor ID (VID) is supplied by the USB standards forum.
These are essential for loading drivers to a USB device for communication.

• USB supports four different types of data transfers i.e. Control, Bulk, Isochronous
and Interrupt
 Control transfer is used by USB system software to query,
configure and issue commands to the USB device.

 Bulk transfer is used for sending a block of data to the device. It

supports error checking and correction. (Ex: transfer data to
printer)

 Isochronous transfer, data is transmitted in streams in real-

time. It does not support error checking and re-transmission of
data. (Ex: Audio devices)

 Interrupt transfer is used for transferring small amounts of

data. This mechanism uses polling technique to see whether USB
device has any data to send. (Ex: Data from mouse or keyboard)
 5.9 MSP430 communications interfaces

The MSP430 microcontroller family is equipped with three

different types of serial communication modules:

•USART,

•USCI;

•USI.

The comparison between the three MSP430 communication

modules is shown in Table .
 USART USCI USI
UART: UART:
- Only one modulator - Two modulators support
n/16 timings
- n/a - Auto baud rate detection
- n/a - IrDA encoder & decoder
- n/a - Simultaneous USCI_A
and USCI_B (2 channels)
SPI: SPI: SPI:
- Only one SPI available - Two SPI (one on each - Only one SPI available
USCI_A and USCI_B)
- Master and Slave Modes - Master and Slave Modes - Master and Slave Modes
- 3 and 4 Wire Modes - 3 and 4 Wire Modes
I2C: (on ‘15x/’16x only) I2C: I2C:
- Simplified interrupt - SW state machine
usage needed
- Master and Slave Modes - Master and Slave Modes - Master and Slave Modes
- up to 400kbps - up to 400kbps
 5.9.1 USART MODULE

The USART (Universal Synchronous/Asynchronous Receiver/Transmitter)

module is a base unit for serial communications, supporting both
asynchronous communications (RS232) and synchronous communications
(SPI).

The USART module is available on the 4xx series devices:

• MSP430x42x and MSP430x43x: One module;
• MSP430x44x and MSP430FG461x: Two modules.
The USART supports:

•Low power operating modes (with auto-start);

•UART or SPI mode (I2C on ‘F15x/’F16x only);
•Double buffered TX/RX;
•Baud rate generator;
•DMA enabled;
•Error detection.
 5.9.1.1USART operation: UART mode
Transmits and receives characters asynchronously;

Timing for each character is based on the selected baud rate;

Transmit and receive use the same clock frequency leading to the same baud
rate;

Recommended initialization/re-configuration process:

Set SWRST (BIS.B #SWRST,&UxCTL);
Initialize all USART registers with SWRST = 1 (including UxCTL);
Enable USART module via the MEx SFRs (URXEx and/or UTXEx);
Clear SWRST via software (BIC.B #SWRST,&UxCTL);
Enable interrupts (optional) via the IEx SFRs (URXIEx and/or UTXIEx);
 Character format.

Character format can be specified as follows:

 Start bit;
 Seven or eight data bits;
 Even/odd/no parity bit;
 Address bit (address-bit mode);
 One or two stop bits.
Asynchronous communication formats:

•Idle-line multiprocessor communication protocol (minimum of two devices):

•IDLE is detected after > 10 periods of continuous marks after the stop bit;
•The first character after IDLE is an address;
•Can be programmed to receive only address characters.
•Address-bit multiprocessor communication protocol (minimum of three
devices):
•An extra bit in the received character marks the character as an address;
•UART can be programmed to receive only address characters.
Automatic error detection:

•Glitch suppression (prevents the USART from being accidentally

started;Any pulse on UCxRXD shorter than the deglitch time (approximately
30 ns) will be ignored).; Receive overrun error OE:;Break condition BRK:
•Framing error FE (Set if the stop bit is missing from a received frame)
•Parity error PE(Set if there is parity mismatch in a received frame)
•Receive overrun error OE (Set if UxRXBUF is overwritten)
•Break condition BRK(Set if all bits in the received frame = 0)
.
Enable the USART receive enable bit URXEx:
Enable the USART transmit enable bit UTXEx:
USART baud rate generation:
USART interrupts:
Receive-start edge detect feature (URXSE bit).
BRCLK is sourced by the DCO;
DCO is off due to low-power mode operation
 5.9.1.2USART operation: SPI mode

•Serial data transmitted and received by multiple devices using a shared clock
provided by the master;
•Three or four signals are used for SPI data exchange:
SIMO: Slave In, Master Out;
SOMI Slave Out, Master In;
UCLK USART SPI clock;
STE slave transmit enable (controlled by the master).
USART operation in SPI mode.
USART initialization/re-configuration process:
•Set SWRST (BIS.B #SWRST,&UxCTL);
•Initialize all USART registers with SWRST = 1 (including UxCTL);
•Enable USART module via the MEx SFRs (URXEx and/or UTXEx);
•Clear SWRST via software (BIC.B #SWRST,&UxCTL);
•Enable interrupts (optional) via the IEx SFRs (URXIEx and/or
UTXIEx);

Define mode: Master or Slave;

Enable SPI transmit/receive, USPIEx
Define serial clock control:UCLK is provided by the master on the
SPI bus.MM = 1:
BITCLK is provided by the USART baud rate generator on the
UCLK;MM = 0: USART clock is provided on the UCLK pin by the
master (baud rate generator disable);
The SPI receiver and transmitter operate in parallel and use the same
clock source for data transfer.
USART interrupts:

One interrupt vector for transmission and one interrupt vector for

reception:

UART transmit interrupt operation:UTXIFGx interrupt flag is set

by the transmitter to indicate that UxTXBUF is ready to accept

another character;

An interrupt request is generated if UTXIEx and GIE are also set;

UTXIFGx is automatically reset if the interrupt request is serviced

or if a character is written to UxTXBUF.

USART registers (UART and SPI modes)
In this section, the register bit definitions are provided for both USART
peripheral interfaces:
Asynchronous UART mode;
Synchronous SPI mode.
The registers common to both modes and only differentiated by the
register number (“UART” for UART mode and “SPI” for SPI mode);
UxCTL, USART Control Register
The registers used exclusively for one mode.
 USCI MODULE

Although supporting UART, SPI and I 2C, the USCI (Universal Serial Communication
Interface) module is a communications interface specially designed to interconnect
with high-speed industrial protocols
LIN (Local interconnect Network), used in cars (door modules, alarm, sunroof, etc.);
IrDA (Infrared Data Association), used for remote controllers.
The USCI module is available in the following devices:
MSP430F5xx;
MSP430F4xx and MSP430FG461x;
MSP430F2xx.
The USCI module Features :
Low power operating modes (with auto-start);
Two individual blocks:
USCI_A:
UART with Lin/IrDA support;
 UART and SPI (Master/Slave, 3 and 4 wire modes).

USCI_B:
 SPI (Master/Slave, 3 and 4 wire mode);

 I2C (Master/Slave, up to 400 kHz).

 USCI block diagram:
Double buffered TX/RX
Baud rate/Bit clock generator with:
 Auto-baud rate detect;

Flexible clock source.

 RX glitch suppression;

 DMA enabled;
 USCI OPERATION: UART MODE
 In asynchronous mode, the USCI_Ax modules connect the
MSP430 to an external system via two external pins the
MSP430 to an external system via two external pins ,
UCAxRXD and UCAxTXD;
 UART mode is selected when the UCSYNC bit is cleared;
 USCI transmits and receives characters asynchronously;
 Timing for each character is based on the selected baud rate
of the USCI;
 Transmit and receive use the same clock frequency leading
to the same baud rate;
 USCI OPERATION: UART MODE
USCI OPERATION IN UART MODE BLOCK DIAGRAM
 USCI OPERATION: UART MODE

Recommended initialization/re-configuration process:

 Set UCSWRST (BIS.B #UCSWRST,&UCAxCTL1);
 Initialize all USCI registers with UCSWRST = 1 (including
UCAxCTL1);
 Configure ports;
 Clear UCSWRST via software: (BIC.B #UCSWRST,&UCAxCTL1);
 Enable interrupts (optional) via UCAxRXIE and/or UCAxTXIE.
 USCI OPERATION: UART MODE
Character format specified as follows:
 Start bit;
 Seven or eight data bits;
 Even/odd/no parity bit;
 Address bit (address-bit mode);
 One or two stop bits.

The UCMSB bit controls the direction of the transfer and selects LSB (usual
in UART communication) or MSB first
Asynchronous communication formats:
 Idle-line multiprocessor communication protocol ( ) minimum
of two devices ):
 IDLE is detected after > 10 periods of continuous marks after
the stop bit;
 The first character after IDLE is an address

 Can be programmed to receive only address characters.

 Address-bit multiprocessor communication protocol

(minimum of three devices ):

 An extra bit in the received character marks an address
character;
 UART can be programmed to receive only address characters.

 Automatic baud rate detection (UCMODEx = 11)

Automatic error detection:
 Glitch suppression prevents the USIC from being
accidentally started ;
 Any pulse on UCAxRXD shorter than the deglitch time
(approximately 150 ns) will be ignored.
 Framing error UCFE: set if the stop bit is missing from a
received frame.
 Parity error UCPE: Set if there is a parity mismatch in a
received frame;
 Receive overrun error UCOE: Set if UCAxRXBUF is
overwritten;
 Break condition UCBRK:
o Set if all bits in the received frame =0;

o Set the UCAxRXIFG if UCBRKIE bit is set

Enable the USCI receive enable bit URXEx.

USCI transmit enable.

USCI baud rate generation.

 Standard baud rates from non -standard source
frequencies;
 Two modes of operation (UCOS16 bit):

 Low-frequency baud rate;

 Oversampling baud rate

USCI interrupts:
 One interrupt vector for transmission and one interrupt
vector for reception:
 USCI OPERATION: SPI MODE
 Flexible interface:

 3 - or 4 -pin SPI; pin SPI;

 7- or 8-bit data length;

 Master or slave;

 LSB or MSB first.

 S/W configurable clock phase and polarity;

 Programmable SPI master clock;

 Double buffered TX/RX;

 Interrupt driven TX/RX (USCI_A and USCI_B share TX

and RX vector);
 Direct Memory Address ( DMA) enabled;

 LPMx operation
USCI MODULE: SPI MODE BLOCK DIAGRAM
USCI MODULE: SPI CONNECTIONS
 Serial data transmitted and received by multiple devices using a
shared clock provided by the master;
Three or four signals are used for SPI data exchange:
 UCxSIMO: Slave in, master out;
 UCxSOMI: Slave out, ; master in;
 UCxCLK: USCI SPI clock;
 UCxSTE: Slave transmit enable:
o Enables a device to receive and transmit data and is
controlled by the master;
o 4 wire master, senses conflicts with other master(s);
o In 4 wire slave, externally controls TX and RX.

USCI interrupts:
o One interrupt vector for transmission and one interrupt vector for
reception:
 USCI OPERATION: I2C MODE

 The I2C mode supports any master or slave I2C- compatible

device.;
 Each I2C device is recognized by a unique address and can
operate as either a transmitter or a receiver,as well as either
the master or the slave;
 A master initiates a data transfer and generates the clock
signal SCL;
 Any device addressed by a master is considered a slave;

 Communication using the bi-directional serial data (SDA)

and serial clock (SCL) pins;
I2C MODE BLOCK DIAGRAM
 I2C serial data:
 One clock pulse is generated by the master for each data bit
transferred;
 Operates with byte data (MSB transferred first);

 The first byte after a START condition consists of a 7-bit slave

address and the R/W bit:
o R/W = 0: Master transmits data to a slave;

o R/W = 1: Master receives data from a slave.

 I2 C module operating modes:

o Master transmitter;
o Master receiver;
o Slave transmitter;
o Slave receiver.
I2C interrupts:
One interrupt vector for transmission and one interrupt
vector for reception;
USI MODULE

 The USI(Universal Serial Interface) module

supports SPI and I2C synchronous serial
communications.
 It is available in MSP4x20xx family devices.
 USI module supports:
SPI and I2C modes
Interrupt driven
Reduces CPU load
Flexible clock source selection
USI BLOCK DIAGRAM
SPI mode:
oProgrammable data length
(8/16-bit shift register);
oMSB/LSB first.

I2C mode:
oSTART/STOP detection;
o Arbitration lost detection.

 Interrupt driven;

 Reduces CPU load;

 Flexible clock source.

USI OPERATION: SPI AND I2C MODES
 Shift register and bit counter that include logic to
support SPI and I 2 C communication;
 USISR shift register (up to 16 bits supported):
o Directly accessible by software;
o Contains the data to be transmitted/received
(simultaneously);
o MSB or LSB first.
 Bit counter:
o Controls the number of bits transmitted/received;
o Counts the number of sampled bits;
 USI initialization:

o Reset USISWRST;
o Set USIPEx bits (USI function for the pin and maintains the
PxIN and PxIFG functions for the pin):
o Port input levels can be read via the PxIN register by
software;
o Incoming data stream can generate port interrupts on data
transitions.