Architecture Diagram of 8086

1
AD15 – AD0:
Pin Connections
Address/Data bus lines. These are multiplexed
lines.
Line carries address when ALE =1
Line carries data when ALE =0

AD19/S6 – A13/S3:
Address/Status bus bits are multiplexed to provide address
signals A19-A16 and status bits S6-S3.
S6 – always remains 0
S5 – indicates the condition of the interrupt flag
S4 and S3 – Indicate the segment being accessed during current
bus cycle.
4
RD:
When this read signal pin is at logic 0, the data bus is receptive
to data from memory or I/O devices.
READY:
This pin is used to enforce a waiting state.
READY pin at 0 – the microprocessor goes into idle state.
READY pin at 1 – the microprocessor does normal operation.
5
INTR:
Interrupt request pin is used to
request a hardware interrupt. If INTR is
held at high when IF =1, the processor
goes into the interrupt
acknowledgement cycle. INTA
becomes active when interrupt is being
serviced.
TEST:
Test pin is an input that is tested by the WAIT instruction. If the
test pin is at logic 0 the WAIT instruction functions as NOP. If
test is a logic 1, the WAIT instruction wait for TEST to become
logic 0. Commonly used with 8087 numeric coprocessor
connections.
6
NMI:
Non-maskable interrupt input is
similar to INTR expect that the NMI
interrupt does not check IF or
priority. Use Interrupt Vector 2.

RESET:
If this reset pin is held high for 4 clock cycles the
microprocessor resets. When 8086 or 8088 is reset it begins
execution at memory location FFFF0H and clears the IF.
CLK:
7
The clock pin is used to connect a clock generator
Vcc:
The power supply. +5V should be
connected to this pin.
GND:
The ground connection for the microprocessor.

MN/MX:
The minimum/maximum mode pin selects the mode for the
processor. To select minimum mode processor should be
connected directly to +5.0V and to select maximum mode
processor should be connected directly to GND.
8
BHE/S7:
The bus high enable pin is used in the 8086 to enable the Most
significant data bus bits during a read or write operation.

9
Pin Connections ( Minimum)

IO/M
This pin indicates whether the address bus contains a memory
address or an I/O port address.
WR:
The write line is a used when the microprocessor is writing data
to memory and the memory bus contains a valid address.
10
INTA:
Interrupt acknowledgement signals is a response to INTR
input pin. This is used when the interrupt vector is placed on the
address bus by the microprocessor.

ALE:
Address Latch enable shows whether the multiplexed AD lines
carry address or data.

DT/R:
Data transmit/receive shows that the microprocessor data bus is
transmitting(1) or receiving(0) data. This is used to control
buffers.
11
DEN:
Data Enable bus activates external data bus buffers.

HOLD:
HOLD pin is used to input request DMA. Hold set to 1
microprocessor gives up control of buses to DMA controller.

12
13
14
15
 Execution Unit

 Main components are

 Instruction Decoder
 Control System
 Arithmetic Logic Unit
 General Purpose Registers
 Flag Register
 Pointer & Index registers

16
 Instruction Decoder
 Translates instructions fetched from memory
into a series of actions which EU carries out

Control System
 Generates timing and control signals to
perform the internal operations of the
microprocessor

Arithmetic Logic Unit

 EU has a 16-bit ALU which can ADD,
SUBTRACT, AND, OR, increment, decrement,
complement or shift binary numbers
17
 General Purpose Registers

EU has 8 general AH AL
purpose registers

Can be individually BH BL
used for storing 8-bit CH CL
data
DH DL

AL register is also
called Accumulator AH AL AX

Two registers can also
be combined to form BH BL BX
16-bit registers
CH CL CX

The valid register pairs
are – AX, BX, CX, DX DH DL DX
18
 Flag Register

8086 has a 16-bit flag register

Contains 9 active flags

There are two types of flags in 8086
 Conditional flags – six flags, set or reset
by EU on the basis of results of some
arithmetic operations
 Control flags – three flags, used to control
certain operations of the processor

19
 Flag Register
U U U U OF DF IF TF SF ZF U AF U PF U CF

1. CF CARRY FLAG
Conditional Flags
2. PF PARITY FLAG
3. AF AUXILIARY CARRY
(Compatible with 8085,
except OF)
4. ZF ZERO FLAG
5. SF SIGN FLAG
6. OF OVERFLOW FLAG

7. TF TRAP FLAG
Control Flags
8. IF INTERRUPT FLAG
 Zero Flag
Carry Flag
This flag is set, if the result of
This flag is set, when there is a
the computation or comparison
carry out of MSB in case of
performed by an instruction is
addition or a borrow in case of
zero
subtraction.
Sign Flag

Parity Flag This flag is set, when the result of

any computation is negative
This flag is set to 1, if the lower
byte of the result contains even Over flow Flag
number of 1’s ; for odd number This flag is set, if an overflow
of 1’s set to zero. occurs, i.e, if the result of a signed
operation is large enough to
accommodate in a destination
Auxiliary Carry Flag register. The result is of more than
7-bits in size in case of 8-bit signed
This is set, if there is a carry from the operation and more than 15-bits in
lowest nibble, i.e, bit three during size in case of 16-bit sign
addition, or borrow for the lowest nibble,
operations, then the overflow will be
i.e, bit three, during subtraction.
set.
 Registers, Flag

8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

into 4 groups
OF DF IF TF SF ZF AF PF CF

Sl.No. Type Register width Name of register

1 General purpose 16 bit AX, BX, CX, DX
register
8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

22
 Registers and Special Functions

Register Name of the Register Special Function

16-bit Accumulator Stores the 16-bit results of arithmetic and logic

AX operations

8-bit Accumulator Stores the 8-bit results of arithmetic and logic

AL operations

Base register Used to hold base value in base addressing mode

BX to access memory data

Count Register Used to hold the count value in SHIFT, ROTATE

CX and LOOP instructions

Data Register Used to hold data for multiplication and division

DX operations

Stack Pointer Used to hold the offset address of top stack

SP memory

Base Pointer Used to hold the base value in base addressing

BP using SS register to access data from stack
memory
Source Index Used to hold index value of source operand (data)
SI for string instructions

Data Index Used to hold the index value 23

of destination
DI operand (data) for string operations
 Bus Interface Unit

 Main Components are

 Instruction Queue
 Segment Registers
 Instruction Pointer

24
 Instruction Queue
 8086 employs parallel processing
 When EU is busy decoding or executing
current instruction, the buses of 8086 may
not be in use.
 At that time, BIU can use buses to fetch upto
six instruction bytes for the following
instructions
 BIU stores these pre-fetched bytes in a FIFO
register called Instruction Queue
 When EU is ready for its next instruction, it
simply reads the instruction from the queue
in BIU
25
 Pipelining

 EU of 8086 does not have to wait in

between for BIU to fetch next
instruction byte from memory
 So the presence of a queue in 8086
speeds up the processing
 Fetching the next instruction while the
current instruction executes is called
pipelining

26
 Memory Segmentation
 8086 has a 20-bit address bus
 So it can address a maximum of 1MB of
memory
 8086 can work with only four 64KB segments
at a time within this 1MB range
 These four memory segments are called
 Code segment
 Stack segment
 Data segment
 Extra segment

27
 Memory
64KB Memory 1 00000H
Segment 2

3
4
4
5
Only 4 such segments can be 5
6
addressed at a time 6
7
7 1MB
8 Address
9
Range
10

11

12

13

14

15
FFFFFH
16
28
 Code Segment
 That part of memory from where BIU is
currently fetching instruction code bytes

Stack Segment
 A section of memory set aside to store
addresses and data while a subprogram
executes

Data & Extra Segments

 Used for storing data values to be used in the
program

29
 Memory
Code Segment 1 00000H
2

4
Data & Extra
5
Segments
6

7 1MB
8 Address
9
Range
10

11

12

13

14

Stack Segment 15 FFFFFH

16
30
 Segment Registers

 hold the upper 16-bits of the starting

address for each of the segments
 The four segment registers are
 CS (Code Segment register)
 DS (Data Segment register)
 SS (Stack Segment register)
 ES (Extra Segment register)

31
 Memory
1 00000H
CS 1000 0H Code Segment
3

4
DS 4000 0H Data Segment
ES 5000 0H Extra Segment
7

Starting Addresses 8 1MB

9 Address
Range
of Segments
10

11

12

13

14

15
SS F000 0H
Stack Segment 32
FFFFFH
 Address of a segment is of 20-bits
 A segment register stores only upper 16-
bits
 BIU always inserts zeros for the lowest 4-
bits of the 20-bit starting address.
 E.g. if CS = 348AH, then the code
segment will start at 348A0H
 A 64-KB segment can be located
anywhere in the memory, but will start at
an address with zeros in the lowest 4-bits

33
Instruction Pointer (IP) Register

 a 16-bit register
 Holds 16-bit offset, of the next instruction
byte in the code segment
 BIU uses IP and CS registers to generate
the 20-bit address of the instruction to be
fetched from memory

34
 Physical Address Calculation Memory
Start of Code Segment
1 00000H
348A0H
Data
Segment
IP = 4214H
3

Code Byte 38AB4H MOV AL, BL 4

Code
Segment
Extra
Segment
1MB
7
Address
8
Range
CS 348A0 H 9

10
IP + 4214 H 11
Physical Address 38AB4 H 12

13

14

15
35 FFFFFH
Stack
 Stack Segment (SS) Register
Stack Pointer (SP) Register

 Upper 16-bits of the starting address of

stack segment is stored in SS register
 It is located in BIU
 SP register holds a 16-bit offset from the
start of stack segment to the top of the
stack
 It is located in EU

36
Other Pointer & Index Registers

 Base Pointer (BP) register

 Source Index (SI) register
 Destination Index (DI) register
 Can be used for temporary storage of data
 Main use is to hold a 16-bit offset of a data
word in one of the segments

37
ADDRESSING
MODES OF
8086
38
 Various Addressing Modes
1. Immediate Addressing Mode
2. Register Addressing Mode
3. Direct Addressing Mode
4. Register Indirect Addressing Mode
5. Index Addressing Mode
6. Based Addressing Mode
7. Based & Indexed Addressing Mode
8. Based & Indexed with displacement Addressing Mode
9. Strings Addressing Mode

39
 1. IMMEDIATE ADDRESSING MODE

• The instruction will specify the name of the

register which holds the data to be
operated by the instruction.

• Source data is within the instruction

• Ex: MOV AX,10AB H

 AL=ABH, AH=10H
 2.REGISTER ADDRESSING MODE

• In immediate addressing mode, an

8-bit or 16-bit data is specified as
part of the instruction

• Ex: MOV AX,BL H

MOV AX,BXH

41
 3. DIRECT ADDRESSING MODE

• Memory address is supplied with in

the instruction
• Mnemonic: MOV AH,[MEMBDS]
AH [1000H]
• But the memory address is not
index or pointer register

42
 4. REGISTER INDIRECT ADDRESSING MODE

• Memory address is supplied in an index or

pointer register
• EX:

MOV AX,[SI] ; AL [SI] ; AH [SI+1]

JMP [DI] ; IP [DI+1: DI]
INC BYTE PTR [BP] ; [BP] [BP]+1
DEC WORD PTR [BX] ;
[BX+1:BX] [BX+1:BX]-1

43
 5.Indexed Addressing Mode

• Memory address is the sum of index

register plus displacement
MOV AX,[SI+2] AL [SI+2]; AH [SI+3]
JMP [DI+2] IP [BX+3:BX+2]

44
 6. Based Addressing Mode

• Memory address is the sum of the BX or BP

base register plus a displacement within
instruction
• Ex:
MOV AX,[BP+2] AL [BP+2]; AH [BP+3]
JMP [BX+2] IP [BX+3:BX+2]

45
 7.BASED & INDEX ADDRESSING MODES

• Memory address is the sum of the index register

& base register
Ex:
MOV AX,[BX+SI] ; AL [BX+SI] ; AH [BX+SI+1]
JMP [BX+DI] ; IP [BX+DI+1 : BX+DI]
INC BYTE PTR [BP+SI] ; [BP] [BP]+1
DEC WORD PTR [BP+DI] ;
[BX+1:BX] [BX+1:BX]-1

46
 8. BASED & INDEXED WITH DISPLACEMENT ADDRESSING MODE

• Memory address is the sum of an index register ,

base register and displacement within instruction

MOV AX,[BX+SI+6] ; AL [BX+SI+6] ; AH [BX+SI+7]

JMP [BX+DI+6] ; IP [BX+DI+7 : BX+DI+6]
INC BYTE PTR [BP+SI+5] ;
DEC WORD PTR [BP+DI+5] ;
 9. Strings Addressing Mode

• The memory source address is a register SI in

the data segment, and the memory destination
address is register DI in the extra segment

• Ex: MOVSB [ES:DI] [DS:SI]

• If DF=0 SI SI+1 , DI DI+1

DF=1 SI SI-1 , DI DI-1