Digital System Design Using Verilog

(21EC32)
 Lesson Plan
SN DATE TOPIC DATE ENGAGED REMARKS
PLANNED
2.1 General Approach to Combinational Logic
design
2.2 Decoders
2.3 BCD Decoders
2.4 Encoders
2.5 Digital Multiplexers
2.6 Using Multiplexers as Boolean function Generators
2.7 Adders and Subtractors
2.8 Cascading Full Adders
2.9 Binary Comparators
2.10 Programmable Logic Devices

2
Combinational Circuits
• Combinational circuit is a feed forward circuit that consists of combination of gates.

To Design a combinational circuit the following steps are followed

1. State the given problem completely and exactly
2. Interpret the problem, and determine the available input variables and required output variables.
3. Assign a letter symbol to each input and output variables.
4. Design the truth table, which defines the required relations between inputs and outputs.
5. Obtain the simplified Boolean expression for each output using k-maps.
6. Draw the logic circuit diagram to implement the Boolean expression.

3
Combinational Circuits
• Design a combinational circuit which has 3-bit input number and a single output (F). The
output signal F is specified as follows:
• F = 1 when the input number is less than (3)
• F = 0 otherwise.
• Implement F using only NAND gates

4
Combinational Circuits
• Let the three inputs be called X, Y, and Z.
• X is the most significant variable and Z is the least significant variable. The output F goes high, that is,
the output produces logic 1 value if the input is less than 011, equivalent to a decimal value of three.
This means that the output will be logic one for input combinations 000, 001, and 010.
• For other input combinations, which are 011 upto 111, the output is logic zero.

5
Binary Adder
• Basic building blocks of all arithmetic circuits are ADDERS.
• It adds two binary numbers and gives out sum and carry-out as outputs.
• Divided into two categories 1.Half adder 2.Full-adder

6
Half Adder
• Adding two single-bit binary values, X, Y produces a sum S bit and a carry out C-
out bit.
• This operation is called half addition and the circuit to realize it is called a half
adder.

Half Adder Truth Table S(X,Y) = S (1,2)

Inputs Outputs S = X’Y + XY’
S = XÅY
X Y S C-out
0 0 0 0
0 1 C-out(x, y, C-in) = S (3)
1 0
1 0 1 0 C-out = XY
1 1 0 1
X
Sum S
Y
X Half S
Y Adder C-OUT C-out

7
Full Adder
• Adding two single-bit binary values, X, Y Sum S X
with a carry input bit C-in produces a sum XY
bit S and a carry out C-out bit. C-in 00 01 11 10
0 2 6 4
Full Adder Truth Table 0 1 1
1 3 7 5
Inputs Outputs 1 1 1 C-in

X Y C-in S C-out Y
0 0 0 0 0 S = X’Y’(C-in) + XY’(C-in)’ + XY’(C-in)’ + XY(C-in)
S = X Å Y Å (C-in)
0 0 1 1 0
0 1 0 1 0 Carry C-out X

0 1 1 0 1 XY
C-in 00 01 11 10
1 0 0 1 0 0 2 6 4
1 0 1 0 1 0 1
1 1 0 0 1 1
1 3
1
7
1
5
1 C-in
1 1 1 1 1
Y
S(X,Y, C-in) = S (1,2,4,7)
C-out = XY + X(C-in) + Y(C-in)
C-out(x, y, C-in) = S (3,5,6,7)
8
Full Adder Circuit Using AND-OR
X’ X’Y’C-in
X Y’
X X’ C-in

X’
Y
X’YC-in’ Sum S
Y C-in’
Y Y’ X
Y

C-in C-in’ XY’C-in’

C-in C-in’ X
Y
C-in’ XYC-in

X Y X XY
Y
Full
C-out C-in X
XC-in
Adder C-out
C-in
Y
S
C-in YC-in

9
Full Adder Circuit Using XOR

Y Sum S
X Y C-in

Full X XY
C-out C-in
Adder Y

X
XC-in C-out
S C-in
Y

C-in YC-in

10
Binary parallel Adder

Inputs to be added
Adds two 4-bit numbers: X3X2X1X0 Y3Y2Y1Y0
X = X3 X2 X1 X0
Y = Y3 Y2 Y1 Y0
producing the sum S = S3 S2 S1 S0 , 4-bit
C4 C-out C-in C0 =0
C-out = C4 from the most significant parallel
position j=3 Adder

S3 S2 S1 S0

Sum Output

Data inputs to be added

X3 Y3 X2 Y2 X1 Y1 X0 Y0

Full C3 Full C2 Full C1 Full

C4 C-out C-in C-out C-in C-out C-in C-out C-in C0 =0
Adder Adder Adder Adder

S3 S2 S1 S0
Sum output

11
Look-Ahead Carry Binary Adders

• Main disadvantage of four bit adder is that higher order bit operation can be performed only if carry out from
lower order bit occurs.Hence it takes n-time’s propagation delay of full adder to complete n-bit addition.This
delay can be overcome by look-ahead carry adder.
• Carry look-ahead adders use a different method to create the needed carry bits for each full adder with a
lower constant delay equal to three gate delays.
• The carry out C-out from the full adder at position i or C j+1 is given by:
C-out = C i+1 = Xi . Yi + (Xi + Yi) . Ci
• By defining:
• Gi = Xi . Yi as the carry generate function for position i (one gate delay)
(If Gi =1 C i+1 will be generated regardless of the value Ci)
• Pi = Xi + Yi as the carry propagate function for position i (one gate delay)
(If Pi = 1 Ci will be propagated to C i+1)
• By using the carry generate function Gi and carry propagate function Pi , then C i+1 can be written as:
C-out = C i+1 = G i + Pi . C i
• To eliminate carry ripple the term Ci is recursively expanded and by multiplying out, we obtain a 2-level
AND-OR expression for each C i+1
12
Carry Look-Ahead Adders

• For a 4-bit carry look-ahead adder the expanded expressions for all
carry bits are given by:
C1 = G0 + P0.C0

C2 = G1 + P1.C1 = G1 + P1.G0 + P1.P0.C0

C3 = G2 + P2.G1 + P2.P1.G0 + P2.P1.P0.C0

C4 = G3 + P3.G2 + P3.P2.G1 + P3 . P2.P1.G0 + P3.P2.P1.P0.C0

where Gi = Xi . Yi Pi = Xi + Yi

• The additional circuits needed to realize the expressions are usually

referred to as the carry look-ahead logic.
• Using carry-ahead logic all carry bits are available after three gate
delays regardless of the size of the adder.

13
Carry Look-Ahead Circuit

Ci = Gi-1 + Pi-1. Gi-2 + …. + Pi-1.P i-2. …P1 . G0 + P i-1.P i-2. …P0 . C0

14
Binary Arithmetic Operation: Subtraction

• Two binary numbers are subtracted by subtracting each pair of bits together with borrowing, where
needed.
• Subtraction Example:

0 0 1 1 1 1 1 0 0 Borrow
X 229 1 1 1 0 0 1 0 1
Y - 46 - 0 0 1 0 1 1 1 0
183 1 0 1 1 0 1 1 1

15
Half Subtractor
• Subtracting a single-bit binary value Y from anther X (I.e. X -Y ) produces a
difference bit D and a borrow out bit B-out.
• This operation is called half subtraction and the circuit to realize it is called a half
subtractor.

D(X,Y) = S (1,2)
Half Subtractor Truth Table D = X’Y + XY’
Inputs Outputs
D = XÅY

X Y D B-out B-out(x, y, C-in) = S (1)

0 0 0 0
B-out = X’Y
0 1 1 1
1 0 1 0
1 1 0 0 X Difference
D
Y
X Half D
Y Subtractor B-OUT B-out

16
Full Subtractor
• Subtracting two single-bit binary values, Y, Difference D X
B-in from a single-bit value X produces a XY
difference bit D and a borrow out B-out B-in 00 01 11 10
bit. This is called full subtraction. 0 2 6 4
0 1 1
Full Subtractor Truth Table 1 3 7 5
Inputs Outputs 1 1 1 B-in

X Y B-in D B-out Y
0 0 0 0 0 S = X’Y’(B-in) + XY’(B-in)’ + XY’(B-in)’ + XY(B-in)
0 0 1 1 1 S = X Å Y Å (C-in)
0 1 0 1 1 Borrow B-out X
0 1 1 0 1 XY
1 0 0 1 0 B-in 00 01 11 10
0 2 6 4
1 0 1 0 0 0 1
1 1 0 0 0 1 3 7 5
1 1 1 1 B-in
1 1 1 1 1
Y
S(X,Y, C-in) = S (1,2,4,7)
B-out = X’Y + X’(B-in) + Y(B-in)
C-out(x, y, C-in) = S (1,2,3,7)
17
Full Subtractor Circuit Using AND-OR
X’ X’Y’B-in
X Y’
X X’ B-in

X’
Y
X’YB-in’ Difference D
Y B-in’
Y Y’ X
Y

B-in B-in’ XY’B-in’

B-in B-in’ X
Y
B-in’ XYB-in

X Y X’ X’Y
Y
Full
B-out B-in X’
X’B-in
Subtractor B-out
B-in
Y
D
B-in YB-in

18
Full Subtractor Circuit Using XOR

X Y Y Difference D
B-in

Full
B-out B-in
Subtractor X’
X’Y

Y
D
X’
X’B-in
B-out
B-in

B-in YB-in

19
n-bit Subtractors
An n-bit subtracor used to subtract an n-bit number Y from another
n-bit number X (i.e X-Y) can be built in one of two ways:

• By using n full subtractors and connecting them in series, creating a borrow ripple
subtractor:
• Each borrow out B-out from a full subtractor at position j is connected to the
borrow in B-in of the full subtracor at the higher position j+1.

• By using an n-bit adder and n inverters:

• Find two’s complement of Y by:
• Inverting all the bits of Y using the n inverters.
• Adding 1 by setting the carry in of the least significant position to 1
• The original subtraction (X - Y) now becomes an addition of X to two’s
complement of Y using the n-bit adder.

20
4-bit Borrow Subtractor
Inputs
X3X2X1X0 Y3Y2Y1Y0

Subtracts two 4-bit numbers:

Y = Y3 Y2 Y1 Y0 from 4-bit
X = X3 X2 X1 X0 B4 B-out B-in B0 =0
Subtractor
Y = Y3 Y2 Y1 Y0
producing the difference D = D3 D2 D1 D0 ,
B-out = B4 from the most significant
D3 D2 D1 D0
position j=3
Difference Output D

Data inputs to be subtracted

X3 Y3 X2 Y2 X1 Y1 X0 Y0

B3 B2 B1
B4 B-out Full B-in B-out Full B-in B-out Full B-in B-out Full B-in B0 =0
Subtractor Subtractor Subtractor Subtractor

D3 D2 D1 D0
Difference output D

21
4-bit Subtractor Using 4-bit Adder
Inputs to be subtracted
Y3 Y2 Y1 Y0

X3 X2 X1 X0

C4
4-bit
C-out C-in C0 = 1
Adder
S3 S2 S1 S0

D3 D2 D1 D0

Difference Output

22
Comparator-one bit

23
Decoders
• A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded
outputs, where the input and output codes are different. e.g. n-to-2 n, BCD decoders.

• Enable inputs must be on for the decoder to function, otherwise its outputs assume a single “disabled”
output code word.

Decoder
Input
Code word
Output
Map code word
Enable
inputs

24
Binary n-to-2n Decoders
• A binary decoder has n inputs and 2n outputs.
• Only the output corresponding to the input value is equal to 1.

n n to 2n 2n
inputs : decoder outputs
:

25
3:8 Decoder

E A B C O0 O1 O2 O3 O4 O5 O6 O7

0 X X X 0 0 0 0 0 0 0 0
O0 ABC
A S2 O1 ABC 1 0 0 0 1 0 0 0 0 0 0 0
O2 ABC 1 0 0 1 0 1 0 0 0 0 0 0
B S1 3:8 O3 ABC
1 0 1 0 0 0 1 0 0 0 0 0
dec O4 ABC
C S0
O5 ABC 1 0 1 1 0 0 0 1 0 0 0 0

O6 ABC 1 1 0 0 0 0 0 0 1 0 0 0
O7 ABC 1 1 0 1 0 0 0 0 0 1 0 0

1 1 1 0 0 0 0 0 0 0 1 0
1 1 1 1 0 0 0 0 0 0 0 1
Enb

27
3:8 Decoder

28
Encoders
• If the a decoder's output code has fewer bits than the input code, the device is usually called an encoder.
e.g. 2n-to-n, priority encoders.

• The simplest encoder is a 2n-to-n binary encoder, where it has only one of 2n inputs = 1 and the output
is the n-bit binary number corresponding to the active input.

• For an 8-to-3 binay encoder with inputs I0-I7 the logic expressions of the outputs Y0-Y2 are:

Y0 = I1 + I3 + I5 + I7
Y1= I2 + I3 + I6 + I7
Binary
Y2 = I4 + I5 + I6 +I7 2n .
encoder
. n
inputs .
.
.
.
outputs

30
8-to-3 Binary Encoder

Inputs Outputs

At any one time, only I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 y2 y1 y2

one input line has a value of 1. 1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
I0
I1 Y2 = I 4 + I 5 + I 6 + I 7
I2
I3 y1 = I2 + I3 + I6 + I7
I4
I5
I6
Y0 = I 1 + I 3 + I 5 + I 7
I7

31
Multiplexers
• A multiplexer (MUX) is a digital switches which connects data from one of n sources to
the output.
• A number of select inputs determine which data source is connected to the output.

D0 1Y
Multiplexer
Enable EN
s bits
2Y
Select SEL
D1
Data
b bits output
. .
D0
b bits Y . .
D1 . .
bY
n Data . Dn-1
Sources .
b bits
Dn-1
SEL EN

32
4-to-1 MUX Circuit
I0 I0

I1 I1
Y Y
I2 I2

I3 I3

0 1 2 3
2-to-4
Decoder

S1 S0 S1 S0

34
Demultiplexers
• Digital switches to connect data from one input source to one of n outputs.
• Usually implemented by using n-to-2n binary decoders where the decoder’s enable line is used for data
input of the demultiplexer.

2X4
Select Decoder
s bits Demux b bits lines One of
Select four 1-bit

One of n outputs
One of n b bits outputs
Data
Data
Sources
Input
selected
. Input Enable
. data (1bit)
b bits
1-bit 4-output demultiplexer using
a 2x4 binary decoder.

36
PLDs (Programmable Logic Devices)

38
General Structure of PLD
• Inputs to the PLD are applied to a set of
buffer/inverters. These devices have both the true
value of the input as well as the complemented value
of the input as its outputs.
• Outputs from these devices are the inputs to an array
of and-gates. The AND array generates a set of p
product terms.
• The product terms are inputs to an array of or-gates
to realize a set of m sum-of-product expressions.

39
General Structure of PLD

40
General Structure of PLD
• One or both of the gate arrays are programmable.
• The logic designer can specify the connections within an array.
• PLDs serve as general circuits for the realization of a set of Boolean
functions.

Device AND-array OR-array

PROM Fixed Programmable
PLA Programmable Programmable
PAL Programmable Fixed

41
Programming a PLD
• In a programmable array, the connections to each gate can be
modified.
• Simple approach is to have each of the gate inputs connected
to a fuse.

• Gate realizes the product term

• To generate the product term we remove the connections by
blowing the corresponding fuses.
• Thus, programming is a hardware procedure. Specialized
equipment called programmers is needed to carry out the
programming of a PLD. 42
Programming a PLD
• Erasable PLD—connections can be reset to their original
conditions and then reprogrammed.
• Can be achieved by exposing the PLD to ultraviolet light or
using electrical signals
• PLDs programmed by a user are called field
programmable.
• User can also specify the desired connections and supply
the information to the manufacturer. Manufacturer
prepares an overlay that is used to complete the
connections as the last step in the fabrication process.
• Such PLDs are called mask programmable.

43
PLD Notation
• Simplified notation. Each gate has only a single input
line.
• Inputs are indicated by lines at right angles to the
single gate lines.
• A cross at the intersection denotes a fusible link is
intact.

44
PLD Notation
• Lack of cross indicates the fuse is blown or no connection exists.

45
PLD Notation
• The occurrence of a hard-wired connection that is not fusible is
indicated by a junction dot.

• For the special case when all the input fuses to a gate are kept
intact, a cross is placed inside the gate symbol.

46
Programmable Read-Only Memory (PROM)
• AND-array with buffer/inverter is an -to--line decoder.
• OR-array is a collection of programmable or-gates.
• Decoder is a min-term generator.
• n-variable minterms appear on the lines at the decoder output.
These are also known as word lines.
• n input lines called address lines, m output lines called bit lines.
• PROM.
• Realization of Boolean expressions same as realization using decoder
discussed previously.
47
PROM Structure

Logic Diagram 48
PROM Structure

PLD Notation

49
Example
Realizing

50
Why is it called PROM?
• 3-bit input combination to the lines is regarded as an
address of one of the word lines.
• As a consequence of selecting a given word line, a
pattern of 0’s and 1’s, a word, as determined by the
fusible connections to the selected word line appears
at the bit lines of the device.
• This 0-1 pattern is considered the word stored at the
address associated with the selected word line.
• E.g. the word stored at address is
• “Read only”: The fact that the connections associated
with the fusible links normally cannot be altered once
they are formed.
51
Programmable Logic Array
• PLAs are characterized by three numbers:
• Number of input lines n
• Number of product terms that can be generated p (the number of AND gates)
• Number of output lines m
• PLAs
• Typical PLA is

52
Programmable Logic Array

53
Programmable Logic Array
• In many logic design situations not all the minterms are needed for a
realization.
• For input variables, minterms.
• This is the number of gates in the AND-array of a PROM.
• PLA’s with 16 input lines
• minterms
• In a PLA only 48 product terms.
• inputs appear at each AND gate.
• For our examples, assume PLA.

54
PROM vs PLA
• PROM: realization of a set of Boolean functions is based on minterm
canonical expressions.
• No minimization necessary.
• PLA: the AND gates are capable of generating product terms that are
not necessarily minterms.
• Realization using PLA is based on sum-of-product expression that may not be
canonical.
• Logic designer is bounded by the number of product terms that are realizable
by the AND-array.
• Simplifications is necessary.

55
Logic Design
𝑓1
Example
𝑓
2 𝑓 1⋅ 𝑓 2

56
Logic Design Example
𝑓1 𝑓2 𝑓 1⋅ 𝑓 2

57
Logic Design
𝑓1
Example
𝑓
2

58
Additional Features
• For greater flexibility, PLAs make provision for either a true
output or a complemented output.

feeds into one input of an XOR

gate. The other input is
connected to a pull-up resistor.
When the fuse is left intact, the
input is 0. When the fuse is
blown, input is 1.

59
Example of Use of Complemented Functions

60
Example of Use of Complemented Functions

61
PLA Table
• A common way of specifying the connections in a PLA.
• 3 sections: input section, output section, T/C section.
• Each product term is assigned a row in the table.
• Input section indicates connections between inputs to AND-array.
• Output section indicates connections between outputs of AND-array
and inputs to the OR-array.
• T/C section indicates how the exclusive or gates are programmed.
• T—true output is used.
• C—output should be complemented.

62
 Programmable Array Logic (PAL) Devices
• OR-array is fixed by the manufacturer of the device.
• PAL device is easier to program and less expensive than the PLA.
• Less flexible.

63
Example of Logic Design with PAL
• Consider

• Minimal sums:

64
Example of Logic Design with PAL

65
University Questions

• Define priority encoder with three inputs with middle bit at highest priority encoding to 10 most
significant bit at next priority encoding to 11 and least significant at least priority encoding 01.
10M
• Define multiplexer and demultiplexer and draw block diagram. 04M
• Design 4:1 Multiplexer draw the circuit using gates. 06M
• Explain how will you implement the following function using implementation table,
F(A,B,C,D)=Σm(0,1,3,4,7,10,12,14) with A,B,C select lines. 10M
• Design Magnitude comparator .Design a two bit binary comparator and implement with suitable
logic gates. 08M
• Design a binary full adder using only two input NAND gates. Write its truth table. 06M
• Implement the following boolean function using 4:1 multiplexer
Y=f(A,B,C,D)=Σm(0,1,2,4,6,9,12,14) 06M

66
 Assignment Questions

• Design a combinational circuit so that output is generated when majority of four inputs is false.
• Draw Half adder using only Nand gates and only Nor gates.
• Design full subtractor by cascading Half-Subtractors.
• Implement the following function by means of the decoder and fundamental gates F=πM(0,1,4,5)
• Implement full adder circuit using decoder and OR gates.
• Construct 1:16 demultiplexer using 1:4 demultiplexer and 2:4 line decoder.
• Implement Σm(2,4,5,7,9,14) Using Mux.

67