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Unit-5 System Level Design Using Mentor Graphics EDA Tool (FPGA Advantage)

The document discusses system level design using Mentor Graphics EDA tools, specifically for FPGA development. It describes the EDA design flow, including design creation and reuse, FPGA/ASIC synthesis, simulation and verification. It highlights Mentor Graphics tools that support each step of the flow, such as HDL Designer for design entry, Precision Synthesis for synthesis, and Leonardo Spectrum as a synthesis tool. The document promotes Mentor Graphics as providing a complete FPGA design solution from RTL design through simulation.

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59 views12 pages

Unit-5 System Level Design Using Mentor Graphics EDA Tool (FPGA Advantage)

The document discusses system level design using Mentor Graphics EDA tools, specifically for FPGA development. It describes the EDA design flow, including design creation and reuse, FPGA/ASIC synthesis, simulation and verification. It highlights Mentor Graphics tools that support each step of the flow, such as HDL Designer for design entry, Precision Synthesis for synthesis, and Leonardo Spectrum as a synthesis tool. The document promotes Mentor Graphics as providing a complete FPGA design solution from RTL design through simulation.

Uploaded by

kumarkankipati19
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Unit-5

System level design using mentor


graphics EDA tool
(FPGA advantage)

G.Nagasudha
R.no:322206540008
EDA tools

• Electronic design automation (EDA), also referred to


as electronic computer-aided design (ECAD), is a category
of software tools for designing electronic systems such as
integrated circuits and printed circuit boards.
• The tools work together in a design flow that chip designers
use to design and analyze entire semiconductor chips.
• Since a modern semiconductor chip can have billions of
components, EDA tools are essential for their design; this
article in particular describes EDA specifically with respect to
integrated circuits (ICs).
FPGA/ASIC Design
• Design creation and reuse
• Fpga/Asic synthesis
• High level synthesis and Verification
• Simulation and verification
• Requirements tracking
Design creation and reuse
• Whether designing an FPGA or ASIC, the devices have advanced
capabilities and complex features that, when put under tight
development cycles, burden the design teams to produce efficient and
robust chips.
• Hence, the design teams have placed more demands on HDL processes,
automation, and style guidelines for developing quality design results.
• Standard languages (such as VHDL, Verilog, SystemVerilog) and IP
formats, along with common industry version management systems aid
in producing repeatable and dependable design processes, but the tools
that utilise these standards need to do much more than edit text files.
• Mentor Graphics delivers a complete design solution for FPGA and
ASIC HDL development beginning with comprehensive design
creation addressing new code creation, formal and informal design
reuse, and any combination in between.
• These HDL design capabilities greatly assist engineers, individuals
and teams, in creating, analysing, and managing their complex
designs, improving their productivity and accelerating design
creation.
• Executives, managers, and engineers all have a big stake in reuse,
but nearly everyone underestimates the challenges associated with
it.
HDL designer
• By using HDL Designer, savings and cost avoidance can be
recognised immediately through automation
• Designing and creating large designs from IP efficiently requires
more than just writing RTL.
• HDL Designer Series provides engineers with a suite of advanced
design editors to facilitate development: interface-based design
spreadsheets and state-machine editing.
• It also includes simulation animation within the graphical editors
to maximise the benefit of the integrated flow with ModelSim,
Precision Synthesis and Leonardo Spectrum.
FPGA/ASIC synthesis
• With increasing competitive pressures and shorter product life cycles, designers
have less time to develop high performance and complex ASIC designs.
• At the same time, the development cost of an ASIC is increasing rapidly, making
it less feasible to use ASIC devices for many cost-sensitive applications without
extensive testing and simulation.
• As FPGA devices have become larger and faster, verifying functionality of costly
ASIC designs in FPGAs has become an effective and economical method of
verification. However, some ASIC structures cannot be directly implemented in
an FPGA efficiently.
• Precision Synthesis helps ease the transition from ASIC to FPGA design by
allowing the same HDL code and constraint syntax to be used. To obtain optimal
performance, automatic conversions of ASIC design structures are utilised.
Precision series
• Precision Synthesis solutions provide high-quality Verilog / VHDL /
SystemVerilog synthesis for the latest FPGAs, easy-to-use debug and
validation environment, comprehensive & user-friendly high-
reliability synthesis, and tight integration with Siemens FPGA
design solutions
• Precision Synthesis is the industry’s most comprehensive FPGA
vendor-independent solution.
• It offers best-in-class results for performance and area. Precision
has tight integration across the Siemens FPGA flow from C++ /
SystemC / RTL design through simulation and formal verification to
board design.
Complete FPGA Design Flow
Leonardo Spectrum
• Features
• Mature synthesis tool for designing PLDs, FPGAs and ASICs, in
VHDL or Verilog
• Supports many current and legacy FPGA devices and ASIC
families
• Highly controllable advanced synthesis algorithms
• Language neutrality, and both platform and target device
independence
• Benefits
• One tool, one easy learning curve, one set of scripts -- for CPLDs,
FPGAs, or ASICs
• Provides high quality of results with the speed and features needed
for large designs
• True hierarchical support allows for easy grouping of design
elements, enabling a single design to be partitioned across multiple
devices
• LeonardoInsight schematic viewer accelerates synthesis analysis
Thank you

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