(Basic Architecture of the whole system)

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2
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The uppermost bus is the address bus. When the CPU reads data
or instructions from or writes data to memory, it must specify
the address of the memory location it wishes to access

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Data is transferred via the data bus. When CPU fetches data from
memory it first outputs the memory address on to its address bus.
Then memory outputs the data onto the data bus. Memory then
reads and stores the data at the proper locations.

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Control bus carries the control signal. Control signal is the
collection of individual control signals. These signals
indicate whether data is to be read into or written out
of the CPU.

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7
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 Register Symbol Number of bits Function
Data register DR 16 Holds memory operand

Address register AR 12 Holds address for the

memory
Accumulator AC 16 Processor register

Instruction register IR 16 Holds instruction code

Program counter PC 12 Holds address of the

instruction

Temporary register TR 16 Holds temporary data

Input register INPR 8 Carries input character

Output register OUTR 8 Carries output character

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 Instruction cycle

The instruction cycle is the procedure a microprocessor goes through to process an

instruction.

It has three phases:

•Fetch

•Decode

•Execute

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 Instruction cycle
• First the processor fetches or reads the instruction from
memory.

• Then it decodes the instruction determining which instruction

it has fetched.

•Finally, it performs the operations necessary to execute the instruction.

• It performs some operation internally, and supplies the address, data & control
signals needed by memory & I/O devices to execute the instruction.

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 Instruction cycle

the microprocessor asserts when it is ready to read data from memory or I/O device.

• When READ signal is asserted the memory subsystem places the instruction code be fetched
on to the computer system’s data bus. The microprocessor then inputs the data from the
bus and stores its internal register.

• READ signal causes the memory to read the data, the WRITE operation causes the memory
to store the data

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TIMING DIAGRAMS

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CPU Organization

Central processing unit (CPU) is the electronic circuitry

within
a computer that carries out the instructions of computer
program by performing a logical,
control the (I/O)
and input/output basic operations
arithmetic,
specified by the
instructions.

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CPU Organization

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 CPU Organization

•The register section, as its name implies, includes a set of

Rregisters and a bus or other communication mechanism.

•The register in a processor’s instruction set architecture are found in the section of the CPU.

•The system address and data buses interact with this section of CPU. The register section
also contains other registers that are not directly accessible by the programmer.

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 CPU Organization

•The fetch portion of the instruction cycle, the processor first

outputs the address of the instruction onto the address bus. The
processor has a register called the ͞program counter͟.

•At the end of the instruction fetch, the CPU reads

The instruction code from the system data bus.

•It stores this value in an internal register, usually called

The instruction register”.

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 CPU Organization
• The arithmetic / logic unit (or) ALU performs most arithmetic and logic operations
such as adding and ANDing values.

• CPU controls the computer, the control unit controls the CPU. The control unit
receives some data values from the register unit, which it used to generate the control
signals.

•The control unit also generates the signals for the system control bus such as READ,
WRITE, IO/ signals

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 CPU Organization

• Memory is the group of circuits used to store data.

• Memory components have some number of memory locations,

each word of which stores a binary value of some fixed length.

• The number of locations and the size of each location vary from
memory chip to memory chip, but they are fixed within
individual chip.

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 CPU Organization

•Memory is usually organized in the form of arrays, in which each cell is capable of
storing one bit information.

• Each row of cell constitutes a memory word, and all cells of a row are connected to
a common column called word line, which is driven by the address decoder on the
chip

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• Data transfer instructions
• Load the data from memory into the microprocessor: These instructions copy data
from memory into a microprocessor register.

• Store the data from the microprocessor into the memory: This is similar to the load
data expect data is copied in the opposite direction from a microprocessor register to
memory.

• Move data within the microprocessor: These operations

copies data from one microprocessor register to another.

• Input the data to the microprocessor: The microprocessor inputs the data from the
input devices ex: keyboard in to one of its registers.

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• Data operational instructions
• Data operational instructions do modify their data values. They
typically perform some operations using one or two data values
(operands) and store result.

• Arithmetic instructions make up a large part of data

operations instructions. Instructions that add, subtract,

multiply, or divide values fall into this category. An instruction

that increment or decrement also falls in to this category.

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• Logical instructions perform basic logical operations on data. They AND, OR, or XOR
two data values or complement a single value.

• Shift operations as their name implies shift the bits of a data

values also comes under this category

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• An isolated I/O input and output devices are treated as being separated from
memory. Different instructions are used for memory and I/O.
• Memory mapped I/O treats input and output devices as memory locations the CPU
access these I/O devices using the same instructions that it uses to access memory. For
relatively simple CPU memory mapped I/O is used.
• There are three registers in ISA of this processor.
– Accumulator (AC)
– Register R
– Zero flag (Z)

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25
Register Transfer
Level Design
CPU State
Diagram
Instruction Cycle

• Fetch
• Decode
• Execute
Very Simple CPU
• 64 x 8 memory
• Address pins A[5..0]
• Data Pins D[7..0]
• 8-bit Accumulator
Non-ISA Registers

• 6-bit Address Register AR

• 6-bit Program Counter PC
• 8-bit Data Register DR
• 2-bit Instruction Register IR
Fetching Instructions from
Memory
• CPU outputs address on A[5..0]
• Delay for memory to perform its internal
operations
• Read data from memory on D[7..0]
Fetch States

FETCH1: AR  PC
 Fetch States

FETCH1: AR  PC
FETCH2: DR  M
 Fetch States

FETCH1: AR  PC
FETCH2: DR  M, PC  PC + 1
 Fetch States

FETCH1: AR  PC
FETCH2: DR  M, PC  PC + 1
FETCH3: IR  DR[7..6], AR  DR[5..0]
Fetch State Diagram
Decoding Instructions
Executing Instructions - ADD

ADD1: DR  M
ADD2: AC  AC + DR
Executing Instructions - AND

AND1: DR  M
AND2: AC  AC ^ DR
Executing Instructions - JMP

JMP1: PC  DR[5..0]
Executing Instructions - INC

INC1: AC  AC + 1
Very Simple CPU
Specification
FETCH1: AR  PC
FETCH2: DR  M, PC  PC + 1
FETCH3: IR  DR[7..6], AR  DR[5..0]
ADD1: DR  M
ADD2: AC  AC + DR
AND1: DR  M
AND2: AC  AC ^ DR
JMP1: PC  DR[5..0]
INC1: AC  AC + 1
Very Simple CPU State Diagram
 Establishing Data Paths
Regroup operations by destination
AR: ARPC; ARDR[5..0]
PC: PCPC + 1; PCDR[5..0]
DR: DRM
IR: IRDR[7..6]
AC: ACAC + DR; ACAC^DR; ACAC + 1
Establishing Data Paths

Determine functions of each component

• AR, DR, and IR only load data
• PC and AC load and increment data
Preliminary
Register Section
Optimize Register Section

• AR only supplies data to memory

 Optimize Register Section

• AR only supplies data to memory

• IR only supplies data to control unit
 Optimize Register Section

• AR only supplies data to memory

• IR only supplies data to control unit
• AC does not supply data to other
registers
 Optimize Register Section

• AR only supplies data to memory

• IR only supplies data to control unit
• AC does not supply data to other
registers
• Bus is 8-bits wide, but some registers
have fewer bits
 Optimize Register Section

• AR only supplies data to memory

• IR only supplies data to control unit
• AC does not supply data to other
registers
• Bus is 8-bits wide, but some registers
have fewer bits
• ALU needed to generate results
Final
Register
Section
Very Simple ALU
Generic Hardwired Control Unit
Introduction – Control Unit
• Control Unit controls system operations
• Control Unit issues a sequence of control signals to initiate sequences
of micro-operations, synchronized with the master clock.
• The control signals enables the associated processing hardware units
and handles exceptions.
• Primary responsibilities:
• Instruction interpretation – decodes the instructions
• Instruction sequencing

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Control Unit Design Methods
• Two major types of control organization –
• Hardwired control
• Microprogrammed control

• Factors to consider
• Cost effectiveness
• Efficiency

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Hardwired Control Unit
• Hardwired control unit – The control signals are generated by
hardwire using conventional sequential logic design techniques.
• Control logic is implemented with logic gates, flip-flops, decoders etc.

• Efficient – can be optimized to operate fast

• Design change is costly - requires changes in the hardwire
components and wiring

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Hardwired Control Unit – contd.

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Hardwired Control Unit – contd.

59
Hardwired Control Unit – contd.

Fig. 3. Example of control timing signal (Source: Computer System

Architecture 3rd ed., section 5-4, by Morris Mano ) 60
Hardwired Control Unit – contd.
The Outputs Of The Control Logic Circuit:

• 1. Signals to control the inputs of the registers

• 2. Signals to control the read and write inputs of memory
• 3. Signals to set, clear, or complement the flip-flops
• 4. Signals select a register for the bus
• 5. Signals to control the AC adder and logic circuit

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Control Functions & Micro-operations
Example
• The control unit design is done based on the register transfer micro-
operations and their analytical description.
• Examples of Control Functions And Micro-operations :
• Instruction Fetch & Decode phase:
• T0: MAR <- PC // MAR: Memory Address register
• T1: IR <-M[MAR], PC <- PC + 1 // IR: Instruction Register
• T2: D0, • • • , D7 <- Decode IR(op-code),
MAR <- IR(operand_addresses)
• Load to Accumulator(AC) operation (LDA opcode):
• D2T4: MDR <--- M [AR] // MDR: Memory Data Register
// D2: operation decoder signal for LDA opcode
• D2T5: AC <--- MDR, SC <--- 0 // SC: Sequence Counter
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H/W Control Logic Implementation
•Example of hardwired control logic implementation:
The control function C is (~a)b. The register transfer operation can be written as:
C: R1 <- R2, ~C: R1 <- R3
•Draw the circuit diagram for the register transfer operation.

Fig. 4. Example of control logic hardware implementation(Source: Computer

63
Organization and Architecture 3rd ed., chapter 3, by T.K. Ghosh)
Microprogrammed Control Unit
• Microprogrammed Control Unit – The control information is stored as
a microprogram in the control memory.
• Each instruction in the microprogram is a micro-instruction.

• Efficiency – slower than hardwired control unit

• But systematic method for controlling micro-operation sequences
• Design change is cost effective - requires change in the microprogram
only

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Microprogrammed Control Unit – contd.
• Control Memory: A ROM memory that is part of control unit.
• Each word in control memory, called control word, stores binary control
variables.
• Each word in control memory contains a microinstruction
• A microinstruction specifies one or more micro-operations.
• A sequence of microinstructions constitutes a microprogram.
• Each control word contains signals to activate one or more micro-
operations
• Microinstructions are retrieved in sequence and executed to activate
one or more micro-operations.
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Structure of a micro-instruction
• Control field holds the control information (may or may not be
encoded) required to issue control signals.
• Condition code allows conditional branching by specifying the
external conditions (status bits) that must be met.
• Branch address specifies the address of the next instruction to
execute if the branch condition is met

Control field Condition code Branch address

Fig. 5. Structure of a micro-instruction (Reference: Computer Organization

and Architecture 3rd ed., chapter 6, by T.K. Ghosh)

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Microprogrammed Control Unit Architecture

Fig. 6. Block diagram of general purpose microprogrammed control unit (Source:

Computer Organization and Architecture 3rd ed., chapter 6, by T.K. Ghosh) 67
Methods of Microprogramming
• Microprogramming Method Classification:
• Based on the organization of control information in micro-instruction:
1. Horizontal Microprogramming
2. Vertical Microprogramming

• Design Goals:
• Reduce Cost
• Reduce size of control memory -> reducing size of microinstructions
• Increase Efficiency
• Degree of parallelism in micro-operation activation

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 Horizontal Micro-programming
• An individual bit for each control signal
• The control fields are in un-encoded
format.
• High parallelism – several control signals
can be simultaneously generated.
• Large instruction size due to long format
• Higher cost: Requires larger control
memory Fig. 7. Horizontal Microinstruction (Source:
Computer Organization and Architecture 3rd ed.,

• High in efficiency: Due to High degree of chapter 6, by T.K. Ghosh)

parallelism
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Vertical micro-programming
• Control information is encoded as Micro-operation code
in control field of micro-instruction
• Requires a decoder for decoding control field
• Takes more time in generating control signals due to
decoding overhead
• Low degree of parallelism – one micro-op code activates
one control line
• Hybrid Approach: Multiple micro-operation codes, each
for disjoint groups of control signals, can be specified to
Fig. 8. Vertical Microinstruction (Source: Computer
issue control signals in parallel Organization and Architecture 3rd ed., chapter 6, by
T.K. Ghosh)
• Micro-instruction size is small, micro-program size
increases
• Cost Efficient: Requires smaller control memory 70
Emulator program
• Emulator: The set of microprograms that interpret a particular
instruction set or machine language ML is called an emulator for ML.
• The instruction op-code identifies the corresponding microprogram
that emulates
• The micro-programs can be written in symbolic form and translated
by an assembler to binary.

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