Digital Integrated

Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic

Design
Methodologies
December 10, 2002

© Digital Integrated Circuits2nd Design Methodologies

 The Design Productivity Challenge
10,000,000 100,000,000

Productivity (Trans./Staff-Month)
Logic Transistors per Chip (K)

.10m 1,000,000 Transistor/Staff Month 10,000,000

100,000 58%/Yr. compound 1,000,000

Complexity growth rate
.35m 10,000 100,000

1,000 10,000
X
100 X X
1,000
Xx X
X
2.5m 10 21%/Yr. compound 100
Productivity growth rate
1 10
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
2007
2009
A growing gap between design complexity and design productivity
Source: sematech97

© Digital Integrated Circuits2nd Design Methodologies

 A Simple Processor

MEMORY
INPUT/OUTPUT

CONTROL

DATAPATH

© Digital Integrated Circuits2nd Design Methodologies

 A System-on-a-Chip: Example

Courtesy: Philips

© Digital Integrated Circuits2nd Design Methodologies

 Impact of Implementation Choices

Domain-specific processor
100-1000
Energy Efficiency (in MOPS/mW)

Embedded microprocessor
10-100

(e.g. DSP)
Configurable/Parameterizable
Hardwired custom

1-10

0.1-1

None Somewhat Fully Flexibility

flexible flexible (or application scope)

© Digital Integrated Circuits2nd Design Methodologies

 Design Methodology

• Design process traverses iteratively between three abstractions:

behavior, structure, and geometry
• More and more automation for each of these steps

© Digital Integrated Circuits2nd Design Methodologies

 Implementation Choices

Digital Circuit Implementation Approaches

Custom Semicustom

Cell-based Array-based

Standard Cells Pre-diffused Pre-wired

Macro Cells
Compiled Cells (Gate Arrays) (FPGA's)

© Digital Integrated Circuits2nd Design Methodologies

 The Custom Approach
Intel 4004

© Digital Integrated Circuits2nd Courtesy Intel Design Methodologies

Transition to Automation and Regular Structures

Intel 4004 (‘71)

Intel 8080 Intel 8085

Intel 8286 Intel 8486

© Digital Integrated Circuits2nd Courtesy Intel Design Methodologies
 Cell-based Design (or standard cells)
Feedthrough cell Logic cell

Routing
channel
Rows of cells

Routing channel
Functional requirements are
module reduced by presence
(RAM, of more interconnect
multiplier, …) layers

© Digital Integrated Circuits2nd Design Methodologies

 Standard Cell — Example

[Brodersen92]

© Digital Integrated Circuits2nd Design Methodologies

 Standard Cell – The New Generation

Cell-structure
hidden under
interconnect layers

© Digital Integrated Circuits2nd Design Methodologies

 Standard Cell - Example

3-input NAND cell

(from ST Microelectronics):
C = Load capacitance
T = input rise/fall time

© Digital Integrated Circuits2nd Design Methodologies

 Automatic Cell Generation

Initial transistor Placed Routed Compacted Finished

geometries transistors cell cell cell

© Digital Integrated Circuits2nd Courtesy Acadabra Design Methodologies

 A Historical Perspective: the PLA
Product terms

x0 x1
x2
AND OR
plane plane

f0 f1

x0 x1 x2

© Digital Integrated Circuits2nd Design Methodologies

 Two-Level Logic
Every logic function can be
expressed in sum-of-products
format (AND-OR)

minterm

Inverting format (NOR-

NOR) more effective

© Digital Integrated Circuits2nd Design Methodologies

 PLA Layout – Exploiting Regularity
And-Plane Or-Plane
V DD  GND

x0 x0 x1 x1 x2 x2 f0 f1
Pull-up devices Pull-up devices

© Digital Integrated Circuits2nd Design Methodologies

 Breathing Some New Life in PLAs
River PLAs
 A cascade of multiple-output PLAs.
 Adjacent PLAs are connected via river routing.
PRE-CHARGE

BUFFER
B U FFER PR E-C H AR G E
CHARGE

BUFFER
PRE-

B U FFER PR E-C H AR G E
PRE-CHARGE

BUFFER

B U FFER PR E-C H AR G E

• No placement and routing needed.

CHARGE

BUFFER
PRE-

B U FFER PR E-C H AR G E
• Output buffers and the input buffers
of the next stage are shared.

© Digital Integrated Circuits2nd Courtesy B. Brayton Design Methodologies

 delay
Experimental Results 1.4

Area:
RPLAs (2 layers) 1.23
SCs (3 layers) - 1.00, 1
NPLAs (4 layers) 1.31
Delay
RPLAs 1.04
SCs 1.00
0.6
NPLAs 1.09
Synthesis time: for RPLA , synthesis time equals design time;
SCs and NPLAs still need P&R.
Also: RPLAs are regular and predictable
0.2
0 2 4 6 area

Layout of C2670 SC NPLA RPLA

Standard cell, Standard cell, Network of PLAs, River PLA,

2 layers channel routing 3 layers OTC 4 layers OTC 2 layers no additional routing

© Digital Integrated Circuits2nd Design Methodologies

 MacroModules

25632 (or 8192 bit) SRAM

Generated by hard-macro module generator

© Digital Integrated Circuits2nd Design Methodologies

 “Soft” MacroModules

© Digital Integrated Circuits2nd Synopsys DesignCompiler Design Methodologies

 “Intellectual Property”

A Protocol Processor for Wireless

© Digital Integrated Circuits2nd Design Methodologies
 Semicustom Design Flow
Design Capture Behavioral

HDL
HDL
Pre-Layout
Pre-Layout Structural
Design Iteration

Simulation
Simulation Logic
LogicSynthesis
Synthesis

Floorplanning
Floorplanning
Post-Layout
Post-Layout
Simulation
Simulation Placement
Placement Physical

Circuit
CircuitExtraction
Extraction Routing
Routing

Tape-out

© Digital Integrated Circuits2nd Design Methodologies

 The “Design Closure” Problem

Iterative Removal of Timing Violations (white lines)

© Digital Integrated Circuits2nd Courtesy Synopsys Design Methodologies

 Integrating Synthesis with
Physical Design
RTL (Timing) Constraints

Physical
PhysicalSynthesis
Synthesis

Macromodules Netlist with

Fixed netlists Place-and-Route Info

Place-and-Route
Place-and-Route
Optimization
Optimization
Artwork
© Digital Integrated Circuits2nd Design Methodologies
 Late-Binding Implementation

Array-based

Pre-diffused Pre-wired
(Gate Arrays) (FPGA's)

© Digital Integrated Circuits2nd Design Methodologies

 Gate Array — Sea-of-gates

polysilicon

VD D

metal
rows of Uncommited
uncommitted possible
cells GND contact Cell

In1 In2 In3 In4

routing
channel Committed
Cell
(4-input NOR)
Out

© Digital Integrated Circuits2nd Design Methodologies

 Sea-of-gate Primitive Cells
Oxide-isolation

PMOS

PMOS

NMOS

NMOS
NMOS

Using oxide-isolation Using gate-isolation

© Digital Integrated Circuits2nd Design Methodologies

 Example: Base Cell of Gate-Isolated GA
VDD 1
2
3
4
continuous
5
p-diff strip
6
7
8
9
10
11
12 n-well
continuous 13 p-well
n-diff strip 14 n-diff
15 p-diff
16 poly
17 m1
contact for 18
isolator m2
19 contact
20
GND 21

© Digital Integrated Circuits2nd From Smith97 Design Methodologies

 Example: Flip-Flop in Gate-Isolated GA
VDD

CLR
Q

CLK
Q

GND

© Digital Integrated Circuits2nd From Smith97 Design Methodologies

 Sea-of-gates
Random Logic

Memory
Subsystem

LSI Logic LEA300K

(0.6 m CMOS)

© Digital Integrated Circuits2nd Courtesy LSI Logic Design Methodologies

 The return of gate arrays?
Via programmable gate array
(VPGA)

Via-programmable cross-point

metal-5 metal-6

programmable via

Exploits regularity of interconnect

© Digital Integrated Circuits2nd [Pileggi02] Design Methodologies

 Prewired Arrays
Classification of prewired arrays (or field-programmable devices):
 Based on Programming Technique
 Fuse-based (program-once)
 Non-volatile EPROM based
 RAM based
 Programmable Logic Style
 Array-Based
 Look-up Table
 Programmable Interconnect Style
 Channel-routing
 Mesh networks

© Digital Integrated Circuits2nd Design Methodologies

 Fuse-Based FPGA
antifuse polysilicon ONO dielectric

n+ antifuse diffusion

2 l

Open by default, closed by applying current pulse

© Digital Integrated Circuits2nd From Smith97 Design Methodologies

 Array-Based Programmable Logic
I5 I4 I3 I2 I1 I0 Programmable
OR array I3 I2 I1 I0 Programmable
OR array I5 I4 I3 I2 I1 I0 Fixed OR array

Programmable AND array Fixed AND array Programmable AND array

O 3O 2O 1O 0 O3O2O1O0 O 3O 2O 1 O 0

PLA PROM PAL

Indicates programmable connection
Indicates fixed connection

© Digital Integrated Circuits2nd Design Methodologies

 Programming a PROM
1 X2 X1 X0

: programmed node
NA NA f 1 f 0

© Digital Integrated Circuits2nd Design Methodologies

 More Complex PAL
programmable AND array (2 i 3 jk) k macrocells

product
1 terms
j -wide OR array

D Q
j OUT

j
macrocell
CLK
A B C i i inputs

i inputs, j minterms/macrocell, k macrocells

© Digital Integrated Circuits2nd From Smith97 Design Methodologies

 2-input mux
as programmable logic block
Configuration
A B S F=
0 0 0 0
0 X 1 X
A 0 0 Y 1 Y
F 0 Y X XY
X 0 Y XY
B 1
Y 0 X XY
Y 1 X X1 Y
1 0 X X
S
1 0 Y Y
1 1 1 1

© Digital Integrated Circuits2nd Design Methodologies

 Logic Cell of Actel Fuse-Based FPGA

B 1
SA Y
1
C

D 1
SB
S0
S1

© Digital Integrated Circuits2nd Design Methodologies

 Look-up Table Based Logic Cell

In Out
Memory

Out 00 00
01 1
10 1
11 0

ln1 ln2

© Digital Integrated Circuits2nd Design Methodologies

 LUT-Based Logic Cell Figure must be
4
updated
C1....C4

xx xxxx xxxx xxxx

D4 Bits xxxx
Logic control
D3 xx xx
function xx
xx x xx x
D2 of xx
xxx
D1
Logic xx xx
functionx x
x
of x
xxx x
F4
Bits xxxx
F3 Logic xx control xx
function xx
xx x xx x
F2 of xx
xxx
F1
xx xx
x
xxxxx x
H x
P
Multiplexer Controlled
by Configuration Program
Xilinx 4000 Series

© Digital Integrated Circuits2nd Courtesy Xilinx Design Methodologies

 Array-Based Programmable Wiring
Interconnect
Point
M

Programmed interconnection Input/output pin

Cell

Horizontal
tracks

Vertical tracks

© Digital Integrated Circuits2nd Design Methodologies

 Mesh-based Interconnect Network
Switch Box

Connect Box

Interconnect
Point

© Digital Integrated Circuits2nd Courtesy Dehon and Wawrzyniek Design Methodologies

 Transistor Implementation of Mesh

© Digital Integrated Circuits2nd Courtesy Dehon and Wawrzyniek Design Methodologies

 Hierarchical Mesh Network

Use overlayed mesh

to support longer connections

Reduced fanout and reduced

resistance

© Digital Integrated Circuits2nd Courtesy Dehon and Wawrzyniek Design Methodologies

 EPLD Block Diagram
Primary inputs Macrocell

© Digital Integrated Circuits2nd Courtesy Altera Design Methodologies

 Altera MAX

© Digital Integrated Circuits2nd From Smith97 Design Methodologies

 Altera MAX Interconnect Architecture
column channel row channel

t PIA

LAB1 LAB2

LAB

PIA

t PIA
LAB6

Array-based Mesh-based
(MAX 3000-7000) (MAX 9000)

© Digital Integrated Circuits2nd Courtesy Altera Design Methodologies

 Field-Programmable Gate Arrays
Fuse-based
I/O Buffers

P rogram/ Te s t/D iag nostics

Ve rtical ro utes

Standard-cell like
floorplan
I/O B u ffe rs

I/O B u ffe rs
R ows o f logic m odule s
R outing channels

I/O Buffers

© Digital Integrated Circuits2nd Design Methodologies

 Xilinx 4000 Interconnect Architecture

12 Quad

8 Single

4 Double

3 Long

Direct
CLB 2 Connect

3 Long
12 4 4 8 4 8 4 2

Quad Long Global Long Double Single Global Carry Direct

Clock Clock Chain Connect

© Digital Integrated Circuits2nd Courtesy Xilinx Design Methodologies

 RAM-based FPGA

Xilinx XC4000ex

© Digital Integrated Circuits2nd Courtesy Xilinx Design Methodologies

 A Low-Energy FPGA (UC Berkeley)
 Array Size: 8x8 (2 x 4
LUT)
 Power Supply: 1.5V &
0.8V
 Configuration: Mapped as
RAM
 Toggle Frequency:
125MHz
 Area: 3mm x 3mm

© Digital Integrated Circuits2nd Design Methodologies

 Larger Granularity FPGAs
PADDI-2 (UC Berkeley)
 1-mm 2-metal
CMOS tech

 1.2 x 1.2 mm2

 600k transistors

 208-pin PGA

 fclock = 50 MHz

 P
av = 3.6 W @ 5V

 Basic Module: Datapath

© Digital Integrated Circuits2nd Design Methodologies

 Design at a crossroad
System-on-a-Chip

500 k Gates FPGA  Embedded applications where

Analog
Multi-
Spectral + 1 Gbit DRAM cost, performance, and
RAM
Imager energy are the real issues!
Preprocessing
 DSP and control intensive
64 SIMD Processor C  Mixed-mode
Array + SRAM system  Combines programmable and
+2 Gbit application-specific modules
Image Conditioning DRAM
100 GOPS Recog-
 Software plays crucial role
nition

© Digital Integrated Circuits2nd Design Methodologies

 Addressing the Design Complexity Issue
Architecture Reuse

Reuse comes in generations

Ge ne ratio n Re us e e le m e nt S tatus
1st S tandard c e lls We ll e s tablis he d
2 nd IP blo c ks Be ing intro duc e d
3 rd Arc hite c ture Eme rg ing
4 th IC Early re s e arc h

Source: Theo Claasen (Philips) – DAC 00

© Digital Integrated Circuits2nd Design Methodologies
 Architecture ReUse
 Silicon System Platform
 Flexible architecture for hardware and software
 Specific (programmable) components
 Network architecture
 Software modules
 Rules and guidelines for design of HW and SW
 Has been successful in PC’s
 Dominance of a few players who specify and control architecture
 Application-domain specific (difference in constraints)
 Speed (compute power)
 Dissipation
 Costs
 Real / non-real time data

© Digital Integrated Circuits2nd Design Methodologies

 Platform-Based Design

“Only the consumer gets freedom of choice;

designers need freedom from choice”
(Orfali, et al, 1996, p.522)
 A platform is a restriction on the space of possible implementation
choices, providing a well-defined abstraction of the underlying
technology for the application developer
 New platforms will be defined at the architecture-micro-architecture
boundary
 They will be component-based, and will provide a range of choices
from structured-custom to fully programmable implementations
 Key to such approaches is the representation of communication in
the platform model

© Digital Integrated Circuits2nd Source:R.Newton Design Methodologies

 Berkeley Pleiades Processor

• 0.25um 6-level metal

FPGA CMOS
• 5.2mm x 6.7mm

Reconfigurable
• 1.2 Million transistors
Data-path • 40 MHz at 1V
• 2 extra supplies: 0.4V,
Interface

ARM8 Core 1.5V

• 1.5~2 mW power
dissipation
© Digital Integrated Circuits2nd Design Methodologies
 Heterogeneous Programmable Platforms
FPGA Fabric

Embedded memories
Embedded PowerPc

Hardwired multipliers

Xilinx Vertex-II Pro

High-speed I/O

© Digital Integrated Circuits2nd Courtesy Xilinx Design Methodologies

 Summary
 Digital CMOS Design is kicking and healthy
 Some major challenges down the road
caused by Deep Sub-micron
 Super GHz design
 Power consumption!!!!
 Reliability – making it work
Some new circuit solutions are bound to emerge
 Who can afford design in the years to come?
Some major design methodology change in
the making!

© Digital Integrated Circuits2nd Design Methodologies