CST1500

Computer Systems Architecture and

Operating Systems

Lecture 5– Sequential Logic

1
 Overview
• Last Lecture

• This Lecture
– Sequential logic circuits
– Source: Chapter 11 (10th
edition)
• Next Lecture
– Memory and Storage Systems

2
 Introduction
• Combinatorial logic circuit - the same inputs always
produces the same outputs (last lecture)

Inputs Combinational Outputs

circuit

• Sequential logic circuit - outputs depend not only on

the present inputs, but also on the past history (this
lecture)
Inputs Combinational Outputs
circuit

Memory

3
 Introduction (cont)
• There are two types of Sequential Circuits
– Synchronous – output changes at a certain time
• State changes occur in synchronization to a clock signal
• Input changes occur between clock pulses
• State changes occur at the clock pulses

– Asynchronous –output changes any time

• State changes occur as changes in inputs occur
• Event driven
• We will not study these

4
 Memory Element

• Memory element device that can remember a value for a certain period, or
change based on the input instruction

• Example: Latch and flip-flop

• Flip-flop is a memory element which change its condition based on clock

signal
 Memory Circuits
• Set-reset latch
• D-type flip-flop
• T-type flip-flop
• JK-type flip-flop

Lecture 5 - Sequential Logic 6

 Set-Reset Latch
• If you tie the output of the circuit to one of its inputs then the
circuit saves state. In this case output is on Q

• Start with a R = S = Q = 0 (Q̅ = 1), the latch stores a 0

R
Q
NOR
A B Q
0 0 1
Q
S 0 1 0
1 0 0
1 1 0

7
 Set (Q) the SR Latch
NOR
• Q=0 A B Q
R 0 0 1
Q
0 1 0

S
Q 1 0 0

• Now toggle S = 1 (set the latch) 1 1 0

R R R R
Q Q Q Q

Q Q Q Q
S S S S

• Q = 1, Now toggle S = 1 (set the latch)

R R R
Q Q Q

Q Q Q
S S S

8
 Reset (Q) SR Latch
NOR
• Q=1 A B Q
R 0 0 1
Q
0 1 0
S
Q 1 0 0

• Now toggle R = 1 (reset the latch) 1 1 0

R R R R
Q Q Q Q

Q Q
Q Q S
S S S

• Q = 0, Now toggle R = 1 (reset the latch)

R R R
Q Q Q

Q Q Q
S S S

9
 Set-Reset Latch
• Regardless of Q,
– By setting S = 1 the latch is set (Q = 1)
– By setting R = 1 the latch is reset (Q = 0)

S R Action
0 0 None
0 1 Q=0
1 0 Q=1
1 1 Invalid (why?)
From: http://en.wikipedia.org/wiki/File:R-S_mk2.gif

• The SR Latch actually has three inputs, Set, Reset and its current state.
The Invalid or Undefined State occurs at both S and R being at 1.

1
0
Clocked (Enabled) SR Flip-Flop
• The SR latch is a nice trick
• If we add a control line to the circuit then we can turn the
latch on and off when we want to

R
Q
Enable
Q
S

11
 Clocked SR NAND flip-flop
• By inverting the signals into the SR latch, a flip-flop can
be built using only NAND gates (De Morgan)
– And recall that a NAND gate can be built with 2 transistors

S
Q
Enable
Q
R

12
 D-Type Flip-Flop
• Since S = R, Combine into one line: D

D
D Q
Q
Enable >C Q
Q
D-Type flip-flop
Triangle indicates edge-
triggered

13
 T Flip-Flop
• Toggle Flip-Flop
– The output is inverted when
• Toggle is held high
• Enable is “clocked”

Toggl
Q
e
Enable
Q

15
 JK Flip-Flop
• One flip-flop to rule them all (the universal flip-flop)

>C Q

K
K Q
Q JK flip-flop

Enable
Q
J

16
 JK Flip-Flop
• One flip-flop to rule them all (the universal flip-flop)
– Set J = K to get T flip-flop
– Set J = K to get a D flip-flop

>C Q >C Q >C Q

J J J

K K K
Q Q Q
JK flip-flop T flip-flop D flip-flop

17
 Asynchronous Ripple Counter
• A 1-bit counter switches between 0 and 1 each cycle
– It’s a toggle flip-flop
Clock >C Q
– It’s also a divide by 2
J
High

Clock

Data
Time t1 t2 t3 t4 t5
Output Q

18
 Asynchronous Ripple Counter
• A 2-bit counter
– The low bit toggles every full clock cycle
– The high bit toggles at half the clock cycle rate
• Tie the output of the low bit to the input of the high bit

19
 Synchronous Counter
• The async counter has the problem that the propagation
delay is inconsistent; a function of the number of transistors
the signal passes through
• Ideally the flip-flops will clock at the same time
– This is achieved with a synchronous counter
– Logic is added to set the next state based on the previous state

20
Sequential Circuits

21
Binary Snakes and Ladders

0 = move 1
1 = move 2 22
 Detect a Given Input Sequence
• Detect the input sequence 11101
• Single input x
• Single output z
• Consider repeating sequences

1
1 1 1 0 1
S0 S1 S2 S3 S4 S5
0 0 0 0 0

Z=0 Z=1

State Transition Diagram

23
 Detect a Given Input Sequence
• Initial state table

Input Present State Next State Output

0 S0 S0 0
1 S0 S1 0
0 S1 S0 0
1 S1 S2 0
0 S2 S0 0
1 S2 S3 0
0 S3 S4 0
1 S3 S3 0
0 S4 S0 0
1 S4 S5 0
0 S5 S0 1
1 S5 S2 1

24
 Detect a Given Input Sequence
• Complete state table
Present State Input Next State Output
A B C X A' B' C' Z
0 0 0 0 0 0 0 0
0 0 0 1 0 0 1 0
0 0 1 0 0 0 0 0
0 0 1 1 0 1 0 0
0 1 0 0 0 0 0 0
0 1 0 1 0 1 1 0
0 1 1 0 1 0 0 0
0 1 1 1 0 1 1 0
1 0 0 0 0 0 0 0
1 0 0 1 1 0 1 0
1 0 1 0 0 0 0 1
1 0 1 1 0 1 0 1
26
 Detect a Given Input Sequence
X Z
Combinatorial
ABC A’B’C
Logic
’
Circuit

A B C
D D D
Q Q Q
Clock
>C >C >C

27
Registers

28
 Tristate Buffer
• The clock is used to enable flip-flop load
• The output can be controlled with a 3-state buffer
– Or a 3-state inverter

D Y Input (D) Output (Y)

E
Output Enable (E)

29
 74LS374
• 3-STATE Octal D- Type Transparent
Latches and Edge- Triggered Flip-
Flops

• Output Control
– “read line”
• Clock
– “write line”

30
 Summary
• Two types of logic circuits
- Combinatorial logic circuit
- Sequential logic circuits

• Flip-flops are used to build digital systems that rely on the sequential
logic like a counter and recorders as well as building RAM and
registers.

• Memory Circuits
- Set-reset latch
- D-type flip-flop
- T-type flip-flop
- JK-type flip-flop