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I2C Protocol

The I2C protocol uses only two bidirectional lines (SDA and SCL) to facilitate communication between integrated circuits on a circuit board. Devices are identified by unique addresses and can act as transmitter or receiver on the shared bus. Communication begins with a start condition and ends with a stop condition, with clock synchronization and acknowledgment bits used to control data transfer. The protocol supports multiple speeds and arbitration for multi-master systems.

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84 views20 pages

I2C Protocol

The I2C protocol uses only two bidirectional lines (SDA and SCL) to facilitate communication between integrated circuits on a circuit board. Devices are identified by unique addresses and can act as transmitter or receiver on the shared bus. Communication begins with a start condition and ends with a stop condition, with clock synchronization and acknowledgment bits used to control data transfer. The protocol supports multiple speeds and arbitration for multi-master systems.

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adyadesai7
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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I2C Protocol

(Inter-Integrated Controller)
Introduction
● I2C stands for Inter-Integrated Circuit.
● Developed by Philips Semiconductor.
● A widely used serial communication protocol for connecting multiple devices on a single
bus.

Purpose
● Facilitates communication between integrated circuits on a circuit board.
● Minimizes wiring complexity by using only two wires:
- SDA (Serial Data Line) and SCL (Serial Clock Line).
● Suitable for connecting microcontrollers, sensors, memory devices, and other peripherals.
Features
● Devices on the I2C bus are identified by unique 7-bit or 10-bit addresses.
● Master device addresses specific slaves for communication.
● It support Single Master-Multi Slave & Multi Master-Multi Slave.
● In I2C only two buses are required for the communication:
- Serial data bus (SDA) & Serial clock bus (SCL).
● Two-Wire Communication: SDA and SCL lines for bidirectional data transfer and clock
synchronization.
● It is worked in half duplex mode.
● Start and Stop Conditions: Communication begins with a start condition and ends with a
stop condition.
● Used for low-speed communication.
Flag Description:
Serial Data Line (SDA):
● Bidirectional line for transmitting data between master and slave devices.
● Devices can pull SDA low to indicate logic 0, and release it for logic 1.
● Open-drain or open-collector configuration allows multiple devices to share the line.

Serial Clock Line (SCL):


● Unidirectional line controlled by the master.
● Generates clock pulses for synchronization of data transmission.
● SCL pulses indicate when data on SDA should be sampled.

Start Condition (S):


● Initiates communication on the bus.
● Master pulls SDA low while SCL is high to signal the start of a data transfer.
Stop Condition (P):
● Indicates the end of communication.
● Master releases SDA from low to high while SCL is high, marking the conclusion of data
transfer.

Acknowledgment (ACK):
● Sent by the receiver (master or slave) after successfully receiving a byte.
● Acknowledgment bit is pulled low by the receiver.
● Lack of acknowledgment may indicate an error or the end of data transmission.

Clock Pulse (SCL) Timing:


● Data on the SDA line is valid on the transition from a low to high clock state (rising edge).
● Devices should sample and change data on the SDA line when SCL is low (falling edge).
Repeated Start Condition:
● Allows the master to initiate another data transfer without releasing control of the bus.
● Achieved by generating a start condition without first generating a stop condition.

Bus Arbitration:
● In multi-master configurations, devices contend for control of the bus.
● Arbitration is determined by which master holds the SDA line low during the ninth clock
cycle.

Clock Stretching:
● Slaves can stretch the clock period by holding the SCL line low.
● Used by a slave to slow down the master if it needs additional time for processing.
Start Condition

● In the idle state SDA and SCL are both


high.
● The start condition occurs when a node
- First pulls SDA low
- Then pulls SCL low
● This "claims the bus".
● Node is now the master.
● Prevents any other nodes from taking
control of the bus.
● Reduces the risk of contention.
● Master that has seized the bus also starts the
clock.
Slave address

● Each I2C node on a bus must have a


unique, fixed address.
● Normally 7 bits long, MSB first.
● 10 bit addresses also supported, but
these are uncommon.
● Address may be hard coded.
● Address may be (partially)
configurable via external address
lines or jumpers.
Read/write bit

● Read/write bit follows the slave


address.
● Set by master to indicate desired
operation
- 0→ master wants to write data to
slave
- 1→ master wants to read data from
slave
● Often interpreted and/or decoded as
part of the address byte.
Ack(knowledge) bit

● Sent by the receiver of a byte of data


- 0→ acknowledgement (ACK)
- 1→ negative acknowledgement (NACK)
● Recall that I2C is idle high, Lack of
response = NACK.
● Used after slave address and each data byte.
● ACK after data byte(s) confirms receipt of
data.
● ACK after slave address confirms that A
slave with that address is on the bus
● The slave is ready to read/write data
(depending on R/W bit).
Data byte(s)

● Data byte contains the information


being transferred between master
and slave.
● Memory or register contents,
addresses, etc.
● Always 8 bit long, MSB first.
● Always followed by an
acknowledgement bit.
● Set to zero by the receiver if data has
been received properly.
Multiple data bytes

● In many cases, multiple data bytes are sent in one I2C frame.
● Each data byte is followed by an ACK bit.
● Bytes may be be all "data" or some may represent an internal address, etc.
● Ex: first byte is a register location and second byte is the data to be written to that
register.
Stop condition

● Stop condition indicates the end of data


bytes.
● First, SCL returns (and remains) high
● Then, SDA returns (and remains) high
● Recall that for data bytes, SDA only
transitions when clock is low
● SDA transition when SCL high = stop
condition
● Bus becomes idle
● No clock signal
● Any node can now use the start condition to
claim
● the bus and begin a new communication
About "open drain"

● Each line (SDA and SDL) is connected to


voltage (Vcc or VDD) via a "pull up" resistor
One resistor per line (not per device).
- Each 12C device contains logic that can open
and close a drain
- When drain is "closed," the line is pulled low
(connected to ground)
- When drain is "open," the line is pulled high
(connected to voltage)
- I2C lines are high in the idle state Sometimes
called an "open drain" system
Modes / Speeds
● I2C can operate at different bus speeds referred to as "modes".
● Table shows max speeds for each mode.

● High speed mode devices are backwards compatible to lower speeds,


- Transmit a special sequence to switch the bus to HS mode.
● Ultra fast mode is unidirectional (write only),
- Also requires modification to the protocol and frames.
Clock Synchronization
● I2C clock synchronization is a process that uses a wired-AND connection between
devices on the SCL line. It involves the following steps:
● All masters generate their own clock on the SCL line.
● A master pulls the clock low, and it stays low until all masters put the clock into a high
state.
● The clock is in a high state until the first master pulls it low.
● Each controller device monitors the SCL line.
● When the SCL does not match its expected output, the controller device reacts.
● After the start of the serial clock pulse, all controllers pull down on SCL to
complete the serial clock pulse.
● During an SCL low phase, any I2C device on the bus may hold down SCL to
prevent it from rising again.
● This enables it to slow down the SCL clock rate or to stop I2C communication for
a while.
Arbitration
● I2C arbitration resolves conflicts when multiple devices attempt to transmit
simultaneously on the same bus.
● Devices compare data during the acknowledge bit; the one with a dominant low state
wins.
● State during acknowledge bit determines arbitration; dominant low state has priority.
● No inherent priority; losing devices release the bus and wait for the next
opportunity.

● Arbitration ensures fairness but can introduce delays in communication.

● Synchronized clocks, addressing, and bus access strategies minimize collision


likelihood.

● Essential in multi-master setups for efficient conflict resolution.

● Arbitration starts when two or more devices attempt to control the bus
simultaneously.
Clock Stretching
● Definition: Slave pauses communication by holding the clock low in I2C clock stretching.
● Purpose: Used when slave needs extra time during read operations.
● Implementation: Slave holds clock low; master waits for it to go high.
● Impact on Bandwidth: Can slow down communication, reducing bus bandwidth,
especially with multiple devices.
● Timing: Allowed after ACK bit and before 1st bit in High-Speed Mode; illegal between
bits 2-9 due to current source boosting.

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