Scribd
Upload
15 views25 pages

Lecture 3

This document discusses computer interrupts and how components are connected in a computer system. It describes how interrupts allow components like I/O devices to interrupt the CPU's normal processing. It explains how the CPU handles interrupts by saving context, jumping to an interrupt handler, and then restoring context. It also discusses priorities between interrupts and how multiple interrupts can be handled sequentially or nested. The document then covers how computer components like the CPU, memory, and I/O devices are connected via buses for addresses, data, and control signals to allow communication between parts.

Uploaded by

ibi Sheikh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
15 views25 pages

Lecture 3

This document discusses computer interrupts and how components are connected in a computer system. It describes how interrupts allow components like I/O devices to interrupt the CPU's normal processing. It explains how the CPU handles interrupts by saving context, jumping to an interrupt handler, and then restoring context. It also discusses priorities between interrupts and how multiple interrupts can be handled sequentially or nested. The document then covers how computer components like the CPU, memory, and I/O devices are connected via buses for addresses, data, and control signals to allow communication between parts.

Uploaded by

ibi Sheikh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 25

Chapter 3

Top Level View of Computer Function and


Interconnection
Interrupts
Mechanism by which other modules (e.g. I/O) may
interrupt normal sequence of processing
Program
 e.g. overflow, division by zero
Timer
 Generated by internal processor timer
 Used in pre-emptive multi-tasking
I/O
 from I/O controller
Hardware failure
 e.g. memory parity error
Program Flow Control
Interrupt Cycle
Added to instruction cycle
Processor checks for interrupt
Indicated by an interrupt signal
If no interrupt, fetch next instruction
If interrupt pending:
Suspend execution of current program
Save context
Set PC to start address of interrupt handler routine
Process interrupt
Restore context and continue interrupted program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Program Timing
Short I/O Wait:
Program Timing
Long I/O Wait:
Instruction Cycle (with Interrupts) - State
Diagram
Multiple Interrupts
Disable interrupts
Processor will ignore further interrupts whilst
processing one interrupt
Interrupts remain pending and are checked after first
interrupt has been processed
Interrupts handled in sequence as they occur
Define priorities
Low priority interrupts can be interrupted by higher
priority interrupts
When higher priority interrupt has been processed,
processor returns to previous interrupt
Multiple Interrupts - Sequential
Multiple Interrupts – Nested
Time Sequence of Multiple Interrupts
Connecting
All the units must be connected
Different type of connection for different type of unit
Memory
Input/Output
CPU
Computer Modules
Memory Connection
Receives and sends data
Receives addresses (of locations)
Receives control signals
Read
Write
Timing
Input/Output Connection(1)
Similar to memory from computer’s viewpoint
Output
Receive data from computer
Send data to peripheral
Input
Receive data from peripheral
Send data to computer
Input/Output Connection(2)
Receive control signals from computer
Send control signals to peripherals
e.g. spin disk
Receive addresses from computer
e.g. port number to identify peripheral
Send interrupt signals (control)
CPU Connection
Reads instruction and data
Writes out data (after processing)
Sends control signals to other units
Receives (& acts on) interrupts
Buses
There are a number of possible interconnection
systems
Single and multiple BUS structures are most common
e.g. Control/Address/Data bus (PC)
e.g. Unibus (DEC-PDP)
What is a Bus?
A communication pathway connecting two or more
devices
Usually broadcast
Often grouped
A number of channels in one bus
e.g. 32 bit data bus is 32 separate single bit channels
Power lines may not be shown
Data Bus
Carries data
Remember that there is no difference between “data”
and “instruction” at this level
Width is a key determinant of performance
8, 16, 32, 64 bit
Address bus
Identify the source or destination of data
e.g. CPU needs to read an instruction (data) from a
given location in memory
Bus width determines maximum memory capacity of
system
e.g. 8080 has 16 bit address bus giving 64k address space
Control Bus
Control and timing information
Memory read/write signal
Interrupt request
Clock signals
Bus Interconnection Scheme

You might also like