Title of the Course: COMPUTER ORGANIZATION AND ARCHITECTURE

Course Code:18EC35
Semester: 3rd ,B.E
Department: Electronics and Communication
Name and designation of the faculty:Mangala S Jolad,Asst Prof

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 MODULE 5
Basic Processing Unit

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SOME FUNDAMENTAL CONCEPTS
A typical computing task consists of a series of steps specified by a
sequence of machine instructions that constitute a program.
An instruction is executed by carrying out a sequence of operations.
Processor fetches one instruction at a time and perform the operation
specified.
Instructions are fetched from successive memory locations until a
branch or a jump instruction is encountered.
Processor keeps track of the address of the memory location containing
the next instruction to be fetched using Program Counter(PC).
Instruction Register(IR)

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Executing an Instruction
Fetch the contents of the memory location pointed to by the PC.
The contents of this location are loaded in to the IR(fetchphase).
IR←[[PC]]
Assuming that the memory is byte addressable, increment the
contents of the PC by 4(fetchphase).
PC←[PC]+4
Carry out the actions specified by the instruction in the IR
(execution phase).
The first 2 steps are referred to as Fetch Phase.
Step 3 is referred to as Execution Phase.


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SOME FUNDAMENTAL CONCEPTS

The operation specified by an instruction can be carried out by

performing one or more of the following actions:
1.Read the contents of a given memory-location and load them into a
register.
2.Read data from one or more registers.
3.Perform an arithmetic or logic operation and place the result into a
register.
4.Store data from a register into a given memory-location.

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The hardware-components needed to
perform these actions are shown in Figure.
The operation specified by an instruction
can be carried out by performing one or
more of the following actions:
1.Read the contents of a given memory-
location and load them into a register.
2.Read data from one or more registers.
3.Perform an arithmetic or logic
operation and place the result into a
register.
4.Store data from a register into a given
memory-location.

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SINGLE BUS ORGANIZATION
ALU and all the registers are interconnected via a
Single Common Bus as shown in Fig.
Data & address lines of the external memory-bus is
connected to the internal processor-bus via MDR &
MAR respectively.
MDR has 2 inputs and 2 outputs. Data may be
loaded
→ into MDR either from memory-bus (external) or
from processor-bus (internal).
MAR input is connected to internal-bus & MAR
output is connected to external-bus.
Instruction Decoder & Control Unit is
responsible for
→ issuing the control-signals to all the units inside
the processor.
→ implementing the actions specified by the
instruction (loaded in the IR).
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Register R0 through R(n-1) are the Processor Registers.
The programmer can access these registers for general-purpose use.
Only processor can access 3 registers Y, Z & Temp for temporary
storage during program-execution.
The programmer cannot access these 3 registers.
In ALU,
A input gets the operand from the output of the multiplexer.
B input gets the operand directly from the processor-bus.
There are 2 options provided for A input of the ALU.
MUX is used to select one of the 2 inputs.
MUX selects either output of Y or constant-value 4( which is used to
increment PC content).

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The operation specified by an instruction can be carried out by
performing one or more of the following actions:
1.Read the contents of a given memory-location and load them into a
register.
2.Read data from one or more registers.
3.Perform an arithmetic or logic operation and place the result into a
register.
4.Store data from a register into a given memory-location.

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REGISTER TRANSFERS
Instruction execution involves a sequence of steps in which data are
transferred from one register to another.
For each register, two control-signals are used: Ri in & Riout , these are
called Gating Signals.
Riin=1, a data on bus is loaded into Ri.
Riout=1, a content of Ri is placed on bus.
Riout=0,a bus can be used for transferring data for other registers.
For example in Move R1, R2
This can be accomplished as follows:
Enable the output of registers R1 by setting R1out to 1 as in fig.
This places the contents of R1 on processor-bus.
Enable the input of register R2 by setting R2in to 1.
This loads data from processor-bus into register R2.
All operations and data transfers within the processor take place within1
0
time-periods defined by the processor-clock.
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Input & Output Gating for one Register Bit
A 2-input multiplexer is used to select the data applied to the input of an
edge-triggered D flip-flop.
Riin=1 : a mux selects data on bus. This data will be loaded into flip-flop
at rising-edge of clock.
Riin=0 :a mux feeds back the value currently stored in flip-flop as shown
in Figure.
Q output of flip-flop is connected to bus via a tri-state gate.
Riout=0: a gate's output is in the high-impedance state.
Riout=1:the gate drives the bus to 0 or 1, depending on the value of Q.

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PERFORMING AN ARITHMETIC OR LOGIC OPERATION

The ALU performs arithmetic operations on the 2 operands applied to its A and B
inputs.
One of the operands is output of MUX and the other operand is obtained directly from
processor-bus.
The result (produced by the ALU) is stored temporarily in register Z.
The sequence of operations for [R3] = [R1]+[R2] is as follows:
 R1out, Yin
 R2out, SelectY, Add, Zin
 Zout, R3in
Instruction execution proceeds as follows:
Step 1 : Contents from register R1 are loaded into register Y.
Step2 : Contents from Y and register R2 are applied to the A and B inputs of ALU
Addition is performed & Result is stored in the Z register.
Step 3 : The contents of Z register is stored in the R3 register.

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CONTROL-SIGNALS OF MDR
The MDR register has 4 control-signals as shown in Figure.
MDRin & MDRout control the connection to the internal processor data bus &
MDRinE & MDRoutE control the connection to the memory Data bus.
MAR register has 2 control-signals.
MARin controls the connection to the internal processor address bus &
MARout controls the connection to the memory address bus

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FETCHING A WORD FROM MEMORY
To fetch instruction/data from memory, processor transfers required
address to MAR.
At the same time, processor issues Read signal on control-lines of
memory-bus.
When requested-data are received from memory, they are stored in
MDR.
 From MDR, they are transferred to other registers.
The response time of each memory access varies (based on cache miss,
memory-mapped I/O).
 To accommodate this, MFC is used. (MFC à Memory Function
Completed).
MFC informs the processor that the requested operation has been
completed by addressed-device.

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FETCHING A WORD FROM MEMORY
To fetch instruction/data from memory, processor transfers required
address to MAR.
At the same time, processor issues Read signal on control-lines of
memory-bus.
When requested-data are received from memory, they are stored in
MDR.
 From MDR, they are transferred to other registers.
The response time of each memory access varies (based on cache miss,
memory-mapped I/O).
 To accommodate this, MFC is used. (MFC à Memory Function
Completed).
MFC informs the processor that the requested operation has been
completed by addressed-device.

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FETCHING A WORD FROM MEMORY
To fetch instruction/data from memory, processor transfers required
address to MAR.
At the same time, processor issues Read signal on control-lines of
memory-bus.
When requested-data are received from memory, they are stored in
MDR.
 From MDR, they are transferred to other registers.
The response time of each memory access varies (based on cache miss,
memory-mapped I/O).
 To accommodate this, MFC is used. (MFC à Memory Function
Completed).
MFC informs the processor that the requested operation has been
completed by addressed-device.

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Storing a Word in Memory
Consider the instruction Move R2,(R1). This requires the following sequence:
1. R1out, MARin ;desired address is loaded into MAR.
2. R2out, MDRin, Write ;data to be written are loaded into MDR & Write
command is issued.
3. MDRoutE, WMFC ;load data into memory-location pointed by R1
from MDR.

EXECUTION OF A COMPLETE INSTRUCTION

Consider the instruction Add (R3),R1 which adds the contents of a memory-location
pointed by R3 to register R1.
Executing this instruction requires the following actions:
1. Fetch the instruction.
2. Fetch the first operand.
3. Perform the addition &
4. Load the result into R1.
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Instruction execution proceeds as follows:
1. The instruction-fetch for Add (R3),R1 operation is initiated by
→ loading contents of PC into MAR &
→ sending a Read request to memory.
The Select signal is set to Select4, which causes the Mux to select constant 4. This value
is added to operand at input B (PC’s content), and the result is stored in Z.
2. Updated value in Z is moved to PC. This completes the PC increment operation and
PC will now point to next instruction.
3. Fetched instruction is moved into MDR and then to IR. The step 1 through 3
constitutes the Fetch Phase.
At the beginning of step 4, the instruction decoder interprets the contents of the IR. This
enables the control circuitry to activate the control-signals for steps 4 through 7.
The step 4 through 7 constitutes the Execution Phase.
4.Contents of R3 are loaded into MAR & a memory read signal is issued.
5.Contents of R1 are transferred to Y to prepare for addition.
6. When Read operation is completed, memory-operand is available in MDR, and the
addition is performed.
7.Sum is stored in Z, then transferred to R1.The End signal causes a new instruction
fetch cycle to begin by returning to step1. 21
BRANCHING INSTRUCTIONS
Control sequence for an unconditional branch instruction is as follows:
Step 1-3--> The processing starts & the fetch phase ends in step3.
Step 4--> The offset-value is extracted from IR by instruction-decoding circuit.
Since the updated value of PC is already available in register Y, the offset X is gated
onto the bus, and an addition operation is performed.
Step 5--> the result, which is the branch-address, is loaded into the PC.
The branch instruction loads the branch target address in PC so that PC will fetch the
next instruction from the branch target address.
The offset X is usually the difference between the branch target-address and the address
immediately following the branch instruction.

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In case of conditional branch,
we have to check the status of the condition-codes before loading a new
value into the PC.
Eg. Offset-field-of-IRout, Add, Zin,
If N=0 then End
If N=0, processor returns to step1 immediately after step4.
If N=1, step5 is performed to load a new value into PC.

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MULTIPLE BUS ORGANIZATION

Disadvantage of Single-bus organization:

Only one data-word can be transferred over the bus in a clock cycle.
This increases the steps required to complete the execution of the
instruction
Solution: To reduce the number of steps, most processors provide
multiple internal-paths.
Multiple paths enable several transfers to take place in parallel.

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MULTIPLE BUS ORGANIZATION
Here,three buses can be used to connect
registers and the ALU of the processor.
All general-purpose registers are
grouped into a single block called the
Register File.
Register-file has 3 ports:
Two output-ports allow the contents of 2
different registers to be simultaneously
placed on buses A & B.
Third input-port allows data on bus C to
be loaded into a third register during the
same clock-cycle.
Buses A and B are used to transfer
source-operands to A & B inputs of ALU.
The result is transferred to destination
over bus C.
Incrementer Unit is used to increment
PC by 4. 25
Instruction execution :
Step 1--> Contents of PC are
passed through ALU using R=B control-
signal
loaded into MAR to start memory Read
operation. At the same time, PC is
incremented by 4.

Step2--> Processor waits for MFC signal

from memory.

Step3--> Processor loads requested-data

into MDR, and then transfers them to IR.

Step4--> The instruction is decoded and add

operation takes place in a single step.
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HARDWIRED CONTROL

To execute instructions, the processor must have some means of

generating the control signals needed in the proper sequence.

Two categories:
-> Hardwired control
-> Micro programmed control

Hardwired control :
The control-signals are generated by using logic circuits such as gates,
flip-flops, decoders etc.
combinational-circuit that generates required control-outputs depending
on state of all its inputs.
Hardwired system can operate at high speed; but with little flexibility.
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Control Unit Organization
Instruction Decoder
 It decodes the instruction loaded in
the IR.
 If IR is an 8 bit register, then
instruction decoder generates 28(256
lines),One for each instruction.
 It consists of a separate output-lines
INS1 through INSm for each machine
instruction.
 According to code in the IR, one of
the output-lines INS1 through INSm is
set to 1,and all other lines are set to 0.
 Step-Decoder provides a separate
signal line for each step in the control
sequence. 28
Encoder
It gets the input from instruction decoder, step decoder, external inputs
and condition codes.
It uses all these inputs to generate individual control-signals: Y in, PCout,
Add, End and so on.
For example in the Figure
, Zin=T1+T6.ADD+T4.BR
This signal is asserted during time-slot T1 for all instructions.
during T6 for an Add instruction.
during T4 for unconditional branch instruction

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Control Unit Organization

When RUN=1, counter is incremented by

1 at the end of every clock cycle and
When RUN=0, counter stops counting.
After execution of each instruction, end
signal is generated.
End signal resets step counter.
 Sequence of operations carried out by
this machine is determined by wiring of
logic circuits, hence the name
”Hardwired”.

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Advantage: Can operate at high speed.

Disadvantages:
Since number of instructions/control-lines is often in hundreds, the
complexity of control unit is very high.
It is costly and difficult to design.
The control unit is inflexible because it is difficult to change the design.

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MICROPROGRAMMED CONTROL
Microprogramming is a method of control unit design
Control-signals are generated by a program similar to machine language
programs.
 Micro instructions for the instruction Add (R3),R1

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MICROPROGRAMMED CONTROL
Control Word(CW) is a word whose individual bits represent various
control-signals (like Add, PCin).
Each of the control-steps in control sequence of an instruction defines a
unique combination of 1s & 0s in CW.
Individual control-words in micro routine are referred to as micro
instructions.
A sequence of CWs corresponding to control-sequence of a machine
instruction constitutes the Micro routine.
The micro routines for all instructions in the instruction-set of a
computer are stored in a special memory called the Control Store (CS).
Control-unit generates control-signals for any instruction by sequentially
reading CWs of corresponding micro routine from CS.
µPC is used to read CWs sequentially from CS. (µPC-> Micro program
Counter).
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MICROPROGRAMMED CONTROL contd…
Every time new instruction is loaded into IR, o/p of Starting
Address Generator is loaded into µPC.
Then, µPC is automatically incremented by clock, causing
successive microinstructions to be read from CS.
Hence, control-signals are delivered to various parts of
processor in correct sequence.

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MICROPROGRAMMED CONTROL contd…
Advantages
It simplifies the design of control unit.
Thus it is both, cheaper and less error prone implement.
Control functions are implemented in software rather than hardware.
The design process is orderly and systematic.
More flexible, can be changed to accommodate new system
specifications or to correct the design errors quickly and cheaply.
Complex function such as floating point arithmetic can be realized
efficiently.
Disadvantages
A micro programmed control unit is some what slower than the
hardwired control unit, because time is required to access the
microinstructions from CM.
The flexibility is achieved at some extra hardware cost due to the
control memory and its access circuitry. 35