Digital System Design

Spring in 2022

TS. Nguyen Khanh Quang

 Course Description

1. Introduction to digital system design (Aug. 28) (by Ying-Shieh Kung)

● Introduction to FPGA
● Introduction to VHDL
● Case study in controller and filter design using VHDL
2. ModelSim/Simulink co-simulation (Aug. 28) (by Hoang Than )
● Introduction to ModelSim Simulation
● Introduction to ModelSim/Simulink co-simulation
● Case study
3. FPGA implementation (…) (…)
● Introduction to Altera DE2-115 Development and Education Board
● Altera DE2-115 Board Programming
● FPGA Project Experiments

2
 A. Introduction to Case Study
of ModelSim Simulation
For ModelSim 5.7d

Spring 2022 in DUT

Refer from:
•TS. Nguyen Khanh Quang, Teaching Material, 2022.
•Volnei A. Pedroni, Circuit Design and Simulation with VHDL,
Second Edition, The MIT Press, 2010.

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1. Create a new project

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1. Create a new project

Type VHDL code here

Example

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2. Open a project

(project file)

testbench file

original VHDL code 6

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Add vhd file and testbench file

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Compile

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 library ieee; -- Terminal count decoder
Counter.vhd use ieee.std_logic_1164.all; IF (cnt = 0 and direction = '0') THEN
use Ieee.std_logic_arith.all; max_min <= '1';
use ieee.std_logic_unsigned.all; ELSIF (cnt = 255 and direction = '1') THEN
max_min <= '1';
------------------------------------------
ELSE
ENTITY counter IS max_min <= '0';
PORT( END IF;
clk, count_ena : IN BIT; END PROCESS;
clear, load, direction : IN BIT; END a;
p : IN INTEGER RANGE 0 TO 255;
max_min : OUT BIT;
qd : OUT INTEGER RANGE 0 TO 255);
END counter;
------------------------------------------
ARCHITECTURE a OF counter IS
BEGIN
PROCESS (clk, clear, load)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
BEGIN
IF (clear = '0') THEN -- Asynchrnous clear
cnt := 0;
ELSIF (load = '1' and clear = '1') THEN -- Asynchronous load
cnt := p;
ELSE
IF (clk'EVENT AND clk = '1') THEN
IF (count_ena = '1' and direction = '0') THEN
cnt := cnt - 1;
ELSIF (count_ena = '1' and direction = '1') THEN
cnt := cnt + 1;
END IF;
END IF;
END IF;
qd <= cnt;

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Counter_tb.vhd
LIBRARY ieee; BEGIN
USE ieee.std_logic_1164.all; ----- counter_1 instantiation ---------------
----------------------------------- Counter_1: counter PORT MAP (clk, counter_ena,
ENTITY counter_tb IS clear, load, direction, P, max_min, qd);
END counter_tb; ----- Stimuli generation --------------
----------------------------------------- clk <= NOT clk AFTER 40ns;
ARCHITECTURE testbench of counter_tb IS clear <= '1' AFTER 0ns;
----- counter declaration --------------- counter_ena <= '1' AFTER 0ns;
COMPONENT counter load <= '0' AFTER 0ns;
PORT ( clk, count_ena : IN BIT; direction <= '1' AFTER 0ns;
clear, load, direction : IN BIT; P <= 20 AFTER 0ns;
p : IN INTEGER RANGE 0 TO 255; END testbench;
max_min : OUT BIT;
qd : OUT INTEGER RANGE 0 TO 255);
END COMPONENT;

----- signal declaration -----------

SIGNAL clk: BIT := '0';
SIGNAL counter_ena: BIT := '0';
SIGNAL clear: BIT := '0';
SIGNAL load: BIT := '0';
SIGNAL direction: BIT := '0';
SIGNAL P : INTEGER :=0;
SIGNAL max_min : BIT;
SIGNAL qd: INTEGER;

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3. Simulation

Choose Library tab

Right click “counter_tb => Simulate

Compilation result

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 Add waveform
Choose Sim tab
Right click “counter_tb => Add => Add to Wave

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Setting the simulation time

Change the running time

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 Running

Simulation results

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 End Simulation

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 B. Introduction to
ModelSim/Simulink Co-simulation
For ModelSim 5.7d
Matlab 2008a

Fall 2016 in STUST, Taiwan

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 Introduction to ModelSim/Simulink Co-simulation

Matlab Simulink ModelSim

• To verify the functionality

of the HDL correctly match the • Chip design using HDL
system specifications (Hardware Description Languages)
• Environment for multidomain • High-level tool for designing
simulation and Model-Based high-performance DSP systems
Design for dynamic and using FPGAs
embedded systems

Co-simulate ModelSim/Simulink
y=f(x)

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 MATLAB AND MODELSIM LINKING
(For the link to work, Modelsim has to be invoked from the command prompt of
MATLAB.
For this purpose, MATLAB needs to know the location of MODELSIM )

>> configuremodelsim (Step 1)

Identify the ModelSim installation to be configured for MATLAB and Simulink

Do you want configuremodelsim to locate installed ModelSim executables [ y ] / n ? y

Select a ModelSim installation to be configured: (Step 2)

[1] C:\Modeltech_5.7d\win32 ModelSim SE 5.7d
[0] None

Select ModelSim installation to be configured: 1 (Step 3)

Previous MATLAB startup file found in this installation of ModelSim:
C:\Modeltech_5.7d\win32\..\tcl\ModelSimTclFunctionsForMATLAB.tcl
Do you want to replace this file [y]/n? y
(Step 4)
ModelSim successfully configured to be used with MATLAB and Simulink

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 MODELSIM/MATLAB SIMULINK CO-SIMULATION
1. Open ModelSim in Matlab main window to make the communication

>> configuremodelsim

Identify the ModelSim installation to be configured for MATLAB and Simulink

Do you want configuremodelsim to locate installed ModelSim executables [ y ] / n ? y

Select a ModelSim installation to be configured:

[1] C:\Modeltech_5.7d\win32 ModelSim SE 5.7d

[0] None

Select ModelSim installation to be configured: 1

Previous MATLAB startup file found in this installation of ModelSim:

C:\Modeltech_5.7d\win32\..\tcl\ModelSimTclFunctionsForMATLAB.tcl
Do you want to replace this file [y]/n? y
ModelSim successfully configured to be used with MATLAB and Simulink

>> vsim('socketsimulink',4449) (Open ModelSim)

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2. ModelSim
2.1. Create new project
- File => New => Project
- Type “counter” (any project name)

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2.2. Add vhd file

(Step 1)

(Step 2: Choose all files)

Co-simulation & Library files

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 2.3. Add new library
- File => New => Library
- Choose “a new library and a logical mapping to it
- At the library name, type “lpm”

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 2.4. Setting file properties
- Choose all files
- Right click and choose Properties
- Click tab VHDL, choose “Use 1993 Language Syntax”

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 2.4. Setting file properties (cont.)
- Choose 2 files “220models” and “220pack”
- Right click and choose Properties
- At tab VHDL, choose “lpm” in ‘Compile to library’ index

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2.5. Compile program
- Choose all files
- Right click and choose Compile => Compile All

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2.6. Simulation
- At main window, type “vsimu work.counter”
(Command’s structure: vsimu work.name_of_entity1 work. name_of_entity2)

# Reading C:/Modeltech_5.7d/tcl/vsim/pref.tcl
# do {D:/Softwares/MATLAB/R2008a/bin/tp2eb1637e_fa87_4651_9eb1_209b9189e1d8}
# Loading project counter
# Compile of 220model.vhd was successful.
# Compile of 220pack.vhd was successful.
# Compile of counter.vhd was successful.
# 3 compiles, 0 failed with no errors.
ModelSim> vsimu work.counter
# vsim -foreign {simlinkserver
{D:/Softwares/MATLAB/R2008a/toolbox/modelsim/windows32/liblfmhdls_vs05.dll} ; -socket
4449 } work.counter
# Loading C:/Modeltech_5.7d/win32/../std.standard
# Loading C:/Modeltech_5.7d/win32/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_5.7d/win32/../ieee.std_logic_arith(body)
# Loading C:/Modeltech_5.7d/win32/../ieee.std_logic_unsigned(body)
# Loading work.counter(a)
# Loading D:/Softwares/MATLAB/R2008a/toolbox/modelsim/windows32/liblfmhdls_vs05.dll

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3. Matlab
3.1. Create new model
- At main window, type “Simulink”
- At Simulink Library Browser, choose EDA Simulator Link MQ

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3.2. Setting HDL block parameters
- At tab Ports, add inputs, outputs and their parameters

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3.2. Setting HDL block parameters (cont.)
- At tab ‘Clock’, add clock and timing period

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3.2. Setting HDL block parameters (cont.)

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3.2. Setting HDL block parameters (cont.)

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 3.3. Create Model and start Co-simulation
bin 1

Display 1

clear
1 Convert clear

Constant5
qd
load (SI) bin 0001 0100
qd
0 Convert load
Display 3
Constant1

direction
1 Convert direction

Constant2

count_ ena
1 Convert count_ ena
max_ min bin 0
max_ min
Constant3
Display6
P 20 int8 P

Constant4
HDL Cosimulation HDL Cosimulation

bin 0001 0100

Display2

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3.3. Create Model and start Co-simulation (cont.)

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3.3. Create Model and start Co-simulation (cont.)

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3.3. Create Model and start Co-simulation (cont.)

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3.3. Create Model and start Co-simulation (cont.)

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3.3. Create Model and start Co-simulation (cont.)

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ModelSim/Simulink Co-simulation
Case study

- Sum of Product (SoP)

- Filter Design

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 Example-1 Sum of Product

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 Example-1 Sum of Product

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 Example-1 Sum of Product

0.2 Convert x1
bin 0000 1100 0010 0111

0.3 Convert x2
0.094940185546875

-0.1 Convert x3

fixdt(1,16,0) y -K-

0.5 Convert a1 Gain 1 Output

0: unsigned
1: signed Q format (Q0) 0.15 Convert a2

0.5 Convert a3

data length (16bits)

Sum of Product

5.9814453125015 e-005
x1

Subtract error
x2

x3
0.095
fcn y
a1
Display 1

a2

function y = fcn(x1,x2,x3,a1,a2,a3)
a3

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y=a1*x1+a2*x2+a3*x3 43
MATLAB Function
 Example-1 Sum of Product
0.2 Convert x1
bin 0000 1100 0010 0111

0.3 Convert x2
0.094940185546875

-0.1 Convert x3

y -K-

0.5 Convert a1 Gain 1 Output

0.15 Convert a2

0.5 Convert a3

Sum of Product

5.9814453125015 e-005
x1

Subtract error
x2

x3
0.095
fcn y
a1
Display 1

a2

a3

Embedded
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 Example-2 Filter Design
A second-order low-pass filter is designed with
bandwidth 5Hz and damping ratio 1.0
• The continuous transfer function of the second order low
pass filter is:

• Its fourth order low pass filter:

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 Example-2 Filter Design
After the bilinear transform with sampling time 0.01,
its discrete transfer function is

Difference equation after Q15 format: (y(n)*32768, or x(n)*32768)

Y(n)= 95486*Y(n-1) – 104366*Y(n-2) + 50692*Y(n-3) - 9234*Y(n-4) +
11*X(n) + 44*X(n-1) + 67*X(n-2) + 44*X(n-3) + 11*X(n-4)
Where x(n) are inputs and y(n) are outputs

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 Example-2 Filter Design
I. Technique description

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 Example-2 Filter Design
II. VHDL Code

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 Example-2 Filter Design

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 Example-2 Filter Design

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 Example-2 Filter Design

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 Example-2 Filter Design
III. Simulation Result (ModelSim/Simulink Co-simulation)

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 Example-2 Filter Design

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 Example-2 Filter Design

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 Example-2 Filter Design

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 Thank you for your attention

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