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The Processor - Introduction

The document describes the processor implementation of a MIPS instruction set architecture. It discusses the core MIPS instruction types, including integer, memory reference, and branch instructions. It provides a high-level view and detailed view of the major functional units involved in instruction execution, including the instruction memory, register file, ALU, data memory, program counter, and control logic. The control unit determines the flow of data between functional units based on the instruction to perform the required operation, address calculation, register write-back, or branch.

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17 views

The Processor - Introduction

The document describes the processor implementation of a MIPS instruction set architecture. It discusses the core MIPS instruction types, including integer, memory reference, and branch instructions. It provides a high-level view and detailed view of the major functional units involved in instruction execution, including the instruction memory, register file, ALU, data memory, program counter, and control logic. The control unit determines the flow of data between functional units based on the instruction to perform the required operation, address calculation, register write-back, or branch.

Uploaded by

sas21-d01-s6-cs15
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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THE PROCESSOR

INTRODUCTION
 Compiler and the instruction set architecture determine the
instruction count required for a given program
 Processor implementation determines both the clock cycle time and
the number of clock cycles per instruction
 Subset of core MIPS instruction set

 Integer arithmetic-logical instructions


 (ADD, SUB, AND,OR, and SLT (Set Less Than))
 Memory-reference instructions
 (load word (lw) and store word (sw))
 Branch instructions BEQ, and J (jump)

 The first two steps are identical:


 1. Fetch the instruction
 2. Read one or two registers
 For the load word instruction, we need to read only one register
INTRODUCTION (2)
 The simplicity and regularity of the instruction set simplifies the
implementation
 By making the execution of many of the instruction classes
similar
 Except jump, all instruction classes, use ALU after reading the
registers
 The memory-reference instructions for an address calculation
 The arithmetic-logical instructions for the operation
execution
 Branches for comparison
 After using the ALU, the actions required to complete various
instruction classes differ
 A memory-reference instruction will need to access the memory
either to read data for a load or write data for a store
 An arithmetic-logical or load instruction must write the data
INTRODUCTION (3)
 A branch instruction, may need to change the next instruction
address based on the comparison
 Otherwise, the PC should be incremented by 4 to get the address
of the next instruction
HIGH LEVEL VIEW OF MIPS
IMPLEMENTATION
 Showing the major functional units and their inter connections
 Shows most of the flow of data through the processor
 Omits two important aspects of instruction execution
 Multiplexer & control unit
 All instructions start by using the program counter
 PC supply the instruction address to the instruction memory
 The register operands specified by the fields of that instruction
are fetched
 Register operands operated on to compute
 a memory address (for a load or store),
 an arithmetic result (for an integer arithmetic-logical
instruction),
 or a compare (for a branch)
 The result from the ALU must be written to a register (AL
instruction)
 For load or store, the ALU result is used as an address to either
store a value from the registers or load a value from memory into
the registers
 The result from the ALU or memory is written back into the
register file
 Branches require the use of the ALU output to determine the next
instruction address
 The thick lines interconnecting the functional units represent
buses (consisting of multiple signals)
MIPS SUBSET IMPLEMENTATION INCLUDING
MULTIPLEXORS AND CONTROL UNIT
 A control unit has the instruction as an input
 Determine control lines for the functional units and multiplexors
 The top multiplexor (“Mux”) controls what value replaces the
PC (PC + 4 or the branch destination address)
 Controlled by AND gate with input as Zero output of the ALU
and a control signal indicating the instruction is a branch
 The middle multiplexor, to the register file, steer the output of
the ALU (in the case of an AL instruction) or the output of the
data memory (in case of a load) for writing into the register file
 Bottommost multiplexor determine whether the second ALU
input is from the registers (for an AL instruction OR a branch)
or from the offset field of the instruction (for a load or store)
 The added control lines are straightforward and determine
 The operation performed at the ALU,
 Whether the data memory should read or write,
 and whether the registers should perform a write operation

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