34B00134 FPGA 設計

FPGA Design

李明哲

Lec. 3
Feb. 20, 2023
 Modules
Verilog is both a behavioral and a structural
language
Internals of each module can be defined at four
levels of abstraction, depending on the needs of the
design
The module behaves identically with the external
environment irrespective of the level of abstraction
at which the module is described
Thus, the level of abstraction to describe a module
can be changed without any change in the
environment

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 4 Levels of Abstraction
 Behavioral or algorithmic level
This is the highest level of abstraction provided by
Verilog HDL
A module can be implemented in terms of the desired
design algorithm without concern for the hardware
implementation details
Designing at this level is very similar to C
programming
 Dataflow level
At this level, the module is designed by specifying the
data flow
The designer is aware of how data flows between
hardware registers and how the data is processed in
the design
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 4 Levels of Abstraction
Gate level
The module is implemented in terms of logic gates
and interconnections between these gates
Design at this level is similar to describing a design
in terms of a gate-level logic diagram.
Switch level
This is the lowest level of abstraction provided by
Verilog
A module can be implemented in terms of switches,
storage nodes, and the interconnections between
them
Design at this level requires knowledge of switch-
level implementation details
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 Mixed Use of 4 Levels of Abstraction
Verilog allows the designer to mix and match all
four levels of abstractions in a design
In the digital design community, the term register
transfer level (RTL) is frequently used for a Verilog
description that uses a combination of behavioral
and dataflow constructs and is acceptable to logic
synthesis tools
If a design contains four modules, Verilog allows
each of the modules to be written at a different level
of abstraction
As the design matures, most modules are replaced
with gate-level implementations

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 Mixed Use of 4 Levels of Abstraction
 Normally, the higher the level of abstraction, the more
flexible and technology independent the design
 As one goes lower toward switch-level design, the design
becomes technology-dependent and inflexible
A small modification can cause a significant number
of changes in the design
Consider the analogy with C programming and
assembly language programming
It is easier to program in a higher-level language such
as C. The program can be easily ported to any
machine
However, if you design at the assembly level, the
program is specific for that machine and cannot be
easily ported to another machine
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 Instances
A module provides a template from which you
can create actual objects
When a module is invoked, Verilog creates a
unique object from the template
Each object has its own name, variables,
parameters, and I/O interface
The process of creating objects from a module
template is called instantiation, and the objects
are called instances

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 Module Instantiation
The top-level block creates four instances from
the T-flipflop (T_FF) template
Each instance must be given a unique name

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 Module Instantiation
Each T_FF instantiates a D_FF and an inverter
gate

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 Nested Module Definitions NOT Allowed
In Verilog, it is illegal to nest modules
One module definition cannot contain another
module definition within the “module” and
“endmodule” statements
Instead, a module definition can incorporate copies
of other modules by instantiating them
It is important not to confuse module definitions and
instances of a module
Module definitions simply specify how the module
will work, its internals, and its interface
Modules must be instantiated for use in the
design
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 Example of Nested Module Definition
An illegal module T_FF is defined inside the module
definition of the ripple carry counter

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 Stimulus Block
Once a design block is completed, it must be tested
The functionality of the design block can be tested
by applying stimulus and checking results
We call such a block the stimulus block, which can
also be written in Verilog
It is good practice to keep the stimulus and design
blocks separate
The stimulus block is also commonly called a test
bench
Different test benches can be used to thoroughly test
the design block
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 Two Styles of Stimulus
Two styles of stimulus application are possible
In the first style, the stimulus block instantiates the
design block and directly drives the signals in the
design block (i.e., the stimulus block becomes the
top-level block)

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 Two Styles of Stimulus
The second style is to instantiate both the stimulus
and design blocks in a top-level dummy module
The stimulus block interacts with the design block
only through the interface

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 A Simple Design Example
To illustrate the concepts discussed in the previous
courses, let us build the complete design &
simulation of a ripple carry counter
We will define the design block and the stimulus
block
We will apply stimulus to the design block and
monitor the outputs
As we develop the Verilog models, you do not need
to understand the exact syntax of each construct at
this stage
Instead, please try to simply understand the design
process
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 Design Blocks
Let’s adopt a top-down design methodology

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 Top Level — Ripple Carry Counter
First, let’s define of the top-level design block the
ripple carry counter

module ripple_carry_counter(q, clk, reset);

output [3:0] q;
input clk, reset;
//4 instances of the module T_FF are created.
T_FF tff0(q[0],clk, reset);
T_FF tff1(q[1],q[0], reset);
T_FF tff2(q[2],q[1], reset);
T_FF tff3(q[3],q[2], reset);
endmodule

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 T_FF
Next, let’s define the module T_FF

module T_FF(q, clk, reset);

output q;
input clk, reset;
wire d;
D_FF dff0(q, d, clk, reset);
not n1(d, q); // not is a Verilog-provided primitive. case sensitive
endmodule

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 D_FF
Next, let’s define the module D_FF
// module D_FF with asynchronous reset
module D_FF(q, d, clk, reset);
output q;
input d, clk, reset;
reg q;
/* Ignore the functionality of the constructs. Concentrate on
how the design block is built in a top-down fashion*/
always @(posedge reset or negedge clk)
if (reset)
q <= 1'b0;
else
q <= d;
endmodule
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 Stimulus Block
 Now, let’s write the stimulus block to check if the ripple
carry counter design is functioning correctly
 Let’s create the waveforms shown below to test the
design
Let’s set the cycle time for “clk” to be 10 units
Make the reset signal stay up from time 0 to 15
Make the reset signal go down at time 15
Make the reset signal go up again from time 195 to
205

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 Stimulus Block
module stimulus;
reg clk;
reg reset;
wire[3:0] q;
// instantiate the design block
ripple_carry_counter r1(q, clk, reset);
/* Control the clk signal that drives the design block.
Cycle time = 10 */
initial
clk = 1'b0; //set clk to 0
always #5 clk = ~clk; //toggle clk every 5 time units

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 Stimulus Block
// Control the reset signal that drives the design block
// reset is asserted from 0 to 15 and from 195 to 205.
initial
begin
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
#20 $finish; //terminate the simulation
end
// Monitor the outputs 此控制指令在 Altera
initial Modelsim 不一定有
$monitor($time, " Output q = %d", q); 用 可以改看
endmodule waveform
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 Stimulus Block
According to your preference, you can choose to
put the D_FF, T_FF, ripple_carry_counter
modules in separate Verilog files
put the sub-modules all together with the
stimulus block

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 Quartus II
You may download the free version from Intel
Website (to use the free version, connection to
the internet is needed)
https://www.intel.com/content/www/us/en/
software-kit/666221/intel-quartus-ii-web-
edition-design-software-version-13-1-for-
windows.html
You can try to explore using Quartus II to run
the Verilog example
We’ll start using the Quartus II next time

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 Verilog Syntax
Lexical conventions in Verilog are similar to C in
the sense that it contains a stream of tokens
A lexical token may consist of one or more
characters and tokens can be comments,
keywords, numbers, strings or white space
All lines should be terminated by a semi-colon
“;”
Verilog is case-sensitive, so “var_a” and “var_A”
are different

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 Comments
Single line comment
starts with “//”
everything after “//” to the end of the line is
regarded as a comment
Multiple-line comment
starts with “/*” and ends with “*/”
cannot be nested
However, single line comments can be nested in a
multiple line comment

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 Comments

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 White space
White space is a term used to represent the
characters for spaces, tabs, newlines and
formfeeds, and is usually ignored by Verilog
except when it separates tokens.

However blanks(spaces) and tabs (from TAB

key) are not ignored in strings

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 Operators ( 運算子 )
There are three types of operators
Unary
Unary operators shall appear to the left of
their operand

Binary
Binary operators shall appear between their
operands ( 運算元 )

ternary or conditional
Conditional operators have two separate
operators that separate three operands

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 Number Specification
By default, Verilog simulators treat numbers as
decimals
23456 // This is a decimal number by default
There are two types of number specification in
Verilog
Sized
Unsized

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 Sized Numbers
Sized numbers are represented as shown below,
where size is written only in decimal to specify the
number of bits in the number

base_format can be either decimal (“d” or “D”),

hexadecimal (“h” or “H”) and octal (“o” or “O”)
and specifies what base the number part
represents
number is specified as consecutive digits from 0,
1, 2 ... 9 for decimal base format and 0, 1, 2 .. 9, a,
b, c, d, e, f for hexadecimal
Uppercase letters are legal for number
specification when the base format is
hexadecimal
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 Sized Numbers
4’b1111; // This is a 4-bit binary number
12’habc; // This is a 12-bit hexadecimal number
16’d255; // This is a 16-bit decimal number
32’hFACE_47B2; // Underscore (_) can be used
to separate 16 bit numbers for readability
An underscore character “_” is allowed
anywhere in a number except the first character
Underscore characters are allowed only to
improve readability of numbers and are ignored
by Verilog
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 Unsized Numbers
Numbers without a base_format specification are
decimal numbers by default
Numbers without a size specification have a default
number of bits depending on the type of simulator
and machine
 23456 // This is a decimal number by default
(whether 32-bit or 64-bit depends on the simulator
and machine)
’hc3 // This is a hexadecimal number(whether 32-
bit or 64-bit depends on the simulator and machine)
 ’o21; // This is an octal number (whether 32-bit or
64-bit depends on the simulator and machine)
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 X or Z values
 Verilog uses “x” to denote an unknown value, and uses
“z” to denote a high impedance value
 An x or z sets four bits for a number in the hexadecimal
base, three bits for a number in the octal base, and one
bit for a number in the binary base
 If the most significant bit (MSB) of a number is 0, x, or z,
the number is automatically extended to fill bits at higher
digits, respectively, with 0, x, or z
 Examples:
 12’h13x // This is a 12-bit hex number; 4 least significant
bits unknown
 6’hx // This is a 6-bit hex number
 32’bz // This is a 32-bit high impedance number
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 Negative Numbers
Negative numbers can be specified by putting a
minus sign before the size for a constant number
Size constants are always positive
It is illegal to have a minus sign between <base
format> and <number>
Examples
-8’d3 // a negative number stored as 2’s
complement of -3
4’d-2 // illegal specification

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 Negative Numbers
Negative numbers are represented as 2’s
complement internally in Verilog
When necessary, try to use negative numbers
with integer type or real type
Negative numbers using the format of
<sss>’<base><nnn> will be treated in 2’s
complement format and hence is likely to cause
unexpected problems

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 Strings
A string is a sequence of characters enclosed in a
double quote " "
A string cannot be split into multiple lines
Every character in a string is treated as 1-byte
ASCII value
Examples
“Hello Verilog World” // is a string
“a / b” // is a string

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Lec. 3 finished