Unit OS5: Memory Management

5.1. Memory Management for Multiprogramming

Windows Operating System Internals - by David A. Solomon and Mark E. Russinovich with Andreas Polze
Copyright Notice
© 2000-2005 David A. Solomon and Mark Russinovich

These materials are part of the Windows Operating

System Internals Curriculum Development Kit,
developed by David A. Solomon and Mark E.
Russinovich with Andreas Polze
Microsoft has licensed these materials from David
Solomon Expert Seminars, Inc. for distribution to
academic organizations solely for use in academic
environments (and not for commercial use)

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Roadmap for Section 5.1.

Memory Management Principles

Logical vs Physical Address Space
Swapping vs Segmentation
Paging

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Memory Management Principles

Memory is central to the operation of a modern

computer system
Memory is a large array of words/bytes
CPU fetches instructions from memory
according to the value of the program counter
Instructions may cause additional loading from
and storing to specific memory addresses

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Address Binding
Source
program

Addresses in source other Compiler or Compile

programs are symbolic object assembler time
modules
Compiler binds symbolic to Object
relocatable addresses module

Linkage editor/loader binds System Linkage

relocatable addresses to libraries editor load
time
absolute addresses Load
module
Binding can be done at any step:
dynamically loader
i.e., compiler may generate loaded
absolute code (as for MS- system In-memory execution
libraries
DOS .COM programs) binary time
memory (run time)
image
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Logical vs. Physical
Address Space
Address generated by CPU is called a logical address
Memory unit deals with physical addresses
compile-time and load-time address-binding:
Logical and physical addresses are identical
execution-time address-binding:
Logical addresses are different from physical addresses
Logical addresses are also called virtual addresses
Run-time mapping from virtual to physical addresses is done by
Memory Management Unit (MMU) – a hardware device
The concept of a logical address space that is bound to a
different physical address space is central to Memory
Management!

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Memory-Management Unit (MMU)

Hardware device that maps virtual to physical address.

The MMU is part of the processor
Re-programming the MMU is a privileged operation that can
only be performed in privileged (kernel) mode

In MMU scheme, the value in the relocation register is

added to every address generated by a user process at
the time it is sent to memory.
The user program deals with logical addresses; it never sees
the real physical addresses.

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Dynamic relocation using a
relocation register

relocation
register
7000
memory
CPU logical + physical
address address
642 7642
MMU

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Dynamic Loading

A routine is not loaded until it is called

All routines are kept on disk in a relocatable load format
When a routine calls another routine:
It checks, whether the other routine has been loaded
If not, it calls the relocatable linking loader to load desired
routine
Loader updates program‘s address tables to reflect change
Control is passed to newly loaded routine
Better memory-space utilization
Unused routines are never loaded
No special OS support required

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Dynamic Linking

Similar to dynamic loading:

Rather than loading being postponed until run time,
linking is postponed
Dynamic libraries are not statically attached to
a program‘s object modules (only a small stub is attached)
The stub indicates how to call (load) the appropriate library
routine
All programs may use the same copy of a library (code)
(shared libraries - .DLLs)
Dynamic linking requires operating system support
OS is the only instance which may locate a library in another
process‘s address space

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Memory Allocation Schemes
Main memory must accommodate OS + user processes
OS needs to be protected from changes by user processes
User processes must be protected from each other
Single partition allocation:
User processes occupy a single memory partition
Protection can be implemented by limit and relocation register
(OS in low memory, user processes in high memory, see below)

limit relocation
register register

logical yes physical memory

CPU < +
address address
no
OS
trap, addressing error

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Memory Allocation Schemes (contd.)
Multiple-Partition Allocation
Multiple processes should reside in memory simultaneously
Memory can be divided in multiple partitions (fixed vs. variable size)
Problem: What is the optimal partition size?
Dynamic storage allocation problem
Multiple partitions with holes in between
Memory requests are satisfied from the set of holes
Which hole to select?
First-fit: allocate the first hole that is big enough
Best-fit: allocate the smallest hole that is big enough
Worst-fit: allocate the largest hole (produces largest leftover hole)
First-fit & best-fit are better than worst-fit (time & storage-wise)
First-fit is generally faster than best-fit

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Overlays

Size of program and data Example:

may exceed size of memory multi-pass compiler

Concept: Symbol
table
Separate program in modules
Common
Load modules alternatively Pass 1 routines
Overlay driver locates Overlay
modules on disk driver

Overlay modules are kept as

absolute memory images Pass 2

Compiler support required

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Swapping
In a multiprogramming environment:
Processes can temporarily be
swapped out of memory to backing Main memory
store in order to allow for execution of
other processes Operating
system Backing store
On the basis of physical addresses:
Then, processes will be swapped in
into same memory space that they
occupied previously Swap Process
out P1
On the basis of logical addresses: User
What current OSes call swapping is space
Swap Process
rather paging out whole processes. in P2
Then, processes can be swapped in
at arbitrary physical addresses.

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Segmentation
What is the programmer‘s view of memory?
Collection of variable-sized segments (text, data, stack, subroutines,..)
No necessary ordering among segments
Logical address: <segment-number, offset>
Hardware:
Segment table containing base address and limit for each segment

Segment
s
table
limit base
Physical
CPU s d memory
yes
< +
no Trap, addressing error

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Fragmentation

External Fragmentation – total memory space exists to satisfy a

request, but it is not contiguous.
Internal Fragmentation – allocated memory may be slightly larger
than requested memory; this size difference is memory internal to a
partition, but not being used.
Reduce external fragmentation by compaction
Shuffle memory contents to place all free memory together in one
large block.
Compaction is possible only if relocation is dynamic, and is done at
execution time.
I/O problem
Latch job in memory while it is involved in I/O.
Do I/O only into OS buffers.

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Paging

Dynamic storage allocation algorithms for varying-sized

chunks of memory may lead to fragmentation
Solutions:
Compaction – dynamic relocation of processes
Noncontiguous allocation of process memory in
equally sized pages (this avoids the memory fitting
problem)

Paging breaks physical memory into fixed-sized blocks

(called frames)
Logical memory is broken into pages (of the same size)

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Paging: Basic Method

When a process is executed, its pages are loaded into

any available frames from backing store (disk)
Hardware support for paging consists of a page table
Logical addresses consist of page number and offset

CPU p d f d
Logical Physical
address address Physical
p memory
offset
Page number Page frames
are typically
2-4 kb
Page table

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Paging Example
frame
number

0
1 Page 1
Page 0 4
0 2
Page 1 1 1
3 Page 3
Page 2 2 6
4 Page 0
Page 3 3 3
5
page
logical Page 2
table 6
memory
7

physical
memory

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 Free Frames
7 Free frame list frame 7
7, 8, 10, 11,13, 16 number
8 8 Page 1
9 9
Process creation
10 10
0 11
11 11 Page 0
1 8
12 12
2 16
13 13 13 Page 3
3
14 14
New process
15 page table 15
16 16 Page 2
Free frame list
17 7, 10 17

physical
After allocation
Before allocation
memory
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Paging: Hardware Support
Every memory access requires access to page table
Page table should be implemented in hardware
Page tables exist on a per-user process basis
Small page tables can be just a set of registers
Problem: size of physical memory, # of processes
Page tables should be kept in memory
Only base address of page table is kept in a special register
Problem: speed of memory accesses
Translation look-aside buffers (TLBs)
Associative registers store recently used page table entries
TLBs are fast, expensive, small: 8..2048 entries
TLB must be flushed on process context switches
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Associative Memory

Associative memory – parallel search

Page # Frame #

Address translation (A´, A´´)

If A´ is in associative register, get frame # out.
Otherwise get frame # from page table in memory

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Paging Hardware With TLB

CPU p d f d
Logical Physical
address TLB hit address

offset Page # Frame #

Page number
TLB
Physical
memory

p TLB miss

Page table

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Effective Access Time with TLB

Associative Lookup in TLB =  time unit

Assume memory cycle time is 1 microsecond
Hit ratio – percentage of times that a page number is
found in the associative registers;
ratio related to number of associative registers.
Let us assume a hit ratio = 

Effective Access Time (EAT)

EAT = (1 + )  + (2 + )(1 – )
=2+–

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Memory Protection

Memory protection implemented by associating control

bits with each frame
Isolation of processes in main memory

Valid-invalid bit attached to each entry in the page table:

“valid” indicates that the associated page is in the
process’ logical address space, and is thus a legal
page
“invalid” indicates that the page is not in the
process’ logical address space

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Valid (v) or Invalid (i) Bit in a Page
frame
Table number

0
1 Page 1
Page 0 4 v
0 2
Page 1 1 1 v
3 Page 3
Page 2 2 6 v
4 Page 0
Page 3 3 3 v
4 i 5
logical i Page 2
5 6
memory
page
7
table
physical
Invalid pages may be paged out memory

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Page Table Structure

Hierarchical Paging

Hashed Page Tables

Inverted Page Tables

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Hierarchical Page Tables

Break up the logical address space into multiple

page tables

A simple technique is a two-level page table

Used with 32-bit CPUs

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Two-Level Paging Example

A logical address (on 32-bit machine with 4K page size)

is divided into:
a page number consisting of 20 bits.
a page offset consisting of 12 bits.
Since the page table is paged, the page number is
further divided into:
a 10-bit page number page number page offset
a 10-bit page offset pi p2 d
Thus, a logical address is as follows: 1 1 1
0 0 2

where pi is an index into the outer page table, and p2 is the

displacement within the page of the outer page table

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Two-Level Page-Table Scheme

outer page table

(page directory)
…

page tables
memory
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Address-Translation Scheme

Address-translation scheme for a two-level 32-

bit paging architecture
page number page offset
p1 p2 d
1 1 1
0 0 2
p1 Main
p2 memory
page
directory

page
table

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Hashed Page Tables

Common in address spaces > 32 bits

IA64 supports hashed page tables

The virtual page number is hashed into a page table.

This page table contains a chain of elements hashing to
the same location

Virtual page numbers are compared in this chain

searching for a match. If a match is found, the
corresponding physical frame is extracted

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Hashed Page Table

CPU p d f d
Logical Physical
address address Physical
memory
offset
Page number

hash p f q r
function
Page table

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Inverted Page Table

One entry for each real page of memory

Entry consists of the virtual address of the page
stored in that real memory location, with
information about the process that owns that
page
Decreases memory needed to store each page
table, but increases time needed to search the
table when a page reference occurs
Use hash table to limit the search to one — or at
most a few — page-table entries

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 Inverted Page Table Architecture

CPU pid p d f d
Logical Physical
address address Physical
memory
offset
Page number
Process ID

search pid p
Page table

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Shared Pages

Shared code
One copy of read-only (reentrant) code shared among
processes (i.e., text editors, compilers, window systems)
Shared code must appear in same location in the logical
address space of all processes

Private code and data

Each process keeps a separate copy of the code and data
The pages for the private code and data can appear anywhere
in the logical address space

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Shared Pages Example frame
Process 1
number
Process 1 page table
virtual memory 0
cpp 1 cpp
1
cc1 2
4
cc2 3
11
data1 4 cc1
7
5
Process 2 Process 2 page table 6
virtual memory
7 data1
cpp 1 8 data2
cc1 4 9
cc2 11 10
data2 8 cc2
11
memory

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Segmentation with Paging
- paged segmentation on the GE 645 (Multics)
The innovative MULTICS operating system introduced:
Logical addresses: 18-bit segment no, 16-bit offset
(relatively) small number of 64k segments
To eliminate fragmentation, segments are paged
A separate page table exists for each segment
physical
s d d memory
logical address yes
>= p d‘
no
+ segment page-table
length base Trap

+ f f d‘
segment table segment table
physical address
base register
page table for segment s
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 selector offset Intel logical

selector
Address
Intel 30386
s
limit base
descriptor
table Address Translation
offset
+

31 22 21 12 11 0 Physical Address
The Intel 386
Intel Linear
10 10 12 uses
Address
segmentation
operand with paging
PTE 4 Kb page for memory
4Kb PDE 4kb page management
frame
with a two-
Page table 22 bit operand
1024 entries offset level paging
4Mb PDE 4 Mb page
4MB page frame scheme.

Page directory
1024x4byte entries
(one per process)
cr 3 Physical Memory
Physical address
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Summary
In a multiprogrammed OS, every memory address
generated by the CPU must be checked for legality and
possibly mapped to a physical address
Checking cannot be implemented (efficiently) in software
Hardware support is essential
A pair of registers is sufficient for single/multiple partition
schemes
Paging/segmentation need mapping tables to define address maps
Paging and segmentation can be fast
Tables have to be implemented in fast registers (Problem: size)
Set of associative registers (TLB) may reduce performance
degradation if tables are kept in memory
Most modern OS combine paging and segmentation
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Further Reading

Abraham Silberschatz, Peter B. Galvin,

Operating System Concepts, John Wiley &
Sons, 6th Ed., 2003;
Chapter 9 - Memory Management
Chapter 10 - Virtual Memory

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