Lecture # 2 & 3

(Computer Organization
and Assembly Language)

BSCS 3rd
Registers

BSCS 3rd
Internal structure and basic operation of
microprocessor

Address bus
ALU Register
Section
Data bus

Control and timing

section Control bus

Block diagram of a microprocessor

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 Arithmetic and logic unit (ALU)
• The component that performs the arithmetic and logical
operations
• the most important components in a microprocessor, and is
typically the part of the processor that is designed first.
• able to perform the basic logical operations (AND, OR), including
the addition operation.
• The inclusion of inverters on the inputs enables the same ALU
hardware to perform the subtraction operation (adding an
inverted operand), and the operations NAND and NOR.

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Internal structure of ALU

2 bits of ALU 4 bits of ALU

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Control unit

• The circuitry that controls the flow of information through the

processor, and coordinates the activities of the other units within it.
• In a way, it is the "brain within the brain", as it controls what
happens inside the processor, which in turn controls the rest of the
PC.
• On a regular processor, the control unit performs the tasks of
fetching, decoding, managing execution and then storing results.

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Internal structure of control unit

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CPU Registers
Register
 Working of Registers:
• When we provide the system with input, that input is stored in registers, and
when the system returns results after processing, those results are also drawn
from the registers. so that the CPU can use them to process the data that the
user provides.
• Registers are performed based on three operations:
• Fetch: The Fetch Operation is used to retrieve user-provided instructions that
have been stored in the main memory. Registers are used to fetch these
instructions.
• Decode: The Decode Operation is used to interpret the Instructions, which
means that the CPU will determine which Operation has to be carried out on
the Instructions after the Instructions have been decoded.
• Execute: The CPU manages the Execute Operation. The results that the CPU
generates are then stored in the memory before being presented on the user
screen.

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Types
General
purpose
registers
iAPX 88 Registers (16-bit)

General Purpose

AX
BX
CX
DX

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iAPX 88 Registers (16-bit)

General Purpose

16-bit

AX
AH AL
8-bit 8-bit

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iAPX 88 Registers (16-bit)

General Purpose

16-bit

BX
BH BL
8-bit 8-bit

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 General Registers

General Registers (AX, BX, CX, and DX) The registers AX, BX, CX, and DX behave
as general purpose registers in Intel architecture and do some specific functions
in addition to it.
X in their names stand for extended meaning 16bit registers.
For example AX means we are referring to the extended 16bit “A” register.
Its upper and lower byte are separately accessible as AH (A high byte) and AL
(A low byte).
All general purpose registers can be accessed as one 16bit register or as two
8bit registers.
The two registers AH and AL are part of the big whole AX. Any change in AH or
AL is reflected in AX as well. AX is a composite or extended register formed by
gluing together the two parts AH and AL.

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iAPX 88 Registers (16-bit)

General Purpose

• AX A Accumulator Register
• BX B Base Register
• CX C Counter Register
• DX D Destination Register

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 General Registers

The A of AX stands for Accumulator. Even though all general purpose

registers can act as accumulator in most instructions there are some
specific variations which can only work on AX which is why it is named the
accumulator.
The B of BX stands for Base because of its role in memory addressing as
discussed next.
The C of CX stands for Counter as there are certain instructions that work
with an automatic count in the CX register.
The D of DX stands for Destination as it acts as the destination in I/O
operations.
The A, B, C, and D are in letter sequence as well as depict some special
functionality of the register.

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03/07/24 21
Data registers

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Types
Accumulator
register
Base
Register
Counter
Register
Data
Register
iAPX 88 Registers (16-bit)

Pointer / Index / Base

SI
DI

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iAPX 88 Registers (16-bit)

Pointer Register
The pointer registers are 32-bit EIP, ESP, and EBP registers and
corresponding 16-bit right portions IP, SP, and BP. There are three
categories of pointer registers −
• IP IP Instruction Pointer
• SP SP Stack Pointer
• BP BP Base Pointer

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Instruction Pointer (IP) This is the special register containing the address of the
next instruction to be executed.
The 16-bit IP register stores the offset address of the next instruction to be
executed. IP in association with the CS register (as CS:IP) gives the complete
address of the current instruction in the code segment.
No mathematics or memory access can be done through this register.
It is out of our direct control and is automatically used. Playing with it is dangerous
and needs special care.
Stack Pointer (SP) It is a memory pointer and is used indirectly by a set of
instructions. This register will be explored in the discussion of the system stack.
The 16-bit SP register provides the offset value within the program stack. SP in
association with the SS register (SS:SP) refers to be current position of data or
address within the program stack.
.

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• Base Pointer (BP) It is also a memory pointer containing the address
in a special area of memory called the stack and will be explored
alongside SP in the discussion of the stack
• The 16-bit BP register mainly helps in referencing the parameter
variables passed to a subroutine. The address in SS register is
combined with the offset in BP to get the location of the parameter.
BP can also be combined with DI and SI as base register for special
addressing.

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03/07/24 32
Index Registers

• The 32-bit index registers, ESI and EDI, and their 16-bit rightmost
portions. SI and DI, are used for indexed addressing and sometimes
used in addition and subtraction. There are two sets of index
pointers

• Source Index (SI) − It is used as source index for string operations.

• Destination Index (DI) − It is used as destination index for string
operations.

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 Index REGISTER

Index Registers (SI and DI) SI and DI stand for source index and destination index
respectively.
These are the index registers of the Intel architecture which hold address of data
and used in memory access.
Being an open and flexible architecture, Intel allows many mathematical and
logical operations on these registers as well like the general registers.
The source and destination are named because of their indirect functionality as
the source or the destination in a special class of instructions called the string
instructions.
However their use is not at all restricted to string instructions. SI and DI are
16bit and cannot be used as 8bit register pairs like AX, BX, CX, and DX.

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3.Index registers: The 16-bit rightmost bits of the 32-bit ESI and EDI index
registers. SI and DI are sometimes employed in addition and sometimes in
subtraction as well as for indexed addressing.
• SI: This source index register is used to identify memory addresses in the data
segment that DS is addressing. Therefore, it is simple to access successive
memory locations when we increment the contents of SI. It has a 16-bit size.
Relative to the data segment, it has an offset.
•DI: The function of this destination index register is identical to that of SI.
String operations are a subclass of instructions that employ DI to access the
memory addresses specified by ES. It is generally used as a Destination index for
string operations.
•Source Index (SI) − It is used as source index for string
operations.
•Destination Index (DI) − It is used as destination index for string
operations.

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Special purpose Registers
Segment Registers :

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Segment

• CS CS Code Segment

• DS DS Data Segment
• SS SS Stack Segment
• ES ES Extra Segment

Segment Registers (CS, DS, SS, and ES) The code segment register, data
segment register, stack segment register, and the extra segment
register are special registers related to the Intel segmented memory
model and will be discussed later.

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Segment Registers

• Segments are specific areas defined in a program for containing data,

code and stack. There are three main segments −
• Code Segment − It contains all the instructions to be executed. A 16-
bit Code Segment register or CS register stores the starting address
of the code segment.
• Data Segment − It contains data, constants and work areas. A 16-bit
Data Segment register or DS register stores the starting address of
the data segment.
• Stack Segment − It contains data and return addresses of procedures
or subroutines. It is implemented as a 'stack' data structure. The
Stack Segment register or SS register stores the starting address of
the stack.
• Apart from the DS, CS and SS registers, there are other extra segment
registers - ES (extra segment), FS and GS, which provide additional
segments for storing data.

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03/07/24 42
• SS (Stack Segment register): A 16-bit register called a stack segment holds the
address of a 64KB segment with a software stack. The CPU by default believes
that the stack segment contains all information referred to by the stack pointer
(SP) and base pointer (BP) registers. POP instruction allows for direct
modification of the SS register.
• ES (Extra Segment register): A 16-bit register called extra segment holds the
address of a 64KB segment, typically holding program data. In string
manipulation instructions, the CPU defaults to assuming that the DI register
refers to the ES segment. POP and LES commands can be used to directly update
the ES register.
• FS (File Segment register): FS registers don’t have a purpose that is
predetermined by the CPU; instead, the OS that runs them gives them a purpose.
On Windows processes, FS is used to point to the thread information block (TIB).

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• GS (Graphics Segment register): The GS register is used in Windows 64-
bit to point to operating system-defined structures. OS kernels frequently
use GS to access thread-specific memory. The GS register is employed by
Windows to control thread-specific memory. In order to access CPU-
specific memory, the Linux kernel employs GS. A pointer to a thread local
storage, or TLS, is frequently used as GS.
• IP (Instruction Pointer register): The registers CS and IP are used by the
8086 to access instructions. The segment number of the following
instruction is stored in the CS register, while the offset is stored in the IP
register. Every time an instruction is executed, IP is modified to point to
the upcoming instruction. The IP cannot be directly modified by an
instruction, unlike other registers; an instruction may not have the IP as its
operand.

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 • Flag register: The status register for an x86 CPU houses its current
state, and it is called the FLAGS register. The flag bits’ size and
significance vary depending on the architecture. It often includes
information about current CPU operation limitations as well as the
outcome of mathematical operations. Some of these limitations
might forbid the execution of a particular class of “privileged”
instructions and stop some interrupts from triggering. Other status
flags may override memory mapping and specify the response the
CPU should have in the event of an arithmetic overrun.

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iAPX 88 Registers (16-bit)

Flag Register

- - - - O D I T S Z - A - P - C

C = Carry S = Sign
Bit
P = Parity T = Trap
Flag
A= Auxiliary Carry I = Interrupt
Flag
Z= Zero Bit D=
Direction Flag
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• The common flag bits are:
• Overflow Flag (OF) − It indicates the overflow of a high-order bit (leftmost
bit) of data after a signed arithmetic operation.
• Direction Flag (DF) − It determines left or right direction for moving or
comparing string data. When the DF value is 0, the string operation takes
left-to-right direction and when the value is set to 1, the string operation
takes right-to-left direction.
• Interrupt Flag (IF) − It determines whether the external interrupts like
keyboard entry, etc., are to be ignored or processed. It disables the
external interrupt when the value is 0 and enables interrupts when set to
1.
• Trap Flag (TF) − It allows setting the operation of the processor in single-
step mode. The DEBUG program we used sets the trap flag, so we could
step through the execution one instruction at a time.

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• Sign Flag (SF) − It shows the sign of the result of an arithmetic operation. This flag is set
according to the sign of a data item following the arithmetic operation. The sign is
indicated by the high-order of leftmost bit. A positive result clears the value of SF to 0 and
negative result sets it to 1.
• Zero Flag (ZF) − It indicates the result of an arithmetic or comparison operation. A
nonzero result clears the zero flag to 0, and a zero result sets it to 1.
• Auxiliary Carry Flag (AF) − It contains the carry from bit 3 to bit 4 following an arithmetic
operation; used for specialized arithmetic. The AF is set when a 1-byte arithmetic
operation causes a carry from bit 3 into bit 4.
• Now let us consider the addition of any two 8-bit (2-hex digit) numbers, a carry
may be generated when we add the LS hex digits of the two numbers. Such a
carry is called intermediate carry also known as half carry, or auxiliary carry (AC).
Intel prefers to call it AC. In the above Example 1, AC was not generated but in
Example 2, AC is generated.
• Carry Flag (CF) − It contains the carry of 0 or 1 from a high-order bit (leftmost) after an
arithmetic operation. It also stores the contents of last bit of a shift or rotate operation
• Parity Flag (PF) − It indicates the total number of 1-bits in the result obtained from an
arithmetic operation. An even number of 1-bits clears the parity flag to 0 and an odd
number of 1-bits sets the parity flag to 1.

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• Flags Register
• The flags register as previously discussed is not meaningful as a unit
• rather it is bit wise significant and accordingly each bit is named
separately.
• The bits not named are unused. The Intel FLAGS register has its bits
• organized as follows:

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Condition code register (CCR)

• an 8 bit register used to store the status of CPU, such as carry, zero,
overflow and half carry.

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Flag Name Description

Z Zero flag Indicates that the result of a mathematical or logical operation was zero.

Indicates that the result of an operation produced an answer greater than

C Carry flag the number of available bits. (This flag may also be set before a mathematical
operation as an extra operand to certain instructions, e.g. "add with carry".)

Masks the XIRQ request when set. It is set by the hardware and cleared by the
X Extend flag
software as well is set by unmaskable XIRQ.

Indicates that the result of a mathematical operation is negative. In some

processors, the N and S flags have different meanings: the S flag indicates
N Negative/ Sign flag
whether a subtraction or addition has taken place, whereas the N flag
indicates whether the last operation result is positive or negative.

Indicates that the result of an operation has overflowed according to the

V Overflow Flag
CPU's word representation, similar to the carry flag but for signed operations.

Interrupts can be enabled or disabled by respectively setting or clearing this

I interrupts flag. Modifying this flag may be restricted to programs executing in
supervisor mode

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Memory Address Registers (MAR):
Memory Buffer Registers (MbR):
Program
Counter
(PC)
Instruction Register (IR):

It is the register which holds the instruction which is currently been

executed.
Stack
pointer
register
 Register sets
• The register section/array consists completely of circuitry used to
temporarily store data or program codes until they are sent to
the ALU or to the control section or to memory.

• The number of registers are different for any particular CPU and
the more register a CPU have will result in easier programming
tasks.

• Registers are normally measured by the number of bits they can

hold, for example, an "8-bit register" or a "32-bit register".

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Register in motorola 68000
microprocessor
31 16 15 8 7 0
D0
D1
D2
D3 DATA REGISTERS
D4
D5
D6
D7
31 16 15 8 7 0
A0
A1
A2
A3 ADDRESS REGISTERS
A4
A5
A6
A7

USER STACK POINTER

A7 STACK POINTER
SUPERVISOR STACK POINTER

PC PROGRAM CONTER
15 8 7 0
SYSTEM BYTE USER VYTE SR STATUS REGISTER
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accumulator

• a register in which intermediate arithmetic and logic results are

stored.
• example for accumulator use is summing a list of numbers.
• The accumulator is initially set to zero, then each number in turn is added to
the value in the accumulator.
• Only when all numbers have been added is the result held in the
accumulator written to main memory or to another, non-accumulator, CPU
register.

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Program counter (PC)

• a 16 bit register, used to store the next address of

the operation code to be fetched by the CPU.
• Not much use in programming, but as an indicator
to user only.
• Purpose of PC in a Microprocessor
• to store address of tos (top of stack)
• to store address of next instruction to be
executed.
• count the number of instructions.
• to store base address of the stack.
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Internal structure of PC

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Stack pointer (SP)

• The stack is configured as a data structure that

grows downward from high memory to low
memory.
• At any given time, the SP holds the 16-bit address of
the next free location in the stack.
• The stack acts like any other stack when there is a
subroutine call or on an interrupt. ie. pushing the
return address on a jump, and retrieving it after the
operation is complete to come back to its original
location.

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 instruction set
• The language to command a computer architecture is comprised of
instructions and the vocabulary of that language is called the instruction set.
• The only way computers can represent information is based on high or low
electric signals, i.e., transistors (electric switches) being turned on or off.
• Being limited to those 2 alternatives, we represent information in computers
using bits (binary digits), which can have one of two values: 0 or 1.

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Program Control Instructions
Instruction Set Architecture

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• Addition with carry (ADC)
• An addition with carry (ADC) instruction adds the bit in the carry flag (C)
to the operand data.
• Example: ADC AL, AH ; AL=AL+AH+carry
• ADC DH, [BX] ; The byte content of the data segment memory
location addressed by BP add to DH with the sum stored in DH.

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 • MOV AX, 20
• MOV BX, 10
• ADD AX, BX ; AX = 30
• SUB AX, BX ; AX = 20

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07/03/24 73
07/03/24 74
Example
MOV AL, 10
MOV DL, 25
MUL DL
...
MOV DL, 0FFH ; DL= -1
MOV AL, 0BEH ; AL = -66
IMUL DL

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 The DIV/IDIV Instructions
• The division operation generates two elements - a quotient and a remainder.
• In case of multiplication, overflow does not occur because double-length registers are
used to keep the product.
• However, in case of division, overflow may occur. The processor generates an interrupt
if overflow occurs.
• The DIV (Divide) instruction is used for unsigned data and the IDIV (Integer Divide) is
used for signed data.

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 • The dividend is in an accumulator. Both the instructions can
work with 8-bit, 16-bit or 32-bit operands. The operation
affects all six status flags.
• Following section explains three cases of division with
different operand size −

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When the divisor is 1 byte −

• The dividend is assumed to be in the AX register (16 bits). After division, the
quotient goes to the AL register and the remainder goes to the AH register.

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When the divisor is 1 word −

• The dividend is assumed to be 32 bits long and in the DX:AX

registers. The high-order 16 bits are in DX and the low-order 16
bits are in AX. After division, the 16-bit quotient goes to the AX
register and the 16-bit remainder goes to the DX register.

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When the divisor is doubleword

• The dividend is assumed to be 64 bits long and in the EDX:EAX

registers. The high-order 32 bits are in EDX and the low-order 32
bits are in EAX. After division, the 32-bit quotient goes to the EAX
register and the 32-bit remainder goes to the EDX register .

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Mnemonic Description Byte

ADD A,Rn Adds the register to the accumulator 1

ADD A,direct Adds the direct byte to the accumulator 2

ADD A,@Ri Adds the indirect RAM to the accumulator 1

ADD A,#data Adds the immediate data to the accumulator 2

ADDC A,Rn Adds the register to the accumulator with a carry flag 1

ADDC A,direct Adds the direct byte to the accumulator with a carry flag 2

ADDC A,@Ri Adds the indirect RAM to the accumulator with a carry flag 1

ADDC A,#data Adds the immediate data to the accumulator with a carry flag 2

SUBB A,Rn Subtracts the register from the accumulator with a borrow 1

SUBB A,direct Subtracts the direct byte from the accumulator with a borrow 2

SUBB A,@Ri Subtracts the indirect RAM from the accumulator with a borrow 1
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Mnemonic Description Byte Cycle

SUBB A,#data Subtracts the immediate data from the accumulator with a borrow 2 2

INC A Increments the accumulator by 1 1 1

INC Rn Increments the register by 1 1 2

INC Rx Increments the direct byte by 1 2 3

INC @Ri Increments the indirect RAM by 1 1 3

DEC A Decrements the accumulator by 1 1 1

DEC Rn Decrements the register by 1 1 1

DEC Rx Decrements the direct byte by 1 1 2

DEC @Ri Decrements the indirect RAM by 1 2 3

INC DPTR Increments the Data Pointer by 1 1 3

MUL AB Multiplies A and B 1 5

DIV AB Divides A by B 1 5

DA A Decimal adjustment of the accumulator according to BCD code 1 1

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Data Transfer Instructions

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Types of Data transfer instructions :

OPCODE OPERAND EXPLANATION EXAMPLE

MOV D, S D=S MOV AX, [SI]

OPCODE OPERAND EXPLANATION EXAMPLE

XCHG D, S exchanges contents of D and S XCHG [2050], AX

OPCODE OPERAND EXPLANATION EXAMPLE

translates a byte in AL using a
XLAT none XLAT
table in the memory

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07/03/24 86
INP 0 INP
STA first 1 STA 9
INP 2 INP
STA second 3 STA 10
LDA first 4 LDA 9
OUT 5 OUT
LDA second 6 LDA 10
OUT 7 OUT
HLT 8 HLT
first DAT 9 DAT 0
second DAT 10 DAT 0

first and second are used to label a DAT instruction. DAT identifies the 10th and 11th instructions as data. The
labels therefore refer to RAM addresses 9 and 10 respectively (0-indexed counting).
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1 STA first //the accumulator contents are stored in RAM address 9 (labelled first).
07/03/24 88
07/03/24 89
Types of Program Control Instructions:

• Types of Program Control Instructions:

• There are different types of Program Control Instructions:

• 1. Compare Instruction:
• Compare instruction is specifically provided, which is similar to a
subtract instruction except the result is not stored anywhere, but
flags are set according to the result.
•

• Example:
• CMP R1, R2 ;

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07/03/24 91
• Conditional jump instructions that often followed by CMP instruction
are
• • JA (jump above)
• • JB (jump below)
• • JAE (jump above or equal)
• • JBE (jump below or equal)
• Example:
• CMP AL, 10H; compare AL against 10H JAE EEE
• ; if AL is 10H or above program jump to EEE

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Bus system

• a subsystem that transfers data between computer components

inside a computer or between computers.

4 PCI Express bus card slots (from top to bottom: x4, x16, x1 and x16),
compared to a traditional 32-bit PCI bus card slot (very bottom).

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Bus system connection

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 Data bus
• The data bus is 'bi-directional'
• data or instruction codes from memory or
input/output.are transferred into the microprocessor
• the result of an operation or computation is sent out
from the microprocessor to the memory or
input/output.
• Depending on the particular microprocessor, the
data bus can handle 8 bit or 16 bit data.

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Address bus

• The address bus is 'unidirectional', over which the microprocessor

sends an address code to the memory or input/output.
• The size (width) of the address bus is specified by the number of bits
it can handle.
• The more bits there are in the address bus, the more memory
locations a microprocessor can access.
• A 16 bit address bus is capable of addressing 65,536 (64K) addresses.

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Control bus

• The control bus is used by the microprocessor to send out or receive

timing and control signals in order to coordinate and regulate its
operation and to communicate with other devices, i.e. memory or
input/output.
• Read command
• Acks command

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Micro processor clock

• Also called clock rate, the speed at which a microprocessor executes

instructions. Every computer contains an internal clock that regulates
the rate at which instructions are executed and synchronizes all the
various computer components.
• The CPU requires a fixed number of clock ticks (or clock cycles) to
execute each instruction. The faster the clock, the more instructions the
CPU can execute per second. Clock speeds are expressed in megahertz
(MHz) or gigahertz ((GHz).
• Some microprocessors are superscalar, which means that they can
execute more than one instruction per clock cycle.
• Like CPUs, expansion buses also have clock speeds. Ideally, the CPU
clock speed and the bus clock speed should be the same so that neither
component slows down the other. In practice, the bus clock speed is
often slower than the CPU clock speed, which creates a bottleneck. This
is why new local buses, such as AGP, have been developed.

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Examples of micro processor

• Intel 8085
• Intel 8086

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 8086
 The 8086 is a 16-bit microprocessor chip
designed by Intel, which gave rise to the
x86 architecture; development work on
the 8086 design started in the spring of
1976 and the chip was introduced to the
market in the summer of 1978.
 The Intel 8088, released in 1979, was a
slightly modified chip with an external 8-
bit data bus (allowing the use of cheaper
and fewer supporting logic chips and is
notable as the processor used in the
original IBM PC.

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 8085
• The Intel 8085 is an 8-bit microprocessor
introduced by Intel in 1977. An Intel 8085AH processor.

• It was binary-compatible with the more- From 1977 to

Produced
famous Intel 8080 but required less 1990s

supporting hardware, thus allowing

simpler and less expensive microcomputer Common manufacturer(s)
•Intel and
systems to be built. several others

Max. CPU clock rate 3,5 and 6 MHz

Instruction set pre x86

Package(s) •40 pin DIP

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Thanks