Computer Organization & Architecture

(COA)
GTU # 3140707

Unit-II
Basic Computer Organization and
Design
 Outline
Looping
• Instruction Codes
• Computer Registers
• Computer Instructions
• Timing and Control
• Instruction Cycle
• Memory-Reference Instructions
• Input-output and Interrupt
• Complete Computer Description
• Design of Accumulator Unit
Instruction Codes
Instruction Codes
 Program
 A program is a set of instructions that specify the operations, operands and the sequence by which
processing has to occur.
 Computer Instruction
 A computer instruction is a binary code that specifies a sequence of micro-operations for the computer.
 The computer reads each instruction from memory and places it in a control register.
 The control then interprets the binary code of the instruction and proceeds to execute it by issuing a
sequence of micro-operations.
 Instruction Code
 An instruction code is a group of bits that instruct the computer to perform a specific operation.
 Example ADD Unique Binary
1547 code is assigned
 Operation Code (Opcode) to every Opcode
 The operation code of an instruction is a group of bits that define such operations as add, subtract,
multiply, shift, and complement.
 The number of bits required for the operation code of an instruction depends on the total number of
operations available in the computer.
Stored Program Organization

Memory
4096 x 16

15 12 11 0
Opcode Address
Instructions
(program)
Instruction Format

15 0 Operand
Binary Operand (data)

Processor Register
(accumulator or
AC)
Stored Program Organization
 The simplest way to organize a computer is to have one processor register(AC) and an
instruction code format with two parts.
 The first part specifies the operation (opcode) to be performed and the second specifies an address
(operand).
 The memory address tells the control where to find an operand in memory.
 This operand is read from memory and used as the data to be operated on together with the
data stored in the processor register.
 Instructions are stored in one section of memory and data in another.
 For a memory unit with 4096 words, we need 12 bits to specify an address since 2 12 = 4096.
 If we store each instruction code in one 16-bit memory word, we have available four bits for
operation code (opcode) to specify one out of 16 possible operations, and 12 bits to specify
the address of an operand.
 The control reads a 16-bit instruction from the program portion of memory.
 It then executes the operation specified by the operation code.
Instruction format of basic computer

Instruction Format
15 14 12 11 0
I Opcode Address

0 0 0 1 0 1 0 0 0 1 0 1 0 1 1 1
Add Instruction – ADD 457
Direct & Indirect Addressing of Memory
 If the second part of an
Memory Memory
instruction format specifies the
AD AD
22 0 457 35 1 300 address of an operand, the
D D
instruction is said to have a
direct address.
300 1350
 In Indirect address, the bits in
457 Operand the second part of the
1350 Operand instruction designate an
address of a memory word in
which the address of the
operand is found.
+ +

AC AC
Direct & Indirect Addressing of Memory
15 14 12 11 0 15 14 12 11 0
22 0 ADD 457 35 1 ADD 300

 A direct address instruction is placed at  The instruction in address 35 has a mode bit
address 22 in memory. I = 1, recognized as an indirect address
 The I bit is 0, so the instruction is instruction.
recognized as a direct address instruction.  The address part is the binary equivalent of
 The opcode specifies an ADD instruction, 300.
and the address part is the binary equivalent  The control goes to address 300 to find the
of 457. address of the operand.
 The control finds the operand in memory at  The address of the operand in this case is
address 457 and adds it to the content of 1350.
AC.  The operand found in address 1350 is then
added to the content of AC.
Computer Registers
Registers are small, fast storage locations within the CPU that are used to store temporary data during program
execution

 Register Initialization:
 mov eax, 5: Moves the immediate value 5 into the eax register.
 mov ebx, 3: Moves the immediate value 3 into the ebx register.

 Arithmetic Operations:
 add eax, ebx: Adds the values in registers eax and ebx, and stores the result in eax.
 sub eax, 2: Subtracts the immediate value 2 from the value in eax and updates eax with the
result.

 System Call for Exit:

 mov eax, 1: Sets the system call number for sys_exit in eax.
 xor ebx, ebx: Clears the ebx register (exit code 0).
 int 0x80: Triggers a software interrupt to invoke the system call for program exit.
Computer Registers
11 0 15 0
Program Accumulator(16
PC Counter(12)
Holds address of instruction AC )Processor register

11 0 7 0
Address Output
AR Register(12)
Holds address for memory OUTR Register(8)
Holds output character
15 0 7 0
Instruction Input
IR Register(16)
Holds instruction code INPR Register(8)
Holds input character
15 0
TR Temporary Memory
Register(16)
Holds temporary data
4096 words
15 0
Data 16 bits per word
DR Register(16)
Holds memory operand
 1 S2
0 S1 Bus
Common Bus Memory
4096 x 16
0 S0
7

System of
Address
Write Read
AR 1

Basic L
D
INR CL
PC R 2

Computer AC
L INR CL
D DR R 3
1 L INR CL
Adder E D R
& AC 4
Logic
L INR CL
D R
INPR
DR AC
IR 5
L
AC DR D TR 6
L INR CL
D OUTR R
Clock
L
D AC
Computer Instructions
 • Computer Instructions
Computer instructions practically often involve using assembly language
programming or working with low-level languages that directly interact with a
computer’s hardware.
Assembly program prints "Hello, World!" to the console using Linux system calls.

 The program is divided into sections, such as .data for data storage and .text for executable
instructions.
 Data Section:
msg db 'Hello, World!', 0: Defines a null-terminated string in the data section.

 Text Section:
start:: The entry point of the program.
mov instructions: Move values into registers.
int 0x80: Triggers a software interrupt, invoking a system call. The specific system
call and its parameters are set in registers.
 System Calls:
The program uses two system calls: sys_write to print to the console and sys_exit to
terminate the program.
 AND: which performs AND operation between Word & Accumulator.

ADD: It performs an Addition operation between the content present in the Word
and the content present in the Accumulator.

LDA: Loading the instruction from register to word.

STA: Store the content from Word to register.

BUN: Branch Unconditional (the control flow will be sequential) while we apply the BUN
Instruction that is not in the sequence will also be executed.

BSA: Branch and save return address (if one instruction is executed, then the address of the
Next instruction will be available on the program counter) that will be loaded into
Accumulator.

ISZ: Increment if Zero. (increment the program counter if the value is zero).

All these are OPCODES.

Types of Computer Instructions
1. Memory Reference Instruction
15 14 12 11 0
I Opcode Address

01 01 01 01 Address

0xxx 8xxx AND AND the content of memory to AC

1xxx 9xxx ADD Add the content of memory to AC
2xxx Axxx LDA Load memory word to AC
3xxx Bxxx STA Store content of AC in memory
4xxx Cxxx BUN Branch unconditionally
5xxx Dxxx BSA Branch and save return address
6xxx Exxx ISZ Increment and skip if zero
Types of Computer Instructions
2. Register Reference Instruction
15 14 13 12 11 0
0 1 1 1 Register Operation

0 1 1 1 10 10 01 10 01 10 01 0 0 0 0 0

7800 CLA Clear AC 0111 1000 0000 0000

7400 CLE Clear E 0111 0100 0000 0000
7200 CMA Complement AC 0111 0010 0000 0000
7100 CME Complement E 0111 0001 0000 0000
7080 CIR Circulate right AC and E 0111 0000 1000 0000
7040 CIL Circulate left AC and E 0111 0000 0100
7020 INC 0000
Increment AC 0111 0000 0010 0000
Types of Computer Instructions
2. Register Reference Instruction

15 14 13 12 11 0
0 1 1 1 Register Operation

0 1 1 1 0 0 0 0 0 0 0 10 01 10 01 01

7010 SPA Skip next instruction if AC is positive

7008 SNA Skip next instruction if AC is negative
7004 SZA Skip next instruction if AC is zero
7002 SZE Skip next instruction if E is zero
7001 HLT Halt computer
Types of Computer Instructions
3. Input – Output Instruction
15 14 13 12 11 0
1 1 1 1 I/O Operation

1 1 1 1 10 01 10 01 01 01 0 0 0 0 0 0

F800 INP Input character to AC

F400 OUT Output character from AC
F200 SKI Skip on input flag
F100 SKO Skip on output flag
F080 ION Interrupt on
F040 IOF Interrupt off
Instruction Set Completeness
 Instruction set is said to be complete if it includes enough instructions in each of the
following categories:
1. Arithmetic, logical and shift instructions
2. Instructions for moving information to and from memory and processor registers
3. Program control instructions together with instructions that check status conditions
4. Input and output instructions
Timing and Control
Timing and control in computer architecture are typically implemented at a low level, involving clock signals,
control signals

 Loop Initialization:
 mov ecx, 10: Initializes the loop counter (ecx register) with the value 10.

 Delay Loop:
 dec ecx: Decrements the loop counter.
 jz exit_program: Jumps to the exit_program label if the zero flag is set (indicating the counter
is zero).
 jmp delay_loop: Jumps back to the delay_loop label to repeat the loop.

 Exit Program:
 mov eax, 1: Sets the system call number for sys_exit in eax.
 xor ebx, ebx: Clears the ebx register (exit code 0).
 int 0x80: Triggers a software interrupt to invoke the system call for program exit.
Control Organization
 Hardwired Control
 The control logic is implemented with gates, flips-flops, decoders and other digital circuits.
 It can be optimized to produce a fast mode of operation.
 It requires changes in the wiring among the various components if the design has to be modified or
changed.
 Microprogrammed Control
 The control information is stored in a control memory.
 The control memory is programmed to initiate the required sequence of micro-operations.
 Any required changes or modifications can be done by updating the microprogram in control memory.
Control Unit of Basic Computer
0 0 0 Instruction
1 0 Register
10001010111
Other inputs
15 14 13 12 11 - 0
0 0 0 1
3x8
Decoder
7 6 5 4 3 2 1 0 Control
D0 Control O/p
I D1 D7 Logic
Gates
T15
T0
15 14 ... 2 1
0 4 x 16
Decoder

4-bit sequence Increment

Clear
counter (SC) Clock(INR)
(CLR)
Control Unit
 Components of Control unit are
1. Two decoders
2. A sequence counter
3. Control logic gates
 An instruction read from memory is placed in the instruction register (IR).
 In control unit the IR is divided into three parts: I bit, the operation code (12-14)bit, and bits
0 through 11.
 The operation code in bits 12 through 14 are decoded with a 3 x 8 decoder.
 Bit-15 of the instruction is transferred to a flip-flop designated by the symbol I.
 The eight outputs of the decoder are designated by the symbols D0 through D7.
 Bits 0 through 11 are applied to the control logic gates.
 The 4‐bit sequence counter can count in binary from 0 through 15. The outputs of counter are
decoded into 16 timing signals T0 through T15.
 The sequence counter SC can be incremented or cleared synchronously.
Control Unit
 Most of the time, the counter is incremented to provide the sequence of timing signals out of
4 X 16 decoder.
 Once in awhile, the counter is cleared to 0, causing the next timing signal to be T 0.
 As an example, consider the case where SC is incremented to provide timing signals T 0, T1,
T2, T3 and T4 in sequence. At time T4, SC is cleared to 0 if decoder output D3 is active. This is
expressed symbolically by the statement
D3T4: SC ← 0
 Initially, the CLR input of SC is active.
 The first positive transition of the clock clears SC to 0, which in turn activates the timing T 0
out of the decoder.
 T0 is active during one clock cycle.
 The positive clock transition labeled T0 in the diagram will trigger only those registers whose
control inputs are connected to timing signal T0.
Timing Cycle for D3T4: SC ← 0
𝑇0 𝑇1 𝑇2 𝑇3 𝑇4 𝑇5
Clock

𝑇0
𝑇1

𝑇2

𝑇3
𝑇4
𝐷3
CLR
SC
Control Unit
 SC is incremented with every positive clock transition, unless its CLR input is active.
 This procedures the sequence of timing signals T0, T1, T2, T3 and T4, and so on. If SC is not
cleared, the timing signals will continue with T5, T6, up to T15 and back to T0.
 The last three waveforms shows how SC is cleared when D3T4 = 1.
 Output D3 from the operation decoder becomes active at the end of timing signal T 2.
 When timing signal T4 becomes active, the output of the AND gate that implements the
control function D3T4 becomes active.
 This signal is applied to the CLR input of SC.
 On the next positive clock transition the counter is cleared to 0.
 This causes the timing signal T0 to become active instead of T5 that would have been active if
SC were incremented instead of cleared.
Instruction Cycle
Instruction Cycle
 A program residing in the memory unit  Fetch & Decode
of the computer consists of a sequence of  PC is loaded with the address of the first
instructions. In the basic computer each instruction in the program.
instruction cycle consists of the  The micro-operations for fetch and decode phases
following phases: are as follows:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory if
the instruction has an indirect address.
 Determine the type of instruction
4. Execute the instruction.
 During time , the control unit determines the type of
 After step 4, the control goes back to step instruction i.e. Memory reference, Register reference
1 to fetch, decode and execute the next or Input-Output instruction.
 If then instruction must be register reference or input-
instruction. output else memory reference instruction.
 This process continues unless a HALT
instruction is encountered.
 Start
SC ← 0
𝑇0
AR ← PC
𝑇1
IR ← M[AR], PC ← PC
+1
𝑇2
Decode operation code in IR(12-14)
AR ← IR(0-11), I ← IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

𝑇3 𝑇3 𝑇3 𝑇3
Execute Execute AR ←
input-output register-reference Nothing
M[AR]
instruction instruction
SC ← 0 SC ← 0
Execute
memory-reference
instruction
SC ← 0
Memory-Reference Instructions
Memory Reference Instructions
1. AND: AND to AC
This is an instruction that performs the AND logic operation on pairs of bits in AC and the
memory word specified by the effective address. The result of the operation is transferred to
AC.
D0T4: DR  M[AR]
D0T5: AC  AC  DR, SC  0
2. ADD: ADD to AC
This instruction adds the content of the memory word specified by the effective address to
the value of AC. The sum is transferred into AC and the output carry C out is transferred to
the E (extended accumulator) flip-flop.

D1T4: DR  M[AR]
D1T5: AC  AC + DR, E  Cout, SC  0
Memory Reference Instructions
3. LDA: Load to AC
This instruction transfers the memory word specified by the effective address to AC.
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
4. STA: Store AC
This instruction stores the content of AC into the memory word specified by the effective
address.
D3T4: M[AR]  AC, SC  0
Memory Reference Instructions
5. BUN: Branch Unconditionally
This instruction transfers the program to instruction specified by the effective address. The
BUN instruction allows the programmer to specify an instruction out of sequence and the
program branches (or jumps) unconditionally.
D4T4: PC  AR, SC  0

6. BSA: Branch and Save Return Address

This instruction is useful for branching to a portion of the program called a subroutine or
procedure. When executed, the BSA instruction stores the address of the next instruction in
sequence (which is available in PC) into a memory location specified by the effective
address.
D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0
Memory Reference Instructions (BSA)

0 BSA 0 BSA
20 20
135 135
PC = 21 Next Instruction 21 Next Instruction

AR = 135 135 21
136 PC = 136

Subroutine Subroutine

1 BUN 1 BUN
135 135
Memory, PC and AR at Time Memory and PC after execution
T4
Memory Reference Instructions
7. ISZ: Increment and Skip if Zero
These instruction increments the word specified by the effective address, and if the
incremented value is equal to 0, PC is incremented by 1. Since it is not possible to
increment a word inside the memory, it is necessary to read the word into DR, increment
DR, and store the word back into memory.

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0
Input-output and Interrupt
Peripheral devices

Input-Output Serial Computer registers

terminal communication and flip-flop
interface
FGO =1=0

Receiver
Printer OUTR
Interface

AC

Transmitter
Keyboard INPR
Interface

FGI =0 =1
Input-Output of basic computer
 A computer can serve no useful purpose unless it communicates with the external
environment.
 To exhibit the most basic requirements for input and output communication, we will use a
terminal unit with a keyboard and printer.
 The terminal sends and receives serial information and each quantity of information has eight
bits of an alphanumeric code.
 The serial information from the keyboard is shifted into the input register INPR.
 The serial information for the printer is stored in the output register OUTR.
 These two registers communicate with a communication interface serially and with the AC in
parallel.
Process of input & output information transfer
Input Output Transfer
 Initially, the Transfer
input flag FGI is cleared to 0.  The output register OUTR works similarly
When a key is struck in the keyboard, an 8- but the direction of information flow is
bit alphanumeric code is shifted into INPR reversed.
and the input flag FGI is set to 1.  Initially, the output flag FGO is set to 1. The
 As long as the flag is set, the information in computer checks the flag bit; if it is 1, the
INPR cannot be changed by striking another information from AC is transferred in
key. The computer checks the flag bit; if it is parallel to OUTR and FGO is cleared to 0.
1, the information from INPR is transferred The output device accepts the coded
in parallel into AC and FGI is cleared to 0. information, prints the corresponding
 Once the flag is cleared, new information character, and when the operation is
can be shifted into INPR by striking another completed, it sets FGO to 1.
key.  The computer does not load a new character
into OUTR when FGO is 0 because this
condition indicates that the output device is
in the process of printing the character.
Input-Output Instruction
D7IT3 = p (common to all input-output instructions)
IR(i) = Bi [bit in IR(6-11) that specifies the operation]
INP pB11 AC(0-7) ← INPR, FGI ← 0 Input Character
OUT pB10 OUTR ← AC(0-7), FGO ← 0 Output Character
SKI pB9 If (FGI = 1) then (PC ← PC + 1) Skip on input flag
SKO pB8 If (FGO = 1) then (PC ← PC + 1) Skip on output flag
ION pB7 IEN ← 1 Interrupt enable on
IOF pB6 IEN ← 0 Interrupt enable off
Interrupt Cycle

Instruction cycle = 0 = 1 Interrupt cycle

R

Fetch & Decode Store return address

instruction in location 0
M[0] ← PC
Execute IE =0
instruction N
=1 Branch to location 1
PC ← 1
=1 FGI
=0
IEN ← 0
=1 FG
R←0
O
=0
R←1
Interrupt Cycle
 The interrupt cycle is a hardware implementation of a branch and save return address
operation.
 An interrupt flip-flop R is included in the computer.
 When R = 0, the computer goes through an instruction cycle.
 During the execute phase of the instruction cycle IEN (interrupt enable flip-flop) is checked
by the control.
 If it is 0, the programmer does not want to use the interrupt, so control continues with the
next instruction cycle.
 If IEN is 1, control checks the flag bits.
 If both flags are 0, it indicates that neither the input nor the output registers are ready for
transfer of information.
 In this case, control continues with the next instruction cycle. If either flag is set to 1 while
IEN = 1, flip-flop R is set to 1.
 At the end of the execute phase, control checks the value of R, and if it is equal to 1, it goes
to an interrupt cycle instead of an instruction cycle.
Register transfer statements for Interrupt cycle
 The flip-flop is set to 1 if IEN = 1 and either FGI or FGO are equal to 1. This can happen
with any clock transition except when timing signals T0, T1 or T2 are active.
 The condition for setting flip-flop R = 1 can be expressed with the following register transfer
statement:
T0 T1 T2 (IEN) (FGI + FGO): R  1
 The symbol + between FGI and FGO in the control function designates a logic OR operation.
This is AND with IEN and T0 T1 T2.
 The fetch and decode phases of the instruction cycle must be modified and Replace T 0, T1, T2
with R'T0, R'T1, R'T2
 Therefore the interrupt cycle statements are :
RT0 : AR  0, TR  PC
RT1 : M[AR]  TR, PC  0
RT2 : PC  PC + 1, IEN  0, R  0, SC  0
Register transfer statements for Interrupt cycle
 During the first timing signal AR is cleared to 0, and the content of PC is transferred to the
temporary register TR.
 With the second timing signal, the return address is stored in memory at location 0 and PC is
cleared to 0.
 The third timing signal increments PC to 1, clears IEN and R, and control goes back to T 0 by
clearing SC to 0.
 The beginning of the next instruction cycle has the condition RT 0 and the content of PC is
equal to 1. The control then goes through an instruction cycle that fetches and executes the
BUN instruction in location 1.
Demonstration of Interrupt Cycle

0 0 256
0 BUN 0 BUN
1 PC = 1
1120 1120
255 255
PC = 256 256
Main Program Main Program

1120 1120
I/O program I/O program

1 BUN 0 1 BUN 0

Before Interrupt After Interrupt

Complete Computer Description
 Start
SC ← 0, IEN ← 0, R ←
0

(Instruction cycle) = 0 =1 (Interrupt cycle)

R

𝑅′𝑇0 𝑅𝑇 0
AR ← PC AR ← 0, TR ← PC
𝑅′𝑇1 𝑅𝑇 1
M[AR] ← TR, PC ←
IR ← M[AR], PC ← PC + 1
0
𝑅′𝑇2 𝑅𝑇 2
Decode operation code in IR(12-14) PC ← PC + 1, IEN ←
AR ← IR(0-11), I ← IR(15) 0, R ← 0, SC ← 0

(Register or I/O) = 1 = 0 (Memory-reference)

D7
(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)
I I

𝑇3 𝑇3 𝑇3 𝑇3
Execute Execute AR ←
Nothing
input-output register-reference M[AR]
instruction instruction
SC ← 0 SC ← 0
Execute
memory-reference
instruction
SC ← 0
Design of Accumulator Unit
Design of Accumulator Logic
 In order to design the logic associated with AC, it is necessary to extract all the statements
that change the content of AC.

D0T5: AC  AC  DR, SC  0 AND with DR

D1T5: AC  AC + DR, SC  0 ADD with DR
D2T5: AC  DR Transfer from DR
pB11: AC(0-7) ← INPR, FGI ← 0 Transfer from INPR
rB9: AC ← AC’ Complement
rB7: AC ← shr AC, AC(15) ← E Shift right
rB6: AC ← shl AC, AC(0) ← E Shift left
rB11: AC ← 0 Clear
rB5: AC ← AC + 1 Increment
Design of Accumulator Logic

Circuit associated with AC

16
16 Adder and logic 16 Accumulator register 16
From DR
circuit (AC) To bus
8
From INPR

LD INR CLR
Clock

Control gates
Design of Accumulator Logic
Gate structure for controlling LD, INR and CLR of AC
D0 AND
T5 16 16
AC
D1 ADD From To bus
Adder
D2 DR & Logic LD INR CLR
T5
Clock
p
B11 INPR
r CMA
B9

SHR
B7
SHL
B6
INC
B5
CLR
B11
End of Unit-II First Half
Thank You