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Implementation of Spi Master Core

This project presents the design of an SPI master core using Verilog HDL. SPI (Serial Peripheral Interface) is a synchronous serial communication protocol that allows for serial data transmission between devices. The SPI master core was developed to generate a serial clock from a wishbone master clock to control data exchange between the SPI master and multiple SPI slave devices in a master-slave configuration. Key components of the SPI master core include generating the serial clock, transmitting data on MOSI from master to slave, and receiving data on MISO from slave to master. The project focuses on developing the block-level architecture and RTL code for the SPI master core in Verilog.

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Ganesh Jalla
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102 views14 pages

Implementation of Spi Master Core

This project presents the design of an SPI master core using Verilog HDL. SPI (Serial Peripheral Interface) is a synchronous serial communication protocol that allows for serial data transmission between devices. The SPI master core was developed to generate a serial clock from a wishbone master clock to control data exchange between the SPI master and multiple SPI slave devices in a master-slave configuration. Key components of the SPI master core include generating the serial clock, transmitting data on MOSI from master to slave, and receiving data on MISO from slave to master. The project focuses on developing the block-level architecture and RTL code for the SPI master core in Verilog.

Uploaded by

Ganesh Jalla
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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K.S.R.M.

COLLEGE OF ENGINEERING
(UGC-AUTONOMOUS)
Kadapa,Andhra Pradesh, India– 516 003
Approved by AICTE, New Delhi & Affiliated to JNTUA,
Ananthapuramu.
An ISO 14001:2004 & 9001: 2015 Certified Institution
Zeroth Project Review for the award of Bachelor of Technology

IMPLEMENTATION OF SPI MASTER CORE

Under The Guidance of


Smt.D.MAMATHA MTech

Assistant Professor,
Batch No: B7
Project Associates :
MAREPALLI SUSHMITHA –209Y1A0488
MOORATHOTI SARADA - 209Y1A0492
MANNURU VENKATA PREETHI - 209Y1A0486
JALLA GANESH – 209Y1A0464
GUDIPALLE MANOJ – 209Y1A0460

Department of Electronics and Communication Engineering


2023-2024
SERIAL PERIPHERAL
INTERFACE
SCLK
MOSI
Master MISO Slave
SS
ABSTRACT

 This project presents the design of the SPI master core. It is a commonly used
communication protocol that allows serial data transfer between a master
and multi-slave device over a short distance. In this project, we will focus on
block-level architecture and develop RTL code for the same. This controller
is developed using Verilog HDL based on the IEEE standards and also verified
using Verilog HDL code. The main part of the SPI master core is to generate
the serial clock which will be derived from the wishbone master clock. The
SPI protocol works with Master-Slave configuration, in full duplex mode. This
is a 4-wire transmission that includes “SCK, MOSI, MISO, SS”. MOSI will
transfer the bit serially from the SPI master core to the SPI slave and MISO
will receive the serial bit from the SPI slave to the SPI master.
Introduction
 Communication Protocol Developed By Motorola
 Four Wire Protocol
 Serial Interface
 Master-Slave Approach
 Synchronous- Data clocked with Clock Signal
 Data Rate-10mbps
 Full Duplex Protocol
 Low power than I2C (no need of Pull ups)
 Supports Single master and multiple slaves
 No hardware slave acknowledgement
Overview
 SPI stands for Serial Peripheral Interface
 Used for moving data simply and quickly from one device to another
 Used to communicate across small distances
 Master-Slave(Multiple Slaves, Single Master)
 Serial Interface
 Synchronous
 Data Exchange
Continue…
 SPI is a Master-Slave protocol
 The Master device controls the clock (SCK)
 No data is transferred unless a clock signal is present
 All slaves are controlled by the master clock
 The slave devices may not manipulate the clock
 Master Set Slave Select low
 Master Generates Clock
 Shift registers shift in and out data
Continue…
 Simple SPI Protocol Specifies 4 Signal Wires
 Master Out Slave In (MOSI)
 Master In Slave Out (MISO)
 Serial Clock (SCLK)
 Slave Select (SS)
 MOSI – Carries data out of Master to Slave
 MISO – Carries data from Slave to Master (Both signals happen for every transmission)
 SS – Unique line to select a slave
 SCLK – Master produced clock to synchronize data transfer MOSI
Continue…
 SPI is a Data Exchange protocol
 As data is being clocked out, new data is clocked in
 Data is exchanged - no device can just be a transmitter only or receiver only
 the master controls the exchange by manipulating the clock line (SCK)
 Often a signal controls when a device is accessed - this is the CS or SS signal
 CS or SS signal is known as “Chip Select” or “Slave Select” and is frequently an active-low signal.
 Data is only output during the rising or falling edge of SCK
 Data is latched during the opposite edge of SCK
 The opposite edge is used to ensure data is valid at the time of reading
Single Master and Single Slave
 Master
• Initiates the Connection
• Controls SCLK and Data transfer
 Slave
• Transmits Data
• Receives Data

SCLK
MOSI
Master MISO Slave
SS
Master and multiple daisy-chained slaves
SPI Peripherals
 Converters (ADC, DAC)
 Memories (EEPROM, RAM’s, Flash)
 Sensors (Temperature, Humidity, Pressure)
 Real Time Clocks
 Misc.- Potentiometers, LCD controllers, UART’s, USB controller, CAN controller, amplifiers
Advantages
 Full Duplex Communication
 Higher Throughput than I2C
 Not Limited to 8 bit words in case of bit transferring
 Arbitrary choice of message size, content and Purpose
 Low Power
 Fast and easy
 Fast for point-to-point connections
 Easily allows streaming/Constant data inflow
 No addressing/Simple to implement
 Everyone supports it
REFERENCES

 1].K.Aditya, M.Sivakumar,F.Noorbasha, and P.B.Thummalakunta, “Design and Functional Verification of a


 SPI Master Slave Core Using System Verilog ,” International Journal of Computional Engineering Research,05
 2018.
 [2]. Zhili Zhou, Zheng Xie, Xin’an Wang and Teng Wang “Development of verification environment for SPI
 master interface using SystemVerilog” ICSP,2012 IEEE 11th international Conference.
 [3]. T.Liu and Y.Wang, “IP design of universal multiple devices SPI interface,” in AntiConterfeiting, Security
 and identification (ASID), 2011 IEEE International Conference on IEEE,2011,pp. 169-172.
 [4].K. Fathy and K. Salah, “An Efficient Scenario Based Testing Methodology Using UVM,” in 2016 17th
 International Workshop on Microprocessor and SOC Test and Verification (MTV), Dec 2016, pp. 57–60.
 [5]. S.Anantha , M.K.Kumar, and J.K. Bhandari, “Design and verification of SPI,” International Journal of
 Engineering Development and Research(IJEDR), vol 1, pp. 130-136,Dec.2014.
THANK YOU

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