International University

MICRO-PROCESSING
SYSTEM
Lecture 7:
AVR Interupt Programming
in C and Assembly

Vo Minh Thanh, M.Eng

School Of Electrical Engineering
1
Chapter 08B: AVR Interrupt Programming
in Assembly and C
 Polling versus Interrupt

 Using polling, the CPU must continually check

the device’s status.
 Using interrupt:
 A device will send an interrupt signal when
needed.
 In response, the CPU will perform an
interrupt service routine, and then resume
its normal execution.
Interrupt execution sequence
ATmega16 interrupt subsystem
 The ATmega16 has 21 interrupts:
 1 reset interrupt
 3 external interrupts
 8 timer interrupts
 3 serial port interrupts
 1 ADC interrupt
 1 analogue comparator interrupt
 1 SPI interrupt
 1 TWI interrupt
 2 memory interrupts
Table 10-1: Interrupt Vector Table for the ATmega32 AVR
Interrupt ROM Location (Hex)
Reset 0000
External Interrupt request 0 0002
External Interrupt request 1 0004
External Interrupt request 2 0006
Time/Counter2 Compare Match 0008
Time/Counter2 Overflow 000A
Time/Counter 1 Capture Event 000C
Time/Counterl Compare Match A 000E
Time/Counter 1 Compare Match B 0010
Time/Counterl Overflow 0012
Time/CounterO Compare Match 0014
Time/CounterO Overflow 0016
SPI Transfer complete 0018
USART, Receive complete 001A
USART, Data Register Empty 001C
USART, Transmit Complete 001E
ADC Conversion complete 0020
EEPROM ready 0022
Analog Comparator 0024
Two-wire Serial Interface (I C)
2
0026
Store Program Memory Ready 0028
 Interrupt Vector Name for the ATmega32/ATmegal6
in WinAVR
Interrupt Vector Name in WinAVR
External Interrupt request 0 INT0_vect
External Interrupt request 1 INT1_vect
External Interrupt request 2 INT2_vect
Time/Counter2 Compare Match TIMER2_COMP_vect
Time/Counter2 Overflow TIMER2_OVF_vect
Time/Counterl Capture Event TIMER1_CAPT_vect
Time/Counterl Compare Match A TIMER1_COMPA_vect
Time/Counterl Compare Match B TIMER1_COMPB_vect
Time/Counterl Overflow TIMER1_OVF_vect
Time/Counter0 Compare Match TIMER0_COMP_vect
Time/Counter0 Overflow TIMER0_OVF_vect
SPI Transfer complete SPI_STC_vect
USART, Receive complete USARTO_RX_vect
USART, Data Register Empty USARTO_UDRE_vect
USART, Transmit Complete USARTO_TX_vect
ADC Conversion complete ADC_vect
EEPROM ready EE_RDY_vect
Analog Comparator ANALOG_COMP_vect
Two-wire Serial Interface TWI_vect
Store Program Memory Ready SPM_RDY_vect
Enabling and disabling an interrupt
 Upon reset, all interrupts are disabled (masked),
meaning that none will be responded to by the
microcontroller if they are activated.
 The interrupts must be enabled (unmasked) by
software in order for the uc to respond to them.
 The D7 bit of the SREG (Status Register) is responsi-
ble for enabling and disabling the interrupts globally.
 Bit D7 D6 D5 D4 D3 D2 D1 D0
OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0

TOIE0 D0 Timer0 Overflow Interrupt Enable:

(0 / 1) = (Disable / Enable) Timer0 Overflow Interrupt
OCIE0 D1 Timer0 Output Compare Match Interrupt Enable:
(0 / 1) = (Disable / Enable) Timer0 Compare Match Interrupt
TOIE1 D2 Timer1 Overflow Interrupt Enable:
(0 / 1) = (Disable / Enable) Timer1 Overflow Interrupt
OCIE1B D3 Timer1 Output Compare B Match Interrupt Enable:
(0 / 1) = (Disable / Enable) Timer1 Compare B Match Interrupt
OCIE1A D4 Timer1 Output Compare A Match Interrupt Enable:
(0 / 1) = (Disable / Enable) Timer1 Compare A Match Interrupt
TICIE1 D5 Timer1 Input Capture Interrupt Enable:
(0 / 1) = (Disable / Enable) Timer1 Input Capture Interrupt
TOIE2 D6 Timer2 Overflow Interrupt Enable:
(0 / 1) = (Disable / Enable) Timer2 Overflow Interrupt
OCIE2 D7 Timer2 Output Compare Match Interrupt Enable:
(0 / 1) = (Disable / Enable) Timer2 Compare Match Interrupt

These bits, along with the I bit, must be set high for an interrupt to be responded to. Upon activation
of the interrupt, the I bit is cleared by the AVR itself to make sure another interrupt can not interrupt
the microcontroller while it is servicing the current one. At the end of the ISR, the RETI instruction will
make I = 1 to allow another interrupt to come in.

Figure 10-3: TIMSK (Timer Interrupt Mask) Register

 Steps to program an interrupt in C
1. Include header file #include <avr\interrupt.h>.
2. Clear (disable interrupts globally) and Set (enable interrupts
globally) the I bit of the SREG register using cli () and sei ()
macros.
3. Defining ISR: To write an ISR (interrupt service routine) for
an interrupt we use the following structure:
ISR (interrupt_vector_name) {
//our program
}
For example, the following ISR serves the Timer0 compare
match interrupt:
ISR (TIMER0_COMP_vect){
}
 Timer0 Interrupt Programming
// Using TimerO generate a square wave on pin PORTB.5, while
// at the same time transferring data from PORTC to PORTD.
#include <avr/io.h>
#include <avr/interrupt.h>
int main(){
DDRB = 0x20; // DDRB.5 = output
TCNT0 = -32; // timer value for 4 us
TCCR0 = 0x01; // Normal mode, int elk, no prescaler
TIMSK = (1<<TOIE0); // enable Timer0 overflow interrupt
sei(); // enable interrupts globally
DDRC = 0x00; // make PORTC input
DDRD = 0xFF; // make PORTD output
while (1) // wait here
PORTD = PINC; // transfer data from PortC to PortD
}

ISR (TIMER0_OVF_vect){ // ISR for Timer0 overflow

TCNT0 = -32; // timer value for 4 us
PORTB ^= 0x20; // toggle PORTB.5
}
 Example 10-9: timer0, timer1 Interrupt
(1/2)
// Using Timer0 and Timer1 interrupts, generate square waves
// on pins PB1 and PB7 respectively, while transferring data
#include <avr/io.h> // from PORTC to
PORTD
#include <avr/interrupt.h>
int main (){
DDRB |= 0x82; // make DDRB.l and DDRB.7 output
DDRC = 0x00; // make PORTC input
DDRD = 0xFF; // make PORTD output
TCNT0 = -160; // start from 96
TCCR0 = 0x01; // Normal mode,inernal clk, no
prescaler
TCNT1H = (-640)>>8; // the high byte 0xFD
TCNT1L = (-640); // the low byte 0x80
TCCR1A = 0x00; // timer1 in normal mode, no
prescaler
TCCR1B = 0x01; // use internal CLK.
// enable Timers 0 and 1 interrupts.
TIMSK = (1<<TOIE0) | (1<<TOIE1);
sei (); // enable global interrupts, set bit7 of
SREG
while (1) // wait here
PORTD = PINC;
 Example 10-9: timer0, timer1 Interrupt
(2/2)
// Using Timer0 and Timerl interrupts, generate square waves
// on pins PB1 and PB7 respectively, while transferring data

ISR (TIMER0_OVF_vect){ //ISR for Timer0 overflow

TCNT0 = -160; // TCNT0 = -160 (reload for next round)
PORTB ^= 0x02; // toggle PORTB.1
}

ISR (TIMER1_OVF_vect){ // ISR for Timer1 overflow

TCNT1H = (-640)>>8;
TCNT1L = (-640); // TCNT1 = -640 (reload for next round)
PORTB ^= 0x80; // toggle PORTB.7
}
 Timer0 Output Compare Match Interrupt
#include "avr/io.h"
#include "avr/interrupt.h"

int main ()
{
DDRB |= 0x20; // make DDRB.5 output
OCR0 = 40;
TCCR0 = 0x09; // CTC mode, internal elk, no
prescaler
TIMSK = (1<<OCIE0); //enable TimerO compare match int.
sei(); // enable interrupts
DDRC = 0x00; // make PORTC input
DDRD = 0xFF; // make PORTD output
while (1) // wait here
PORTD = PINC;
}

ISR (TIMER0_COMP_vect){ // ISR for TimerO compare match

PORTB ^= 0x20; //toggle PORTB.5
}
 External Hardware Interrupts
 The ATmega32 has three external hardware interrupts: pins PD2
(PORTD.2), PD3 (PORTD.3), and PB2 (PORTB.2), designated as INT0,
INT1, and INT2, respectively.
 Upon activation of these pins, the AVR is interrupted in whatever it is
doing and jumps to the vector table to perform the interrupt service
routine.
External Hardware Interrupts
 The interrupt vector table locations $2, $4, and $6 are set aside for
INT0, INT1, and INT2, respectively.
 The hardware interrupts must be enabled before they can take effect.
This is done using the INTx bit located in the GICR register.
 Upon reset INT0 and INT1 are low-level-triggered interrupts.
 INT2 is only edge triggered, while INT0 and INT1 can be level or edge
triggered.
 The bits of the MCUCR register indicate the trigger options of INT0
and INTl, as shown in Figure 10-7.
 Interrupts pulses shorter than 1 machine cycle are not guaranteed to
generate an interrupt.
 when an interrupt is in level-triggered mode, the pin must be held low
for a minimum time of 5 machine cycles to be recognized.
External Hardware Interrupts
 The ISC2 bit of the MCUCSR register defines whether INT2
activates in the falling edge or the rising edge (Figure 10-8).
 Upon reset ISC2 is 0, meaning that the external hardware
interrupt of INT2 is falling edge triggered.
 Using level-triggered Interrupt INT0
// Assume that the INT0 pin is connected to a switch that is
// normally high. Write a program that toggles PORTA.0,
// whenever INTO pin goes low. Use the external interrupt in
// level-triggered mode.
#include "avr/io.h"
#include "avr/interrupt.h"

int main (){

DDRA = (1<<0); // PA0 as an output
PORTD = (1<<2); // pull-up activated
MCUCR = 0x00; // make INT0 low level
triggered
// MCUCR = 0x02; // make INT0 falling edge
triggered
GICR = (1<<INT0) ; // enable external interrupt 0
sei (); // enable interrupts
while (1); // wait here
}

ISR (INT0_vect){ // ISR for external interrupt 0

PORTA ^= (1<<0) ; // toggle PORTA.0
}
 Using edge-triggered Interrupt INT0
// Assume that the INT0 pin is connected to a switch that is
// normally high. Write a program that toggles PORTA.0 only
// once whenever INTO pin goes low. (Use the external
// interrupt in edge-triggered mode).

#include "avr/io.h"
#include "avr/interrupt.h"

int main (){

DDRC = 1<<3; // PC3 as an output
PORTD = 1<<2; // pull-up activated
MCUCR = 0x02; // make INT0 falling edge
triggered
GICR = (1<<INT0) ; // enable external interrupt
0
sei (); // enable interrupts
while (1); //wait here
}

ISR (INT0_vect){ // ISR for external interrupt 0

PORTC ^= (1<<3) ; // toggle PORTC.3
}
 Using INT0, INT1 and INT2
#include "avr/io.h"
#include "avr/interrupt.h"
int main (){
DDRA = 0xFF; // PA as an output
MCUCR = 0x00; // make INT0 and INT1 low level triggered
MCUCSR = (1<<ISC2); // make INT2 rising edge triggered
GICR = (1<<INT0)|(1<<INT1)|(1<<INT2);
sei (); // enable interrupts
while (1); // wait here
}
ISR (INT0_vect){ // ISR for external interrupt 0
PORTA ^= (1<<0) ; // toggle PORTA.0
}
ISR (INT1_vect){ // ISR for external interrupt 1
PORTA ^= (1<<1) ; // toggle PORTA.1
}
ISR (INT2_vect){ // ISR for external interrupt 2
PORTA ^= (1<<2) ; // toggle PORTA.2
}
 Using INT0, INT1 and INT2 in ASM
#include "m32def.inc"
.org 0x0000
rjmp main
.org 0x0002
rjmp EXT_INT0
.org 0x0004
rjmp EXT_INT1
.org 0x0006
rjmp EXT_INT2

main:
LDI R16,0xFF
OUT DDRA,R16 ; DDRA = 0xFF; // PA as an output
LDI R16,0b00001011; MCUCR = 0b00001011;
OUT MCUCR,R16
LDI R16,0x00;
OUT MCUCSR,R16 ; MCUCSR = 0; // make INT2 rising edge triggered

LDI R16,(1<<INT0)|(1<<INT1)|(1<<INT2) ;
OUT GICR,R16 ; GICR = (1<<INT0)|(1<<INT1)|
(1<<INT2) ;

sei ; sei(); // enable interrupts

While_1:
rjmp While_1
 Using INT0, INT1 and INT2 in ASM
EXT_INT0:
IN R16,PORTA
LDI R17,(1<<0)
EOR R16,R17
OUT PORTA,R16;
RETI

EXT_INT1:
IN R16,PORTA ; PORTA ^= (1<<0) ; // toggle PORTA.0
LDI R17,(1<<1)
EOR R16,R17
OUT PORTA,R16;
RETI

EXT_INT2:
IN R16,PORTA
LDI R17,(1<<2)
EOR R16,R17
OUT PORTA,R16;
RETI
Using INT0, INT1 and INT2
Interrupts Priority
 If two interrupts are activated at the same time, the interrupt
with the higher priority is served first.
 The priority of each interrupt is related to the address of that
interrupt in the interrupt vector.
 The interrupt that has a lower address, has a higher priority. See
Table 10-1.
 For example, the address of external interrupt 0 is 2, while the
address of external interrupt 2 is 6; thus, external interrupt 0
has a higher priority, and if both of these interrupts are
activated at the same time, external interrupt 0 is served first.
Interrupt latency
 The time from the moment an interrupt is activated to the
moment the CPU starts to execute the task is called the
interrupt latency. This latency is 4 machine cycle times.
 During this time the PC register is pushed on the stack and the I
bit of the SREG register clears, causing all the interrupts to be
disabled.
 The duration of an interrupt latency can be affected by the type
of instruction that the CPU is executing when the interrupt
comes in,
 since the CPU finishes the execution of the current instruction
before it serves the interrupt. It takes slightly longer in cases
where the instruction being executed lasts for two (or more)
machine cycles (e.g., MUL) compared to the instructions that
last for only one instruction cycle (e.g., ADD).