ENCS3310

Advanced Digital Design

Primitives
Operators
Introduction

 Contents
 User Define Primitives (UDP)
 Operators
 Rise, Fall, and Turn-Off Delays
 The delays declaration can contain up to three
values, such as rise, fall, and turn-off delays.
 The time taken for the output of a gate to change
from some value to 1 is called a rise delay.
 The time taken for the output of a gate to change
form some value to 0 is called a fall delay.
 The time taken for the output of a gate to change
from some value to high impedance is called turn-
off delay.
Delays on Primitive Instances

 Instances of primitives may include delays

buf b1(a, b); // Zero delay

buf #3 b2(c, d); // Delay of 3
buf #(4,5) b3(e, f); // Rise=4, fall=5
buf #(4,5,2) b4(g,h); //Rise, Fail,Turnoff
User-Defined Primitives (UDP)

 Way to define gates and sequential elements

using a truth table
 Often simulate faster than using expressions,
collections of primitive gates, etc.
 Gives more control over behavior with X
inputs
 Most often used for specifying custom gate
libraries
UDP Features
 UDP’s do not use the keyword module. Instead they
are declared with the keyword primitive.
 There can be only one output and it must be listed
first in the port list and declared with an output keyword.
 There can be any number of inputs. The order in which
they are listed in the input declaration must conform to
the order in which they are given values in the table that
follows.
 The truth table is enclosed within the keywords table
and endtable.
 The values of the inputs are listed with a colon (:). The
output is always the last entry in a row followed by a
semicolon (;).
 It ends with the keyword endprimitive.
UDP Features
Symbol Comments
0 Logic 0
1 Logic 1
Unknown, can be either logic 0 or 1. Can be used as
x
input/output or current state of sequential UDPs
? Logic 0, 1 or x. Cannot be output of any UDP
- No change, only allowed in output of a UDP
ab Change in value from a to b where a or b is either 0, 1, or x

* Same as ??, indicates any change in input value

r Same as 01 -> rising edge on input

f Same as 10 -> falling edge on input
 UDP Example1
//User defined primitive(UDP)
primitive crctp (x,A,B,C);
output x;
input A,B,C;
//Truth table for x(A,B,C) = Minterms (0,2,4,6,7)
table
// A B C : x (Note that this is only a comment)
0 0 0 : 1;
0 0 1 : 0;
0 1 0 : 1;
0 1 1 : 0;
1 0 0 : 1;
// Instantiate primitive
1 0 1 : 0; module declare_crctp;
1 1 0 : 1;
1 1 1 : 1; reg x,y,z;
endtable
endprimitive wire w;
crctp (w,x,y,z);
endmodule
Example2: A Carry UDP
primitive carry(out, a, b, c);
output out;
input a, b, c; Always have
table exactly one
00? : 0; output
0?0 : 0;
?00 : 0; Truth table may
11? : 1; include don’t-
1?1 : 1; care (?) entries
?11 : 1;
endtable
endprimitive
A Sequential Primitive
Primitive dff( q, clk, data);
output q; reg q;
input clk, data;
table
// clk data q new-q
(01) 0 : ? : 0; // Latch a 0
(01) 1 : ? : 1; // Latch a 1
(0?) 1 : 1 : 1; // Hold when d and q both
1
(0?) 0 : 0 : 0; // Hold when d and q both
0
(?0) ? : ? : -; // Hold when clk falls
? (??) : ? : -; // Hold when clk stable
endtable
endprimitive
Three-State Gates
 Three-State Gates
 Three-state gates have a control input that can place
the gate into a high-impedance state. (symbolized by z
in HDL).
 The bufif1 gate behaves like a normal buffer if
control=1. The output goes to a high-impedance
state z when control=0.
 bufif0 gate behaves in a similar way except that the
high-impedance state occurs when control=1
 Two not gates operate in a similar manner except that
the o/p is the complement of the input when the gate is
not in a high impedance state.
 The gates are instantiated with the statement
 gate name (output, input, control);
 Three-State Gates
• Keywords wire and tri are examples of net data type.
•Nets represent connections between hardware
elements. Their value is continuously driven by the
output of the device that they represent.
•The word net is not a keyword, but represents a class
of data types such as wire, wor, wand, tri, supply1 and
supply0.
• The wire declaration is used most frequently.
•The net wor models the hardware implementation of the
wired-OR configuration.
• The wand models the wired-AND configuration.
•The nets supply1 and supply0 represent power supply
and ground.
Gate-level Primitives

 Verilog provides the following:

and nand logical AND/NAND

or nor logical OR/NOR
xor xnor logical XOR/XNOR
buf not buffer/inverter
bufif0 notif0 Tristate with low enable
bufif1 notif1 Tristate with high enable
 Operators
{} concatenation ~ bit-wise NOT
+ - * / & bit-wise AND
arithmetic | bit-wise OR
% modulus ^ bit-wise XOR
^~ ~^ bit-wise XNOR
> >= < <=
& reduction AND
relational
| reduction OR
! logical NOT ~& reduction NAND
&& logical AND ~| reduction NOR
|| logical OR ^ reduction XOR
== logical equality ~^ ^~ reduction XNOR
!= logical inequality << shift left
?: conditional >> shift right
 Operator Precedence
[ ] bit-select or part-select >, >=, <, <=
( ) parentheses relational
!, ~ logical and bit-wise ==, != logical equality
negation & bit-wise AND
&, |, ~&, ~|, ^, ~^, ^~ ^, ^~, ~^
reduction operators bit-wise XOR and XNO
+, - unary arithmetic | bit-wise OR
{ }concatenation && logical AND
*, /, % arithmetic || logical OR
+, - arithmetic ?: conditional
<<, >> shift
Numbers
Format : <size>’<base><value>
Example : 8’d16
8’h10
8’b00010000
8’o20
Summary

 UDP
 Operators
 3-state gates
 Wire types (nets)