EEE600 VLSI Design

Verification and Testing

Course organization

Sakthivel R
 Course outline
• This course covers the analysis and implementation of test
techniques for digital VLSI
– regular class lectures form the core of the course
– exercise sessions are scheduled
– hand-on computer laboratory sessions

• Introduction to test theory

– Introductory topics cover the role of testing
– automatic test equipment and
– overview of the economics of test

• Test methods
– fault modeling and fault simulation
– automatic test-pattern generation
– measures of testability

Sivanantham S
 Course outline (2)
• Design for testability
– scan design
– built-in-self-testing
– Boundary-Scan standard (JTAG)

• Advanced Testing
– Analog Testing
– Delay Test

Sivanantham S
 Course goals
Upon completing this course, students shall

• have a theoretical understanding of popular integrated circuits (IC)

testing algorithms
• be able to incorporate appropriate testing techniques into various
phases of VLSI development
• have acquired an introductory knowledge of test EDA software
tools and their integration in a global design-flow

• understand the necessity of VLSI testing

• know standard methods applied in VLSI testing
• be able to apply appropriate testing methods in various phases of
VLSI developments

Sivanantham S
 Documents
• documents distributed in class:
– lecture slides
– homework exercises
– practical laboratory reports and documentation

Sivanantham S
 Major References

Following books have been utilized in the preparation of this

course, and teaching material as the main sources

M. L. Bushnel and W. D. Agrawal, “Essential of Electronic Testing for Digital,

Memory, and Mixed Signal VLSI Circuits,” Springer, 2005

N. Jha and S. Gupta, “Testing of Digital Systems,” Cambridge University Press,

2003

L.-T. Wang, C.-W. Wu, X. Wen, “VLSI Test Principles and Architectures,” Morgan
Kaufmann (Elsevier), 2006

Sivanantham S
 Logistics (1)
• class lectures

• exercise sessions
– exercises will be distributed regularly as homework
– a number of class hours will be reserved for exercise solving

• laboratory sessions
– mostly at the end of the every two week, because knowledge must first
be acquired on EDA-based design, VLSI design, and hardware
systems modeling
– laboratory guide/report will be delivered in class

Sivanantham S
 Course grading policy
• homework's will not be graded
• SET Conference – 20 %
• practical laboratory sessions: 25%
a report will be delivered after completion of the laboratory sessions,
and will be graded
Report should be prepared using Latex. A separate training session will
be arranged to learn Latex

written examination: 55%

– Midterm (15 %)
– final examination (40 %)

Sivanantham S
 Links with other courses
• integrated circuit test is related to several courses in VLSI design
• typically, a background is needed in VLSI, and hardware modeling
in order to take optimal benefit of IC Testing, and be able to
practically apply the proposed methods

• for the practical part, knowledge in hardware modeling and

synthesis would be recommendable

Sivanantham S
Simplified integrated circuit development flow
Problem analysis each of these steps involves the
interaction of
Write Specifications – humans with humans
– humans with computer software
Partition into sub-blocks – computer software with various
database file formats
HDL description
Schematic of sub-blocks very soon, you will be familiar with all
Synthesis theses steps (EDA-Based Design)
Design mask layout
Placement and routing misunderstanding, wrong interpretation
of simulation results, errors, software
Floorplaning bugs (!), …, may occur in any step

Generation of gdsii

red arrows: simulation, back-annotation, redesign

Sivanantham S
 Simplified chip fabrication process
gdsii chip description Wafer fabrication each of these steps involves the
interaction of
Field oxyde growth/metallizaton
– several machines
– several chemical components
Lithography
– a clean room environment, where
n times all room parameters are constant
Etching
– human operators
Planarization

unstable process temperature,

dust, unwanted impurities,
imprecise timings, approximate
chemical concentrations, non-
Wafer sawing laminar gas flows, …, may occur in
any step
Chip packaging

once fabrication has started, no quality assessment can be

done till the chip can be tested

Sivanantham S
 Hardware models
In VLSI, models are used at
various abstraction levels to
predict how a circuit will
performs once fabricated

Simulators apply stimuli to

selected models to produce
the output signals

M1
SiO2
SiO2
n+ n+

Sivanantham S
 Hardware models (2)
However …

• a model is hypothesis of how a component, a circuit or a defective

circuit may behave
e.g. to do a transistor-level SPICE simulation, you may chose
BSIM3v3 or EKV transistor models; under specific conditions, the
result signals will differ significantly

Nevertheless …

• having a model of faults, it is possible to predict how a faulty circuit

will behave

• thus, defects affecting a chip can be identified

Sivanantham S
 Perfect circuits
• Most courses in device technology, VLSI, hardware modeling,
analog circuit design consider that presented devices, circuits
will be fabricated with a perfect matching with the applied
models, i.e. it is expected that the fabricated circuits behave as
simulations suggest

• This holds true … in most cases

however …

Sivanantham S
 Real-World Circuits
An NMOS transistor is fabricated like In practice, following mask layout
this, according to semiconductor are designed
device theory

M1
SiO2
top view
SiO2
n+ n+
cross-section

The transistor that is actually

fabricated looks as depicted
i4004 optical Source Intel Corp.

Sivanantham S
 Real-World Circuits (2)

Focused Ion Beam (FIB) image of metal lines on the surface of an IC

• Rounded edges can be observed, instead of sharp 90 degree angles

• Ripple in the material surface, where is should be flat

image source unknown

Sivanantham S
 A chip may be defective because …
• The circuit does not comply with the project specifications
– development errors  functional test

correct functionality of the modules is tested in a functional test; a high

coverage of the fault is targeted, leading to a long test process

• The manufactured chip does not match with the developed chip
– physical or manufacturing defects  structural test

the presence of all signal lines, and their ability to carry 0 and 1s is
checked in a structural test

Sivanantham S
 Catastrophic defects

bridge formation (DRAM) - optical defective via (void in Al layer) - SEM

residual particle masked the metal-

etch process - optical electromigration notch
Sources: T. Reuter, et al , Using laser-based patterned-wafer inspection for memory and logic applications; J. M. Soden, et al, IC Failure Analysis:
Magic, Mystery, and Science; C. F. Hawkins, et al, Test and Reliability: Partners in IC Manufacturing, Part 1

Sivanantham S
 More causes of defects
• bridged or missing metal
• contamination by particles
• missing contact window
• oxide breakdown
• over etching, or incomplete etching
• mechanical damage, or scratches
• defective mask
• defective photoresist
• incomplete removal of photoresist
• cracks, crystal imperfections
• defective connection on the bonding pads
• etc.

Sivanantham S
 Definitions
• Verification Predictive analysis to ensure that the synthesized
design, when manufactured, will perform the given I/O function.
– Verifies correctness of design.
– Performed by simulation, hardware emulation, or formal methods.

• Test A manufacturing step that ensures that the physical device,

manufactured from the synthesized design, has no manufacturing
defect.
– Verifies correctness of manufactured hardware.
– Two-part process:
1. during the design of the system, test structures are included on-chip, and
software simulation enable deducting test vectors
2. after the chip is fabricated, electrical tests are applied to the hardware

Sivanantham S
 Why test electronic systems
The rule of Ten The cost of discovering a defective chip increases by an order
of magnitude at each successive level of integration, from die/package, board
and system.

1000 Field
System
Test and 100
Board
repair cost 10
Component
1

Product Phase

The economical model of cost/profit for an IC-based system must also include
testing

To place in the balance:

• cost of testing and testing equipment, testing time overhead, vs.
• cost of shipping defective ICs, or systems, that need further repair

Sivanantham S
 OK ! Let us perform IC test …
… so what are the issues of testing ? (1)
scales / dimensions
• the silicon chip delivered back from fabrication has no dimensions
in match with human scale (e.g. Sony Cell processor, 2006)
– it is tiny: 221mm2 in a 65nm technology
– it has a huge number of transistors: 234e6
– it runs fast: 4.6GHz

>5M transistor microprocessor, its surface 0.2m x 0.4m nickel particle

is 196mm2, it has 5 levels of wiring causing a short between two nodes
Sources: D. P. Vallett, IC Failure Analysis: The Importance of Test and Diagnostics

Sivanantham S
 OK ! Let us perform IC test …
… so what are the issues of testing ? (2)
complexity
• the chip is formed of numerous functional blocks
– datapath, memory, control logic, etc.
– each of these blocks are conceived by different groups, using various
development methods

Intel Core2 Duo Extreme

Control
presumably semi-
Memory custom
memory generators
Datapath
full-custom design

• a strategy on how this chip will be tested must be decided before

fabrication - actually, the test strategy must be developed hand in
hand with the development of the chip Source: Intel Corp.

Sivanantham S
 Roles of testing
• Detection Determination whether or not the device under test
(DUT) has any faults
– identification of process flaw
– detection of chips that must not be sold to customers

• Diagnosis Location and identification of a specific fault that is

present on DUT

• Device characterization Identification of errors in the actual

design or in the testing procedure

• Failure mode analysis (FMA) Determination of manufacturing

process errors that may have caused defects on the DUT
– used in all stages of test in order to improve the manufacturing process
and the number of fault-free chips

Sivanantham S
 Real tests
• Based on analyzable fault models, which may not perfectly match
real defects

• Incomplete coverage of modeled faults due to the extreme

complexity of modern integrated circuit designs
– mixed-mode analog and digital
– including several cores, memory
– hundreds of millions of transistors

• Some good chips are rejected. The fraction (or percentage) of

such chips is called the yield loss.

• Some bad chips pass tests. The fraction (or percentage) of bad
chips among all passing chips is called the defect level.

Sivanantham S
 How chips are tested
The internals of the integrated circuit is not accessible !
• binary patterns called test vectors are applied to the inputs
• the outputs are compared to expected values

Digital Input Circuit Correct

Patterns Response Response
DUT
100 101 101
110 Device Under 111 110
Test DUT
Comparator

010 Digital Circuit 010 010

Result of
Test

• the process is automatized using an Automatic Test Equipment (ATE)

Sivanantham S
 ATE example: Agilent 93000 (1)
• subpoints mainframe

workstation

testhead

Source: Agilent

Sivanantham S
 ATE example: Agilent 93000 (2)
• workstation
– test software, interface and control of mainframe
– test engineer computer

• mainframe
– test computer
– power sources
– measurement instruments

• testhead
– Device Interface Board (DIB) to Device Under Test (DUT)
– sensible measurement equipment kept close to DUT

• ATE manufacturers: Teradyne, LTX, Agilent, Credence, …

Figure source: unknown

Sivanantham S
 Probers

Wentworth Laboratories Cantilever Probecard

Electroglas, Inc.

• robotic machine that manipulates the wafers

• connects individual chip to probe card needles
• ATE is connected for measurement

Philips

Sivanantham S
 Four types of testing: 1. Characterization
• characterization verification that a new design is functionally
correct and will meet the specifications, prior to production

– determines the limits of some operating values

• a pass or fail decision is provided
• the plot is based on numerous pass/fail decisions, that have been obtained
under various parameter combinations
• a limited number of chips is tested (statistically relevant sample)
• perform the test on a combination of two of more variables
• plot the schmoo plot

Sivanantham S
 Schmoo plot (characterization)
V
Example: this sample is
2.0 @ the result of the one test
* * @
* procedure under the
@
* * * @ conditions Vcc=2.0V and
* @
* @ clk =1.37 GHz; it has
* * * * @@ @
1.8 * failed
* * * @ @@ @
* * * @ @
* *
* * * @ @@@@
fail * @
* * @ @@ @ correct
1.6 * * @ @ @ @
* @@ @ @ @@ @ @ @
@ @ @ @ @@
@
@@ @@@ operation:
@@@@ @ @
@ @ @ @ @@ @ pass
@ @@ @ @ @@

1.2 1.3 1.4 1.5 1.6 1.7 GHz

• consider two (or more) variables, and apply simultaneous variations

• identify pass/fail regions

Sivanantham S
 Four types of testing: 2. Go/No-Go
• test class: production test, go/no-go

• every chip is tested  test time must be minimized

• all relevant characteristics of the specifications are tested, i.e. no
full coverage can be considered
• no fault diagnosis is attempted  go/no-go
• has to be fast, and efficient to limit testing errors to occur

Sivanantham S
 Four types of testing: 3. Burn-in
• burn-in, stress test
• Procedure:
– Integrated circuits are exposed to higher-than-usual levels of stress:
temperature, power voltage, etc. to speed up degradation 
accelerated life test
• Detected faults:
– Infant mortality chips that are subject to defects have a high failure
rate in the early phase of their life cycle; it is very undesirable to ship or
use these ICs
– Freak failures devices exhibiting the same failure mechanisms as
reliable devices  long burn-in is required
early failures random failures wearout failures
Failure rate

bathtub curve
elevated operating normal operating
temperature temperature

infant
working life wearout Time
morality

Sivanantham S
Four types of testing: 4. Incoming inspection
• Incoming inspection performed by the customer, prior to accepting:
– limited functionality can be tested (test should be fast)
– the application dictates the blocks to be tested in priority

• A sample of incoming devices is selected by the customer for incoming

inspection
– The sample size depends on device quality and system reliability requirements
– The customer must carefully balance the two costs:
• cost of diagnosing and repairing a faulty sytem
• cost of the incoming inspection

• The rule of Ten The cost of discovering a defective chip increases by an

order of magnitude at each successive level of integration, from
die/package, board and system.
1000 Field
System
Test and 100
Board
repair cost 10
Component
1

Product Phase

Sivanantham S
 Types of manufacturing tests
• Wafer sort or probe test
– is performed on full wafers
– faulty chips are marked with a dark spot, and discarded after the wafer is cut
– process control monitoring (PCM) devices are placed on the wafer, and enable
electrical characterization
• Gate threshold
• Polysilicon field threshold
• Poly sheet resistance, etc.
– PCM are located along the wafer,
where gradients may have caused
a variation of electrical parameters
– PCM can be place between ICs,
and are destroyed when the wafer
is diced
• Packaged device tests

PCM Process Control Monitoring C. H. Gebotys, U. Waterloo

structures on-wafer

Sivanantham S
 Subtypes of test
• Parametric
– correct operation of the chip pads must be verified
– all pads must be checked, thus, the test method must be fast
– e.g. DC parametric test: contact test: verifies that the chip pins have no opens
or shorts
IO port protection circuit
VDD
Three healthy IC pads and bonding

R
PAD Core circuit

IO port protection circuit parametric test procedure

1. Set all inputs to 0 V

2. Force current Ifb out of pin (expect Ifb to be 100 to 250 A)
3. Measure pin voltage Vpin. Calculate pin resistance R

• Contact short (R = 0 )
• No problem
• Pin open circuited (R huge), I and V
fb pin large
Sivanantham S
 Subtypes of test (2)
• Functional test

– the correct functionality of the core is validated

– input vectors are applied to the inputs, and the core response is
checked for functional correctness

– this type of test is very long

– allows testing of the all transistors and wires in the core, if the test
covers all possible cases

Sivanantham S
 Engineering economics
Engineering Economics is the study of how engineers choose to optimize their
designs and construction methods to produce objects and systems that will
optimize their efficiency and hence the satisfaction of their clients

M. L. Bushnell, V. D. Agrawal

Sivanantham S
 Costs
Several costs must be considered

• Fixed costs
necessary but do not change with use, are fixed in time, e.g. building,
machinery

• Variable costs
increase with the extent of the production, e.g. labor, energy, raw material

• Total costs
the sum of fixed and variable costs

• Average costs
division of total cost by the number of produced units

Sivanantham S
 Cost of production test (1)
Testing cost  N c  Cs  Tm
Nc = total number of circuits
Cs = cost of testing per second
Tm = mean time of testing per circuit

n
Tm   Ti (1  Pi 1 )
i 1

n = number of test vectors

Ti = processing time for test number i
P(i-1) = probability of a defect to be detected during the
application of tests prior to test i

Sivanantham S
 Cost of production test (2)
1 Tprod ,tot  Tdown ,tot  Tidle ,tot
Cs  ( Dt  Dh  Ct  M t  Ot )  ( )( )
Ttest ,tot Tprod ,tot

total yearly cost testing time (s) occupation rate

Cs = cost of testing per second

Dt, Dh = depreciation of tester and handler
Ct = fixed cost of tester
Mt = maintenance cost
Ot = operating cost and personnel (building, facilities,
auxiliary equipment)
Ttest,tot = testing time
Tprod,tot = usage time of tester per week
Tdown,tot = down time of tester per week
Tidle,tot = idle time of tester per weekS
Sivanantham
 Simple cost analysis
Using an ATE at 1.7M$, with 1024 channels at 2000$ each, we have:
purchase price = 1.7M$ + 1024 x 2000 = 3.748M$

Considering following cost distributions:

Dt, Dh= 20% linear depreciation per year
Mt = 2% of purchase price
Ot = 0.5M$/year

running cost = (3.748M x .2)+(3.748M x .02)+0.5M = 1.325M$/year

The system is operated 24/7:

Tyear = 3600 x 24 x 365 = 31.536Ms

Testing cost: Cs = 1.325M/31.536M = 4.2 cents/s

Sivanantham S
 Simple cost analysis (2)
Test time for an ASIC is equal to 6s:
Tm = 6s

Test cost for one IC:

T m x Cs = 25.2 cents

Bad chips are not sold, their test cost must be recovered from good ones:

yield = 65%

test component of sale price = 27.36/65%  39 cents

Sivanantham S
 Discussion
• Testing is (very) expensive !

– in our example: 39 cents is a significant portion of a chip supposed to

be sold for a few dollars

• In order to reduce testing costs

– reduce Cs: cost of test per second
– reduce Tm: testing time per chip
• limit number of test vectors

– reduce the price of test equipment and maintenance

– increase yield (!)
– increase the operating rate of equipment

Sivanantham S
 VLSI chip yield
• The percentage or fraction of acceptable parts among all parts that
are fabricated is called yield. Yield is denoted by symbol Y.

number of acceptable parts

Y=
total number of parts fabricated

• Cost of a chip:

Cost of fabricating and testing a wafer

Yield • Number of chip sites on the wafer

Sivanantham S
 Yield
• process yield fraction or percentage of acceptable parts among all
fabricated
• wafer yield average number of good chips per wafer; the wafer
yield can be normalized by the number of chip sites on wafer and
used as the process yield

Physical defect Faulty chip

Small dies Unclustered defects Clustered defects (VLSI)

Wafer yield = 117/128 = 0.91 Wafer yield = 22/32 = 0.69 Wafer yield = 25/32 = 0.78

Sivanantham S
 Factors affecting yield
• the area of the die
• the maturity (stability) of the fabrication process, which is directly
linked with the defect density
• the number of steps in the fabrication process

• nevertheless, the exact value of yield is difficult to obtain

– tests are based on fault models that do not detect all faults
– data is difficult to obtain once the product has been sold

Sivanantham S
 Defect level and fault coverage
• defect level DL
the fraction of bad parts that have passed all tests
– is a measure of the quality of tests
– is defined in ppm (parts per million)
– is processed from field returns data

• fault coverage T
ratio of actual number of detected faults over total number of faults
– it is impossible to have fault coverage T=1 in practice
– a model of possible faults is assumed

• defect level, fault coverage and yield are related

(1T )
DL  1  Y

Sivanantham S
 Defect level and fault coverage
• defect level, fault coverage and yield are related

DL  1  Y (1T )
0
1 10

0.9
Y=.01 10
-1

0.8
Y=.1
0.7 -2
Y=.25 10
%

%
0.6
Y=.75
Defect Level

Defect Level
-3 Y=.95
0.5 10
Y=.5
0.4 Y=.99
-4
10
0.3
Y=.7
0.2 -5
10
0.1
Y=.95
-6
0 10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0.97 0.975 0.98 0.985 0.99 0.995 1
Fault Coverage % Fault Coverage %

Sivanantham S
 Practical example
• assuming a fabrication process with
– Y = 0.7
– T = 0.8
we have: DL = 1-0.7(1-0.8) = 0.069

interpretation of this result:

about 7% of all shipped parts are defective

• assuming a DL of 100ppm is required:

100ppm = 0.0001 = 0.01%

T = 1-(log(1-DL)/log(Y)) = .99971 = 99.971% of fault coverage

possible interpretation of this result:

knowing my circuit, I expect that metal lines may be disconnected (this is my
fault model) in one million locations; my test must allow discovering 0.99971e6
of these faults if I want to guarantee that only 0.01% of all shipped parts be
defective

Sivanantham S
 Increasing importance of test

Source: International Business Solutions,

Global System IC (ASSP/ASIC) Service
Management Report, May 2004

in very-deep submicron technologies, e.g. <45nm, functionally

correct chips will fail over time, affected by
– electromigration
– hot-carrier degradation
– oxide breakdown
– soft errors
Sivanantham S
 Discussion
• Testing is (very) expensive !

yes, but doing testing eventually pays off …

– enhance profit
• reduces costs due to repair, warranty maintenance
• increase customer satisfaction
• shorten time-to-market (time-to-volume)
• improve fabrication technology and its reliability
• improve quality of integrated circuits

Sivanantham S
 Additional readings and references
• J. M. Soden, et al, “IC Failure Analysis: Magic, Mystery, and Science,” IEEE Design and Test of
Computers, pp. 59-69, July-September 1997
• C. F. Hawkins, J. Segura, “Test and Reliability: Partners in IC Manufacturing, Part 2,” IEEE
Design and Test of Computers, pp. 64-71, July-September 1999
• C. F. Hawkins, J. Segura, J. Soden, T. Dellin, “Test and Reliability: Partners in IC
Manufacturing, Part 1,” IEEE Design and Test of Computers, pp. 66-73, October-December
1999
• V. D. Agrawal, “A Tale of Two Designs: the Cheapest and the Most Economic,” J. of Electronic
Testing: Theory and Applications, 5, 131-135, 1994
• C. F. Hawkins, H. T. Nagle, R. R. Fritzmeier, J. R. Guth, “The VLSI Circuit Test Problem - A
Tutorial,” IEEE T. Industrial Electronics, Vol. 36, No. 2, pp. 111-116, May 1989
• K. Baker, J. Van Beers, “Shmoo Plotting: The Black Art of IC Testing,” IEEE Design and Test of
Computers, pp. 90-97, July-September 1997
• A. C. Evans, “Applications of Semiconductor Test Economics, and Multisite Testing to Lower
Cost of Test,” International Test Conference, 1999

IC testing tutorial (for reading in a later time)

• R. R. Fritzmeier, H. T. Nagle, C. F. Hawkins, “Fundamentals of Testability - A Tutorial,” IEEE T.
Industrial Electronics, Vol. 36, No. 2, pp. 111-116, May 1989
• A. Grochowski, D. Bhattacharya, T. R. Viswanathan, K. Laker, “Integrated Circuit Testing for
Quality Assurance in Manufacturing: History, Current Status, and Future Trends,” IEEE T. on
Circuits and Systems - II, Vol. 44, No. 8, pp. 610-633, 1997

Sivanantham S
 References
• M. L. Bushnel and W. D. Agrawal, “Essential of Electronic Testing for Digital, Memory, and
Mixed Signal VLSI Circuits,” Springer, 2005
• A. P. Ambler, M. Abadir, S. Sastry, Edts., “Economics of Design and Test for Electronic Circuits
and Systems,” Ellis Horwood Ltd., 1992
• T. Reuter, et al , “Using laser-based patterned-wafer inspection for memory and logic
applications,” Micro pp 89-95, 1999
• D. P. Vallett, IC Failure Analysis: The Importance of Test and Diagnostics,” IEEE Design & Test
of Computers, Vol. 14, No. 3, pp. 76-82, 1997
• T. W. Williams, N. C. Brown, “Defect Level as a Function of Fault Coverage,” IEEE Trans.
Computers, Vol. C-30, No. 12, 1981
• Cadence Design Systems Inc, “The Role of Design in Enhancing Nanometer Process Yield,”
White Paper, http://www.cadence.com/whitepapers/5889_DFMYield_WP_022405.pdf

Sivanantham S