Presentation

on

“FPGA Implementation of Synchronous and

Asynchronous Counter using Reversible Logic
Gates”

Presented by
Harishnaik K.P
Contents
 Introduction
 Objective
 Motivation
 Problem statement
 Solution
 Methodology
 Related work
 System design
 Hardware and software requirements
 System implementation/ Simulation
 Advantages
 Applications
 Conclusion/Future work
 References
Introduction
Reversible Logic:
 Reversible circuits are those circuits that do not erase
information.
 Reversible circuits can generate a unique output vector
from each input vector, and vice versa.
 In reversible circuits, there is a one-to-one mapping
between input and output vectors.
i1 O1
i2 O2 A gate with k inputs
i3 O3
Reversible and k outputs is
Gate called k*k gate.

iK-1 OK-1
iK OK
 cont….
Equal number of input and output vectors.
One or more operation can implement in a single
unit is called Reversible Gate.
Reversible circuit should be designed using min
number of reversible logic gates.
The block diagram of classical XOR and reversible
XOR gate is as shown in figures.
Reversible logic definitions
Parameters for determining the complexity and
performance of circuits
1. The number of Reversible gates (N):
2. The number of constant inputs (CI):
3. The number of garbage outputs (GO):
4. Quantum cost (QC):
 Objective
R.Landauer[1] has shown that for every bit of information
lost in irreversible logic, generates kTln2 joules of heat
energy.
Whenever a logic operation is performed, the computer
erases information. All these operations are irreversible
dissipating a lot of heat.
As Moore's law continues to hold, processing power
doubles every 18 months.
 Cont..
Bennett[2] showed that zero power dissipation in logic
circuits is possible only if a circuit is composed of
reversible logic gates.
Reversible logic operation do not erase(lose) information
and dissipate less heat.
Reversible logic is likely to be in demand in high speed
power circuits.
Reversible circuits are high interest in low power CMOS
design etc..
 Motivation
Reversible circuits dissipate less power than irreversible
circuits.
Reversible circuits can be used as a part of irreversible
computing devices to allow low-power design using
current technologies like CMOS.
Problem statement
 Information loss = Energy loss
The loss of information is associated with laws of
physics requiring that one bit of information lost
dissipates k T ln 2 of energy,
where k is Boltzmann’s constant .
and T is the temperature of the system.
Solution to the problem
Solution = Reversibility
Interest in reversible computation arises
from the desire to reduce heat dissipation,
thereby allowing:
higher densities.
higher speed.
less power dissipation.
Methodology
Specification
Block Diagram
Logic Design
Verilog
Simulation
Synthesis
Implementation
Physical Dumping
Physical Testing
 Related work
 R.Landauer [1] showed the amount of energy dissipated for
every irreversible bit operation is given by KTln2.
 Bennett showed that KTln2 energy dissipation would not
occur, if a computation is carried out in a reversible way[2].
 Edward Fredkin and Tommaso Toffoli introduced new
reversible gates known as Fredkin and Toffoli gates[4,5].
 Peres [6] introduced a new gates known as peres gate.
 Prashanth R Yelekar designed sayem gate used for sequential
circuits[9].
cont..
 H Ranganathan were first invented the D-latch, JK
latch etc [7,8].
 first people to introduce the reversible logic to
sequential circuits in 2011[8].
 Reversible sequential circuit can be constructed by
replacing flip-flops and gates of traditional design by
their reversible counter parts[9].
 All the above works presents reversible design of
latches, flip-flops and counters[8,9,10].
System design
Design Constraints for Reversible Logic Circuits:
I. Avoid leading output signals of gates to more than
one input( Fan-out).
II. Should have minimum quantum cost.
III. Use minimum number of garbage outputs.
IV. Use minimum number of constant inputs.
V. Use minimum logic depth or gate levels.
VI. Use minimum number of reversible gates.
 Basic reversible logic gates
 Feynman Gate:
 The input vector is I (A, B) and
 The output vector is O (P, Q).
 The outputs are defined by P=A, Q=A xor B.
 Quantum cost of a Feynman gate is 1.
A B P Q +
0 0 0 0
A P=A
Feynman 0 1 0 1
Gate
B Q=A B 1 0 1 1
A B
1 1 1 0
Basic reversible logic gates(contd.)
AB C P QR
Fredkin Gate:
0 0 0 0 0 0
 The input vector is I (A, B, C) and
 the output vector is O (P, Q, R). 0 0 1 0 0 1

 The output is P=A, Q=A′B xor AC and 0 1 0 0 1 0

R=A′C xor AB. 0 1 1 0 1 1

 Quantum cost of a Fredkin gate is 5. 1 0 0 1 0 0

1 0 1 1 1 0
1 1 0 1 0 1
1 1 1 1 1 1
Synchronous counters:
The clock inputs of all the flip-flops are connected
together and are triggered by the input pulses.
The most important advantage is that there is no time
delay.
Asynchronous counters
the first flip-flop is clocked by the external clock pulse,
and
then each successive flip-flop is clocked by the Q or Q'
output of the previous flip-flop.
Hardware and software requirements:
 Hardware Requirement specification
Minimum Intel Pentium IV Processor.
Primary memory: 2 GB RAM.
Virtex V FPGA.
Xilinx Vertex V FPGA development board.
JTAG cable, Power supply.
 Software Requirement Specification:
Operating System: Windows 7.
Synthesis Tool: Xilinx 13.1
Simulation Tool: Modelsim6.3c.
System Implementation/ Simulation
T-FF with SG & FG gate:
Used to toggle the o/p
when i/p high & retains the
o/p when i/p is low.
realization of T-ff has two
SG gates and one FG gate.
T QT+1

0 QT
1 QT+
  T-FF with SVS gate:
Used to toggle the o/p
when i/p high & retains the
o/p when i/p is low.
realization of T-ff has only
One gate i.e SVS gate.
T flip flop design No of gates Garbage Constant
outputs inputs

Existing [11](using 3 3 2
SG and FG gate)

Proposed 1 2 1
Design(using SVS
gate)

Improvement factor 3 1.5 2

w.r.t [11]
 Asynchronous counters:
 Proposed 4-bit Asynchronous up Counter:

No of gates Garbage Constant

outputs inputs
Existing [13] 16 17 8
Existing [15] 17 8 9
Existing [16] 15 12 11
Proposed design 7 8 7
Improvement 2.28 2.12 1.14
factor w.r.t [13]
Improvement 2.42 1 1.28
factor w.r.t [15]
Improvement 2.14 1.5 1.57
factor w.r.t [16]
 Proposed 4-bit Asynchronous down Counter:

No of gates Garbage Constant

outputs inputs
Existing [13] 16 17 8
Existing [15] 17 8 9
Existing [16] 15 12 11
Proposed design 7 8 7
Improvement 2.28 2.12 1.14
factor w.r.t [13]
Improvement 2.42 1 1.28
factor w.r.t [15]
Improvement 2.14 1.5 1.57
factor w.r.t [16]
Proposed 4-bit Asynchronous up/down Counter:

No of gates Garbage Constant

outputs inputs

Existing [16] 15 12 11

Existing [13] 19 20 8

Proposed design 7 8 7

Improvement 2.14 1.5 1.57

factor w.r.t [16]

Improvement 2.71 2.5 1.14

factor w.r.t [13]
Synchronous counters:
 Proposed 4-bit Synchronous up Counter:

No of gates Garbage Constant

outputs inputs

Existing [16] 17 18 18

Proposed design 9 12 10
Improvement 1.88 1.5 1.8
factor w.r.t [16]
 Proposed 4-bit Synchronous down Counter:

No of gates Garbage Constant

outputs inputs

Existing [16] 16 16 17
Proposed 7 12 8
design
Improvement 2.28 1.33 2.12
factor w.r.t [16]
FPGA TOP MODULE IMPLEMENTATION:
Cadence power & area analysis:
Instance Cells Leakage(Power(nW)) Dynamic(Power(nW)) Total(Power(nW))

down_counter_async 24 17.615 2125.028 2142.643

up_counter_async 27 17.722 2825.949 2843.671

up_down_counter_async 27 20.299 3969.653 3989.952

up_counter_sync 26 17.630 1471.669 1489.298

down_counter_sync 30 18.935 1993.504 2012.439

Power analysis
Instance Cells Cell Area

down_counter_async 24 91

up_counter_async 27 94

up_down_counter_async 27 102

up_counter_sync 26 95

down_counter_sync 30 100

Area analysis
Advantages
Less power dissipation.
Low power circuits.
High speed.
High performance.
High energy efficiency.
Increases portability of device.
Less delay.
Applications
Low power CMOS.
Quantum computing.
Nanotechnology.
Optical computing.
Signal processing (DSP).
DNA computing.
Computer graphics.
Communication.
Conclusion/Future work
Reversible logic is very important for low power design.
Most of the attempts on reversible logic design concentrate
on reversible combinational logic design.
Only a few attempts were made on reversible sequential
circuit design.
This project has proposed the designs 0f reversible
synchronous and asynchronous counter using reversible T
Flip-flop.
The designs of T-FF and counters are compared with
existing design for 3 parameter and found the
improvement over existing design by factor of 1 to 3.
cont…
The implemented counters power and area is also
calculated by using cadence tool and they all have
low power designs.
The proposed counters designs have applications
in building reversible processor, reversible jonshan
& ring counter etc.
The design can further be extended to develop
efficient reversible counters and reversible
sequential circuit as a future work.
References
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development, pp. 183-191, 1961.
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