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Memory System

The document discusses several topics related to computer memory systems: 1. It describes the basic concepts of memory including maximum size, byte addressability, memory address register (MAR), and memory data register (MDR). 2. It discusses memory access time, memory cycle time, and transfer rate and how cache memory can help address the speed difference between CPU and RAM. 3. It covers different memory cell technologies like static RAM, asynchronous DRAM, and synchronous DRAM and read-only memories like ROM, PROM, EPROM, and flash memory.

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28 views41 pages

Memory System

The document discusses several topics related to computer memory systems: 1. It describes the basic concepts of memory including maximum size, byte addressability, memory address register (MAR), and memory data register (MDR). 2. It discusses memory access time, memory cycle time, and transfer rate and how cache memory can help address the speed difference between CPU and RAM. 3. It covers different memory cell technologies like static RAM, asynchronous DRAM, and synchronous DRAM and read-only memories like ROM, PROM, EPROM, and flash memory.

Uploaded by

musfiqurrahman232
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 41

The Memory System

Dr. Md. Aminul Haque Akhand


Dept. of CSE, KUET
Safwat Zaky-292
William Stallings – page 97
Some Basic Concepts
2

Maximum size- 64K for 16 bit


Byte Addressable – lower-order 2 bits for specific byte

MAR and MDR


3
Some Basic Concepts
 Access time
 Time between presenting the address and getting the valid data
Time between READ and MFC signal.
 Memory Cycle time
 Minimum Time delay between two successive memory
operations.
 Cycle time = access + recovery
 Transfer Rate
 Rate at which data can be moved
CPU process instructions and data faster than they can be fetched

from RAM
Cache memory

 CPU may generate address (based on MAR) that might not exist.
Virtual memory
Some Basic Concepts
4
Cache and Main Memory
Memory Cell Operation
Chip Organization

 Consider an individual memory cell. Select line indicates


if active, Control line indicates read or write.

Control

Cell
Select Data In / Data Out (sense)

Memory Cell Operations


8
Organization of bit cells in a memory chip

16 X 8 organization
9
Organization of 1K X 1 memory chip

Only one bit is select at a time



10
A 16 Megabit DRAM chip
Organization in detail

 Some possible ways to create a 16Mbit chip


 1M of 16 bit words
 16 1Mbit chips, one chip for each bit of the desired 16 bit word
 A 2048 x 2048 x 4bit array. Consider a 4 bit word size, so 4,194,304
addressable locations
 Reduces number of address pins
 Multiplex row address and column address
 This example: 11 pins to address (211=2048), multiplex over the pins twice
to get 22 bits (222 = 4M) for each 4 bit word
 To access memory, first send an address for the row (RAS), then send the
address for the column (CAS). Together this activates the SELECT line.
Need four lines for the Data In/Sense lines.
 Adding one more pin doubles range of values so 4 times the capacity as
we increase the dimensions
Typical 16 Mb DRAM (4M x 4)

A0
A1
…
A21
14
Static Memories
Retain state as long as Vsupply is

available.

6 transistors for a single bit

Costly but faster


15
Asynchronous DRAMS

Timing is controlled
asynchronously

Store bit as a charge of capacitor ;


require refreshing.

One transistor for a single bit

Slower but cheap


16 Synchronous DRAM
17
Read – Only Memories

 ROM
 PROM
 EPROM
 EEPROM
 Flash Memory
Types of ROM

 Written during manufacture


 Very expensive for small runs
 Programmable (once)
 PROM
 Needs special equipment to program
 Read “mostly”
 Erasable Programmable (EPROM)
 Erased by UV
 Electrically Erasable (EEPROM)
 Takes much longer to write than read
 Flash memory
 Erase whole memory electrically

18
Error Correction

 Hard Failure
 Permanent defect
 Soft Error
 Random, non-destructive
 No permanent damage to memory
 Hamming error correcting code one technique for
detecting errors
 Similar to parity bit, but contains enough information to correct
data with single bit errors
Error Correction
 Hard Failure
 Permanent defect
 Soft Error
 Random, non-destructive
 No permanent damage to memory
 Detected using Hamming error correcting code

20
Error Correcting Code Function

21
22
23
24
Speed, Size and Cost
25
Cache Memories

 Locality of reference
 Temporal
 Spatial
 Read or write hit
 Write-through protocol
 Write-back or copy back protocol
 Read miss
 Load-through or early restart
26
Direct Mapping

May arise contention


27
Associative Mapping

Require
associative search
28
Set-Associative Mapping

Depends on set size converts


to direct or associative search
29
Cache Memories

 Valid bit ensure stale data will not exist in the


cache.
30
Example of Mapping Techniques
Assumption
 CPU has separate instruction and data caches
 Cash size = 8 blocks
 Each block = 1 word of 16 bits
 A 4 X 10 array numbers (each occupying 1 word)
 Address 16 bits

Task
 Normalize Elements According to Row
Array Stored in the Memory in Column Order
31
Task : Normalize Row Wise
32

For Only 0th Row

 2nd loop in descending order. Why?


33
Direct Mapping (For 0th Row)

Loop 1 Loop 2

 Tag 16-3=15bits
34
Associative Mapping (For 0th Row)

Loop 1 Loop 2

Tag 16bits
35
Set-Associative Mapping (For 0th Row)
Data cache is organized into two sets and
each holds four blocks/words

Loop 1 Loop 2

Tag 15bits
For Row
0,2,4,6,8

For Row A(0,6) to A(0,9) is available for Loop2


1,3,5,7,9

Six elements must be reloaded


36
Summary from the Example

 Associative Mapping Performs Better


 Set-Associative is the next best

 Full Associative Mapping is expensive to implement, so


Set-Associative is a good practical compromise
Performance Considerations : Interleaving
37

1. Only one Module Involve for


Block Data Transfer

2. Device with DMA may access


information in other modules

1. Consecutive addresses are


located in successive
modules .

2. Access to consecutive
memory location can keep
several module.

3. Must require 2k module


38
Performance Considerations :
Hit Rate and Miss Penaly
Virtual Memories
39
VM: Address Translation
40

Page should not be too


small or too big

Where page table


resides?
VM: Translation Lookaside Buffer(TLB)
41

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