Microprocessor Technologies

(102045610)

MODULE 2
MEMORY AND I/O INTERFACING
 Module 2
• Various types of memories
• Review of logic devices for interfacing, RAM and ROM
• Interfacing with 8085 based systems
• Interfacing input and output devices
• Memory mapped I/O

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ROM Organization

k inputs (address)
2k x n n outputs (data)
ROM

• k inputs – provide address for the memory

• n outputs – data bits of the stored word selected by address
• k address input lines specify 2k words
• ROM does not have data inputs because it does not have write operation.

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SRAM v/s DRAM
Static RAM Dynamic RAM
1. SRAM has lower access time, so it is faster 1. DRAM has higher access time, so it is slower than
compared to DRAM. SRAM.
2. SRAM is costlier than DRAM. 2. DRAM costs less compared to SRAM.
3. SRAM requires constant power supply, which 3. DRAM offers reduced power consumption, due to
means this type of memory consumes more power. the fact that the information is stored in the capacitor.
4. Due to complex internal circuitry, less storage 4. Due to the small internal circuitry in the one-bit
capacity is available compared to the same physical memory cell of DRAM, the large storage capacity is
size of DRAM memory chip. available.
5. SRAM has low packaging density. 5. DRAM has high packaging density.
6. No need to refresh periodically. 6. Due to capacitor used as storage element,
information may lose over period of time. So, need to
refresh periodically.
7. Uses an array of 6 transistors for each memory 7. Uses a single transistor and capacitor for each
cell. memory cell.

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RAM v/s ROM
RAM ROM
The data is not permanent but it
The data is permanent. It can be altered but only a
Data can be altered any number of
limited number of times that too at slow speed.
times.
Speed It is a high-speed memory. It is much slower than the RAM.

CPU The CPU can access the data The CPU can not access the data stored on it. In
Interaction stored on it. order to do so, the data is first copied to the RAM.

Size and
Large size with higher capacity. Small size with less capacity.
Capacity
Firmware like BIOS or UEFI. RFID tags,
Primary memory (DRAM DIMM microcontrollers, medical devices, and at places
Usage
modules), CPU Cache (SRAM). where a small and permanent memory solution is
required.
Cost It doesn’t come cheap. Way cheaper than RAM.
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Magnetic Disk Floppy Disk

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Hard Disk Optical Disk

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 Memory structure

Block diagram of Memory Device: RAM

N=Number of Register
Data Inputs M=Word Length
E.g.
WR If a memory is having
Input Buffer
CS address lines=13
A10
Internal Decoder

data lines=8
then
Address NXM 1. number of registers / memory
Input Memory locations = N=213 = 8192
2. word length M= 8 bit
A0 Therefore, N X M= 8192 X 8
Output Buffer
RD

Data Output

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Memory structure

No. of Lines Memory size(bytes) No. of Lines Memory size(bytes)

1 2 9 512
2 4 10 1024=1k
3 8 11 2048=2k
4 16 12 4096=4k
5 32 13 8192=8k
6 64 14 16384=16k
7 128 15 32768=32k
8 256 16 65536=64k

IC available for IC available for RAM

EPROM 6116-2k*8
2716-2k*8 6204-8k*8
2732-4k*8 21114-1k*4
2764-8k*8
27128-16k*8
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Memory Interfacing

• 8085 can access 64K of memory, thus address bus is of 16-bit.

• But it is not always necessary to use full 64K address space. The total memory size
depends upon the application.
• Generally EPROM is used as a program memory and RAM is used as data memory.
• When both are used then total 64K address will be shared by both.
• The capacity of program memory and data memory depends on the application.

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Memory Interfacing

• It is not always necessary to select 1 EPROM and 1 RAM. We can have

multiple EPROMs and multiple RAMs as per the requirement of application.
• We can place EPROM / RAM anywhere in full 64 Kbytes address space.
• But program memory (EPROM) should be located from address 0000H,
since reset address of 8085 microprocessor is 0000H.
• It is not always necessary to locate EPROM and RAM in consecutive
memory addresses.

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Memory Interfacing: Example 1
Interface 4kB of EPROM with starting address from 0000H and 2kB of RAM with starting
address followed by EPROM
Step-1:
Total EPROM required = 4kB
Chip size available = 4kB
No. of chips required = 4kB/4kB=1

Total RAM required = 2kB

Chip Size Available = 2kB
No. of Chips required = 2kB/2kB=1

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Memory Interfacing: Example 1

Step-2:

EPROM Chip-1:

Starting Address = 0000H

Chip Size = 4kB (i.e. address Line=12, m/m = 2 12 = 4096B = 4k)

Ending Address = 0FFFH

Step-3:

RAM Chip-1:

Starting address = Ending address of EPROM +1

= 0FFFH+1

= 1000H

Chip Size = 2kB = 07FFH

Ending address = 1000H+07FFH

= 17FFH
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 Memory Interfacing: Example 1
Step-4: Memory A A A A A A A A A A A A A A A A
Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EPRO 0000 H
M End
4k
Address
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
0FFF H
Start
Address 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
RAM 1000 H
2k End
Address 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1
17FF H

EPROM chip size = 4kB & RAM chip size = 2kB

∴smaller chip size RAM = 2kB = 211
Thus neglect lower 11 address lines (A0 to A10), and consider A11 to A15 for Decoding.
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Memory Interfacing: Example 1
A A A A A A A A A A A A A A A A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Addres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
s
EPRO 0000 H
M End
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Addres
s
0FFF H

EPROM
• Required Address Lines: A11 to A15.
• Now, EPROM has two Possibilities, either 00000 b or
00001 b.
• Therefore, it requires Y0 and Y1 outputs of decoder.

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Memory Interfacing: Example 1
A A A A A A A A A A A A A A A A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Addres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
s
EPRO 0000 H
M End
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Addres
s
Start
0FFF H
Addres 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
s
1000 H
RAM
End 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1
Addres
s
RAM has 17FF
00010 H b, hence it requires Y2 output of
decoder.

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 Memory Interfacing: Example 1 Implementation
Step-
5: R
D
IO/
M
A0 -
W O
E A10
R
R
D
EPROM
D0
-
Y 000 D7
00 To
A15 Y
0
000 EPROM
A14 1
Y 01 To D0 – A0 -
A13 5:32 000
Decoder 2 10 RAM D7 A10
A12 O RAM
E
A11

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Memory Interfacing: Example 2
Interface 16kB of EPROM with chip size of 8kB and starting address from 0000H and 8kB of RAM with
starting address followed by EPROM.
Step-1:
Total EPROM required =16kB
Chip size available = 8kB
No. of chips required = 16kB/8kB = 2

Total RAM required = 8kB

Chip size available = 8kB
No. of chips required = 8kB/8kB = 1

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Memory Interfacing: Example 2
Step-2: EPROM Chip-1:
Starting Address = 0000H
Chip Size = 8kB (i.e. address Line=13, m/m=213 =8192B =8k)
Ending Address = 1FFFH

EPROM Chip-2:
Starting Address =1FFFH + 1 = 2000H
Chip Size = 1FFFH
Ending Address = 2000+1FFFH = 3FFFH

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Memory Interfacing: Example 2
Step-3: RAM Chip-1:
Starting Address = EPROM ending address + 1
Starting Address = 3FFFH+1 = 4000H
Chip Size = 8kB (i.e. address Line =13, m/m=213 = 8192B =8k)
Chip Size = 1FFFH
Ending Address = 4000h+1FFFH = 5FFFH

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Memory Interfacing: Example 2
Step-4: Memory A A A A A A A A A A A A A A A A
Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EPRO 0000 H
M1 End
Address
1FFF H
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Start
Address 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
EPRO 2000 H
M End
2 Address 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3FFF H
Start
Address 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4000 H
RAM End
Address 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
5FFF H

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Memory Interfacing: Example 2
Step-5:Interface Implementation
• EPROM chip size = RAM chip size = 8kB = 213

• Therefore, neglect lower 13 address lines (i.e. A 0 to A12) and consider only A13 to
A15 for decoding.

EPROM CHIP-01 000

EPROM CHIP-02 001
RAM CHIP-01 010 Y0 To EPROM Chip-1
Y1 To EPROM Chip-2

A15 Y2 To RAM Chip-1

3:8
A14 Decoder
A13

Y7

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Memory Interfacing: Example 2
Step-4: Memory A A A A A A A A A A A A A A A A
Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EPRO 0000 H
M1 End
Address
1FFF H
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Start
Address 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
EPRO 2000 H
M End
2 Address 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3FFF H
Start
Address 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4000 H
RAM End
Address 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
5FFF H

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 Memory Interfacing: Example 2 Implementation
Step-5:
RD
A0 - A12
OE
IO/M
EPROM
CHIP-1
WR D0
RD -
D7

D0 – D7 A0 - A12

Y0 000 To EPROM CHIP-1 OE

EPROM
Y1 001 To EPROM CHIP-2 CHIP-2
A15
Y2 010 To RAM
A14 3:8
Decoder
A13
D0 – D7 A0 - A12

OE RAM

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Exercise: Memory Interface Example
1. Draw the interfacing of a 4KB EPROM having a starting address 2000h and two 2KB static RAMs
having starting addresses 4000h and 8000h, respectively, with 8085 microprocessor.
2. Design an 8085 microprocessor system such that it should contain 16KB of EPROM and 4KB of RAM
with starting addresses 0000H and 4000H respectively. Use two 8KB of EPROMs (2764) and two 2KB
of RAMs (6116) for this system.

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Exercise: Example 1
Step-4: Memory A A A A A A A A A A A A A A A A
Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Address 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
EPRO 2000 H
M1 End
Address
2FFF H
0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1
Start
Address 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4000 H
RAM 1 End
Address 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1
47FF H
Start
Address 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8000 H
RAM 2 End
Address 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
87FF H

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 Exercise: Example 1
Step-5:
RD
A0 - A12
OE
IO/M
EPROM
CHIP
WR D0
RD -
D7

D0 – D7 A0 - A12

Y0 00100 OE
To EPROM
Y1 RAM-1
00101
A15
Y2 To RAM-1
A14 5:32 01000
A13 Decoder
Y3 To RAM-2
A12 10000
D0 – D7 A0 - A12
A11
OE RAM-2

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Exercise: Example 2
Step-4: Memory A A A A A A A A A A A A A A A A
Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EPRO 0000 H
M1 End
Address
1FFF H
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Start
Address 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
EPRO 2000 H
M2 End
Address 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3FFF H
Start
Address 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4000 H
RAM 1 End
Address 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1
47FF H
Start
Address 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0
4800 H
RAM 2 End
Address 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
4FFF H
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 Exercise: Example 2
Step-5: A0 - A10
RD OE

IO/M D0 EPROM-1
-
D7
WR
RD A0 - A10
OE

D0 EPROM-2
-
D7
Y0 00011
EPROM-1
Y 00000
1
D0 – D7 A0 - A10

A15 00100 OE
RAM-1
A14 5:32 EPROM-2
Y2 00111
A13 Decoder
A12 Y3 01000 To RAM-1
A11
A0 - A10
Y4 10000 To RAM-2
D0 – D7

OE RAM-2

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IO Interfacing

What do you mean by I/O Interfacing?

• There are various communication devices like the keyboard, mouse, printer, etc.
• So, we need to interface the keyboard and other devices with the microprocessor by using
latches and buffers.
• This type of interfacing is known as I/O interfacing.

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8085 Interfacing Pins
Following is the list of 8085 pins used for interfacing with other
devices:

1. A15-A8 (Higher Address Bus)

2. AD7-AD0(Lower Address/Data Bus)

3. ALE
4. RD
5. WR
6. READY

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Ways of Communication with Microprocessor
There are two ways of communication in which the microprocessor can connect with the outside
world.
1. Serial Communication Interface

In this type of communication, the interface gets a single bit of data from the microprocessor
and sends it bit by bit to the other system serially and vice-a-versa.

2. Parallel Communication Interface

In this type of communication, the interface gets a byte of data from the microprocessor and
sends it bit by bit to the other systems in simultaneous (or) parallel fashion and vice-a-versa.

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