Microprocessor Technologies

(102045610)

MODULE 3
INSTRUCTION SET AND ASSEMBLY LANGUAGE
PROGRAMMING
 Module 3
• Classification of instructions
• Addressing Modes
• 8085 Instruction Set, Instruction And Data Formats
• Writing 8085 assembly language programs with decision,making and looping
using data transfer, arithmetic, logical and branch instructions,
• Timing diagram of instructions

2
Hierarchy of
Languages Application
Program

Machine Independent
High Level High Level
Language Language
Machine Low Level Language
Specific Assembly
Language
MOV • Assembly
1100 Machine language
BL,05h
1011 Language is a
ADD CL 0100
1100
MUL BH 1111
1110
Micro Program low-level • Native to a
Control programming processor:
language executed
Hardware designed directly by
for a hardware
specific • Instructions
type of processor. consist of
3
• Uses symbolic binary code: 1s
3
Compilers and
Assemblers
High Level Language

Compile
r

Compile Assembly Language

r
Assemble
r

Machine Language
Assemblers translates assembly code to machine
code
Compilers translate high-level programs to machine code
either directly, or Indirectly via an assembler
4 4
Instructions and Machine
Language
• Each command of a program is called an instruction (it instructs the computer, what to
do?).

• Computers only deal with binary data, hence the instructions must be in binary format
(0’s and 1’s).

• Therefore, each Opcode is having unique bit pattern of (0’s and 1’s).

5 5
Instruction
Fields
• Assembly language instructions usually are made up of several fields.
• Each field specifies different information.
The major two fields are:
1. Opcode: Operation code that specifies operation to be
performed. Each operation has its unique opcode.
2. Operands: Fields which specify, where to get the source and destination operands
for
the operation specified by the opcode.

6 6
Instruction Fields
Opcode Operand
MOV Rd,
Rs M,
Rs R,
M

Rd → Destination
Register Rs → Source
Register
M → Memory
Translating
Languages
English: Sum of A and B

High-Level Language: A + B

A statement in a high-level language is translated

typically into several machine-level instructions

Assembly Language: Machine Language:

MVIA,02 1001 1011 0010

MVI 1001 1001 0011

B,03 1011 0011 0010

ADD B

8 8
Advantages of High-Level
Languages
• Program development is faster
• High-level statements: fewer instructions to code.
• Program maintenance is easier
• As Higher Level Language contains fewer instruction code.
• Programs are portable
• Contain few machine-dependent details.
• Can be used with little or no modifications on different
machines.
• Compiler translates to the target machine language.

9 9
Why to Learn Assembly
Language?
• Accessibility to system hardware
• Assembly Language is useful for implementing system
software.
• It is also useful for small embedded system applications.

• Space and Time efficiency

• Understanding sources of program efficiency.
• Tuning program performance.
• Writing compact code.

• It is helpful for
• Compiler writing
• Programming microcontrollers
• Device drivers
• System design
• Low-level numeric routines 10 10
Why to Learn Assembly
Language?
• Writing assembly programs gives the computer designer, deep
understanding of the instruction set and how todesign.
• To be able to write compilers for HLL (Higher Level Language), we need to
be expert with the machine language. Assembly programming provides such
experience.

11 11
Assembly Language Programming Tools
1. Assembler
2. Linker
3. Debugger
4. Editor

12 12
Assemble
r• An assembler is a program that converts programs written in assembly language
into
object files(machine language).
• Popular assemblers have emerged over the years for the Intel family of
processors. These include …
• TASM (Turbo Assembler from Borland).
• NASM (Net wide Assembler for both Windows and Linux), and
• GNU assembler distributed by the free software foundation.

13 13
Linker
• A linker program is required to produce executablefiles.
• It combines program's object file created by the assembler with other
object files and link libraries, to produces a single executableprogram.

14
Assembly Language Programming Tools
Assemble and Link
Process
Source Object
File Assemble File
r

Source Object Executable

File Assemble File Linker
File
r

Source Object Link

File Assemble File Libraries
r

A project may consist of multiple source files

Assembler translates each source file separately into an object
file
Linker links all object files together with link libraries
15
Debugger
• Allows you to trace the execution of a program.
• Allows you to view code, memory, registers, etc.
• Example: WinDbg, GDB - the GNU debugger,
etc.

16 16
Editor
• Allows to create assembly language source files.
• Some editors provide syntax highlighting features and can be
customized as per programming environment.

17
 Classification of 8085
Instructions

Based on Byte Size Based on Function

One-byte Instructions Data Transfer
Requires one memory Instructions
location to perform an
Arithmetic
operation
Instructions
E.g. CMA, ADD
Two-byte Instructions Logic & Bit
Requires two memory Manipulation
locations to perform an Instructions
operation Branch Instructions
E.g. MVI A,32H
Control
Three-byte
Instructions
Instructions
Requires three memory
locations to perform an
operation
E.g. JMP, CALL 18
18
Classification of 8085
instructions
• An instruction is a binary pattern designed inside a microprocessorto
perform a specific function.
• Each instruction is represented by an 8-bit binary value called Op-
Code.
• The entire group of instructions that a microprocessor supports isknown
as an Instruction Set.

19 19
Classification of 8085
instructions
Instruction Set
• It is the set of instructions that the microprocessor can understand.
Opcode
• Known as Operation Code.
• This required field contains the mnemonic operation code for the 8085
instruction.
Operand
• The operand field identifies the data to be operated on by the specified opcode.
• Some instructions require no operands, while others require one or two operands.
MVI D, 8BH

Opcode Operand
20 20
Classification of 8085
instructions
General
Terms
R 8085 8-bit register (A, B, C, D, E, H, L)
M Memory
Rs Register Source
Rd Register Destination
Rp Register Pair (BC, DE, HL)

21 21
One-byte
Instruction
One-byte instructions includes Opcode and Operand in the same
byte.
Instruction Binary Code Hexa Code
Opcode Operand
MOV C,A 0100 1111 4FH
ADD B 1000 0000 80H
CMA 0010 1111 2FH

22 22
List of one-byte
Instructions
Sr. Instruction Sr. Instruction Sr. Instruction Sr. Instruction
1 MOV dest.,src 13 SBB R/M 25 RNZ 37 CMA
2 LDAX RP (B/D) 14 INR R/M 26 RPE 38 CMC
3 STAX RP 15 INX RP 27 RPO 39 STC
4 XCHG 16 DCR R/M 28 RST 0-7 40 NOP
5 SPHL 17 DCX RP 29 CMP R/M 41 HLT
6 XTHL 18 DAA 30 ANA R/M 42 DI
7 PUSH RP 19 RET 31 XRA R/M 43 EI
8 POP RP 20 RC 32 ORA R/M 44 RIM
9 ADD R/M 21 RNC 33 RLC 45 SIM
10 ADC R/M 22 RP 34 RRC
11 DAD 23 RM 35 RAL
12 SUB R/M 24 RZ 36 RAR

23 23
 Two-byte
Instruction
In two-byte instruction,
1st Byte : Specifies Opcode
2nd Byte: Specifies
Operand
Instruction Binary Code Hexa Code
Opcode Operand
MVI A,32H 0011 1110 3E: 1st Byte
0011 0010 32: 2nd Byte
MVI B,F2H 0011 1110 3E: 1st Byte
1111 0010 F2: 2nd Byte
IN 0AH 1101 1011 DB: 1st Byte
0000 1010 0A: 2nd Byte

24
List of two-byte
Instructions Sr. Instruction
1 MVI destination,8-bit data
2 OUT 8-bit port address
3 IN 8-bit port address
4 ADI 8-bit data
5 ACI 8-bit data
6 SUI 8-bit data
7 SBI 8-bit data
8 CPI 8-bit data
9 ANI 8-bit data
10 XRI 8-bit data
11 ORI 8-bit data

25 25
Three-byte
Instruction
In three-byte instruction,
1st Byte: Specifies Opcode
2nd Byte: Specifies lower order 8-bit
Byte: Specifies higher order 8-bit
address
3rd
address

Instruction Binary Code Hexa Code

Opcode Operand
LDA 2050H 0011 1010 3A: 1st Byte
0101 0000 50: 2nd Byte
0010 0000 20: 3rd Byte
JMP 2085H 1100 0011 C3: 1st Byte
1000 0101 85: 2nd Byte
0010 0000 20: 3rd Byte

26 26
List of three-byte
Instructions
Sr. Instruction Sr. Instruction
1 LDA 16-bit address 13 JPE 16-bit address
2 LXI Rp, 16-bit data 14 JPO 16-bit address
3 LHLD 16-bit address 15 CALL 16-bit address
4 STA 16-bit address 16 CC 16-bit address
5 SHLD 16-bit address 17 CNC 16-bit address
6 JMP 16-bit address 18 CP 16-bit address
7 JC 16-bit address 19 CM 16-bit address
8 JNC 16-bit address 20 CZ 16-bit address
9 JP 16-bit address 21 CNZ 16-bit address
10 JM 16-bit address 22 CPE 16-bit address
11 JZ 16-bit address 23 CPO 16-bit address
12 JNZ 16-bit address

27

27
 Instruction Set of 8085
• An instruction is a binary pattern designed
insidea microprocessor to perform a specific
function.
• T h e entire group of instructions that a
microprocessor supports is called Instruction
Set.
• 8085 has 246 instructions.

• Each instruction is represented by an 8-bit

binary value.
•
These8-bits of binary value is called Op-Code or
Instruction Byte.
Classification of Instruction Set

•
Data Transfer Instruction
•
Arithmetic Instructions
•
Logical Instructions
•
Branching Instructions
•
Control Instructions
1.Data Transfer Instructions
•
These instructions move data between
registers, or between memory and
registers.
•
These instructions copy data from source
to destination(without changing the
original data ).
 MOV-Copy from source to destination
Opcode Operand
Rd,
MO Rs
V M, Rs
Rd,
• T h i s instruction copies the contents of the source
M
register into the destination register. (contents of the
source register are not altered)

• If one of the operands is a memory location, its

location is specified by the contents of the HL
registers.
BEFORE AFTER EXECUTION
EXECUTION
A 20 B MOV A 20
B,A B 20

A F A F
B 30 C B 30 C
MOV M,B
D E D E
H 20 L 50 H 20 L 50 30

A F A F
B C B C 40
D E MOV C,M
D E
H 20 L 50 40 H 20 L 50 40
 MVI-Move immediate 8-
bit
Opcode Operand

MV Rd,
Data
I M, Data
• T h e 8-bit data is stored in the destination
registeror memory.

• If the operand is a memory location, its

location isspecified by the contents of
the H-L registers.

•
Example: MVI B, 60H or MVI M, 40H
 BEFORE EXECUTION AFTER EXECUTION

A F A F
B C MVI B 60 C
D E B,60H D E
H L H L

BEFORE EXECUTION AFTER EXECUTION

204FH 204F

HL=2050 HL=2050 40
MVI
2051H M,40H 2051H
 LDA-Load
accumulator
Opcode Operand

LD 16-bit address

A
• T h e contents of a memory location, specified by
a16- bit address in the operand, are copied to the
accumulator.

• T h e contents of the source are notaltered.

•
Example: LDA 2000H
BEFORE EXECUTION AFTER EXECUTION

A
A
30
LDA 30
2000H 30
2000H
2000H
LDAX-Load accumulator
indirect
Opcode Operand
LDA B/D Register
Pair
X

• T h e contents of the designated register pair point to a memory

location.

• T h i s instruction copies the contents of that memory location into

the accumulator.

• T h e contents of either the register pair or the memory locationare

not altered.

Example: LDAX
•
D
 BEFORE EXECUTION AFTER EXECUTION

A F A 80

B C B F C 80
2030H 80 2030H
LDAX D
D 20 D 20 E
E 30
30
 LXI-Load register pair
immediate
Opcode Operand
LX Reg. pair, 16-bit
data
I

•
This instruction loads 16-bit data in the register pair.

•
Example: LXI H, 2030 H
 BEFORE EXECUTION AFTER EXECUTION

A F A 80 F

B C B C
2030H 30 9030H 50
LXI
H L H, H 90 L 30
2031H 90 2030

M=50
 LHLD-Load H and L registers
directOpcode Operand
LHL 16-bit address
D

• T h i s instruction copies the contents of memory

location pointed out by 16-bit address into register
L.

• It copies the contents of next memory

location into register H.

•
Example: LHLD 2030 H
 BEFORE EXECUTION AFTER EXECUTION

A F A 80 F

B C B C
2030H 00 8500H 60
LHLD
H L 85 H 85 L 00
2030

M=60
 STA-Store accumulator direct
Opcode Operand
ST 16-bit address
A
•
T h e contents of accumulator are copied
intothe memory location specified by the
operand.
• E x ample: STA
2000 H
BEFORE EXECUTION AFTER EXECUTION

A A
50
50
STA 50
2000H 2000H
2000H
 STAX-Store accumulator indirect
Opcode Operand

STA Reg.
X pair

•
T h e contents of accumulator are copied into the
memory location specified by the contents of the
register pair.

•
Example: STAX B

collected by C.Gokul AP/EEE , Velalar college of Engineering and Technology,

BEFORE EXECUTION AFTER EXECUTION

B 85 C
00
8500H 1A
A=1AH STAX B
 SHLD-Store H and L registers direct
Opcode Operand
SHLD 16-bit address

• T h e contents of register L are stored

intomemory location specified by the 16-bit
address.

• T h e contents of register H are stored into

thenext memory location.

•
Example: SHLD 2550H
BEFORE EXECUTION AFTER EXECUTION

D E
8500H 80
H 70 L 80 SHLD
8501H 70
8500
XCHG-Exchange H and L with D and
E
Opcode Operand
XCHG None

• T h e contents of register H are exchanged

withthe contents of register D.

• T h e contents of register L are exchanged

withthe contents of register E.

Example: XCHG
•
BEFORE EXECUTION AFTER EXECUTION

D 20 40 D 70 E 80
E
XCHG
H 70 80 H 20 L 40
L
 SPHL-Copy H and L registers to the
stack pointer
Opcode Operand

SPH None

L
•
T h i s instruction loads the contents of H-L
pairinto SP.

•
Example: SPHL
 BEFORE EXECUTION

SP
H 25 L 00

SPHL
AFTER EXECUTION
SP 2500
H 25 L 00
 XTHL-Exchange H and L with top
of stack
Opcode Operand
XTHL None

• T h e contents of L register are exchanged with

the location pointed out by the contents of the
SP.

• T h e contents of H register are exchanged

withthe next location (SP + 1).

Example: XTHL
•
 L=SP
H=(SP+1)

BEFORE EXECUTION AFTER EXECUTION

SP 2700
2700H 50 SP 2700
40
2700H
H 30 L H L

40 2701H 60 50
30
60 2701H
XTHL
2702H
2702H
Opcode Operand Description
PCHL None Load program counter with H-
L contents

• T h e contents of registers H and L are copied

intothe program counter (PC).

• T h e contents of H are placed as the high-

orderbyte and the contents of L as the low-order
byte.

•
Example: PCHL
 PUSH-Push register pair onto stack
Opcode Operand
PUSH Reg. pair

• T h e contents of register pair are copied ontostack.

• SP is decremented and the contents of high-order

registers (B, D, H, A) are copied into stack.

• SP is again decremented and the contents of low-

order registers (C, E, L, Flags) are copied into stack.

•
Example: PUSH B
PUSH
H
 POP- Pop stack to register pair

Opcode Operand
POP Reg. pair

• T h e contents of top of stack are copied into register

pair.

• T h e contents of location pointed out by SP are copied to

the
low-order register (C, E, L, Flags).

• SP is incremented and the contents of location are

copied to the high-order register (B, D, H,A).
POP H
 IN- Copy data to accumulator from a
port with 8-bit address
Opcode Operand
I 8-bit port address
N
•
T h e contents of I/O port are copied intoaccumulator.

•
Example: IN 8C H
 BEFORE EXECUTION

PORT 10 A
80H

IN 80H
AFTER EXECUTION

PORT
10 A
80H 10
 OUT- Copy data from accumulator to
a port with 8-bit address
Opcode Operand
OUT 8-bit port address
•
T h e contents of accumulator are copied into
theI/O port.

• E x ample:
OUT 78H
 BEFORE EXECUTION

PORT 10 A 40
50H

OUT
50H
AFTER EXECUTION

PORT 40 A 40
50H
2.Arithmetic Instructions
•
These instructions perform the
operations like:
◦ Addition

◦ Subtract

◦ Increment

◦ Decrement
 Addition
• A n y 8-bit number, or the contents of register, or
the contents of memory location can be added to
the contents of accumulator.

• T h e result (sum) is stored in the accumulator.

• N o two other 8-bit registers can be

added directly.

• Example: The contents of register B

cannot be added directly to the contents of
register C.
 ADD

Opcode Operand Description

ADD R Add register or memory to
accumulator
M
• T h e contents of register or memory are added to
the contents of accumulator.

• T h e result is stored inaccumulator.

• If the operand is memory location, its address is

specified by
H-L pair.

•
 BEFORE EXECUTION AFTER EXECUTION
A
04 A. 09
B C B. C 05
05
D E
ADD C D E
H L
H L

A=A+C 04+05=09

BEFORE EXECUTION
AFTER EXECUTION

A 04
ADD M A 14
B C B C
D E D E
H 20
L
50
10 A=A+M H 20
L
50 10

2050 04+10=14 2050

 ADC

Opcode Operand Description

ADC R Add register or memory to
accumulator with carry
M
• The contents of register or memory and Carry Flag (CY) are added to the
contents of accumulator.

• The result is stored in accumulator.

• If the operand is memory location, its address is specified by H-L pair.

• All flags are modified to reflect the result of the addition.

• Example: ADC B or ADC M

 BEFORE EXECUTION AFTER EXECUTION

CY
01
A 50 A
B C
56
B C 20
05 ADC C D E
D E A=A+C+CY H L
H L

50+05+01=56
BEFORE EXECUTION AFTER EXECUTION

CY 1
A 06 2050H 30 ADC M A 37 2050H 30

H 20 L 50
A=A+M+CY
H 20 50
L
 AD
I
Opcode Operand Description
ADI 8-bit data Add immediate to accumulator

• T h e 8-bit data is added to the

contentsof accumulator.

• T h e result is stored inaccumulator.

• A l l flags are modified to reflect the result of

the addition.

•
Example: ADI 45 H
BEFORE EXECUTION AFTER EXECUTION

A 03 ADI 05H A 08
A=A+DATA(8)
03+05=08

collected by C.Gokul AP/EEE , Velalar college of Engineering and Technology,

 AC
I
Opcode Operand Description

ACI 8-bit data Add immediate to

accumulator with carry
• T h e 8-bit data and the Carry Flag (CY) are
addedto the contents of accumulator.

• T h e result is stored inaccumulator.

• A l l flags are modified to reflect the result of

the addition.

•
Example: ACI 45 H
BEFORE EXECUTION AFTER EXECUTION

CY 1 ACI 20H
A 05 A=A+DATA A 26
(8)+CY 05+20+1=26
 DAD
Opcode Operand Description
DAD Reg. pair Add register pair to H-L pair

• T h e 16-bit contents of the register pair are added to

the contents of H-L pair.

• T h e result is stored in H-Lpair.

• If the result is larger than 16 bits, thenCY is set.

• No other flags are changed.

•
Example: DAD B or DAD D
 BEFORE EXECUTION AFTER EXECUTION

D 12 E 34 D 12 E 34

H 23 L 45 DAD D H 35 L 79

1234
2345
DAD HL=HL+DE
+ D HL=HL+BC
 Subtraction
• A n y 8-bit number, or the contents of
register,or the contents of memory location can
be subtracted from the contents of accumulator.

• T h e result is stored in the accumulator.

•
Subtraction is performed in 2’s complement
form.

• If the result is negative, it is stored

in 2’s complement form.

• N o two other 8-bit registers can

besubtracted directly.
 SU
B
Opcode Operand Description
SUB R Subtract register or memory
from accumulator
M
• T h e contents of the register or memory location are
subtracted from the contents of the accumulator.

• T h e result is stored inaccumulator.

• If the operand is memory location, its address is

specified by H-L pair.

• Al l flags are modified to reflect the result of subtraction.

•
Example: SUB B or SUB M
 BEFORE EXECUTION AFTER EXECUTION
A
09 A. 05
B C B. C 04
04
D E
SUB C D E

H L A=A- H L

C 09-04=05

BEFORE EXECUTION
AFTER EXECUTION

A 14
SUB M A 04
B
D
C
E
A=A- B
D
C
E

10 M
H 20 50 H 20 50 10
L L
2050 14-10=04 2050
 SB
B
Opcode Operand Description
SBB R Subtract register or memory
from accumulator with borrow
M

• The contents of the register or memory location and Borrow Flag (i.e.
CY) are subtracted from the contents of the accumulator.

• The result is stored in accumulator.

• If the operand is memory location, its address is specified by H-L pair.

• All flags are modified to reflect the result of subtraction.

• Example: SBB B or SBB M

 BEFORE EXECUTION AFTER EXECUTION

CY
01
A 08 A
B C
02
B C 05
05
D E
SBB C D E
H L
H L A=A-C-CY
08-05-01=02

BEFORE EXECUTION AFTER EXECUTION

CY 1
A 06 2050H 02 SBB M A 03 2050H 02

H 20 L 50 A=A-M-CY H 20 50
L
 SU
I
Opcode Operand Description

SUI 8-bit data Subtract immediate from

accumulator

• T h e 8-bit data is subtracted from the contents of

the accumulator.

• T h e result is stored inaccumulator.

• A l l flags are modified to reflect the result of

subtraction.

•
Example: SUI 05H
BEFORE EXECUTION AFTER EXECUTION

A 08 SUI 05H A 03
A=A-DATA(8)

08-05=03
 SB
IOpcode Operand Description
SB 8-bit data Subtract immediate from
I accumulator with borrow

• T h e 8-bit data and the Borrow Flag (i.e. CY) is

subtracted from the contents of the accumulator.

• T h e result is stored inaccumulator.

• A l l flags are modified to reflect the result of

subtraction.

•
Example: SBI 45 H collected by C.Gokul
BEFORE EXECUTION AFTER EXECUTION

CY
1 SBI 20H
A 25 A=A-DATA A 04
(8)-CY
25-20-01=04
 Increment / Decrement
• T h e 8-bit contents of a register or a
memory location can be incremented or
decremented by 1.

• T h e 16-bit contents of a register pair

can be incremented or decremented by
1.
•
Increment or decrement can be
performed on any register or a memory
location.
IN
R
Opcode Operand Description
INR R Increment register or
memory by 1
M
• T h e contents of register or memory location are
incremented by 1.

• T h e result is stored in the same place.

• If the operand is a memory location, its address is

specified by
the contents of H-L pair.

•
 BEFORE EXECUTION AFTER EXECUTION

A
A A
B
B 10
1 C
C INR B B 11 C
0 E
D
D
H
H
E
L
L
R=R+1 D
H
E
L

10+1=11
BEFORE EXECUTION AFTER EXECUTION

H L
2050H 10 H L
11 2050H
20 50
INR M 20 50

M=M+1 10+1=11
 IN
X
Opcode Operand Description
INX R Increment register pair by 1

• T h e contents of register pair are incremented

by1.

• T h e result is stored in the sameplace.

•
Example: INX H or INX B or INX D
BEFORE EXECUTION AFTER EXECUTION

SP
SP

B C B C
D E INX H D E
H 10 L 20 RP=RP+1 H 10 L 21

1020+1=1021
 DCR

Opcode Operand Description

DCR R Decrement register or
memory by 1
M
• T h e contents of register or memory location
are decremented by 1.

• T h e result is stored in the same place.

• If the operand is a memory location, its address is

specified by
the contents of H-L pair.

•
 BEFORE EXECUTION AFTER EXECUTION

A A
B C B C
D E 20 DCR E D E 19
H L R=R- H L

1 20-1=19
BEFORE EXECUTION AFTER EXECUTION

H L
H L 2050H
21 20 50 2050H 20
20 50 DCR M
M=M-1 21-1=20
 DCX

Opcode Operand Description

DCX R Decrement register pair by 1

• T h e contents of register pair are decremented

by1.

• T h e result is stored in the sameplace.

•
Example: DCX H or DCX B or DCX D
BEFORE EXECUTION AFTER EXECUTION

SP
SP

B C B C
D E DCX H D E
H 10 L 21 RP=RP-1 H 10 L 20
 3.Logical Instructions
•
These instructions perform logical operations on
data stored in registers, memory and status
flags.

• T h e logical operations are:

◦ AND
◦ OR
◦ XOR
◦ Rotate
◦ Compare
◦ Complement
 AND, OR, XOR
• A ny 8-bit data, or the contents of
register, or memory location can
logically have
◦ AND operation
◦ OR operation
◦ XOR operation

with the contents of accumulator.

• T h e result is stored in accumulator.
Opcode Operand Description

ANA R Logical AND register or

memory with accumulator
M

• The contents of the accumulator are logically ANDed with the contents of
register or memory.
• The result is placed in the accumulator.
• If the operand is a memory location, its address is specified by the
contents of H-L pair.
• S, Z, P are modified to reflect the result of the operation.
• CY is reset and AC is set.
• Example: ANA B or ANA M.
collected by C.Gokul
 BEFORE EXECUTION 1010 1010=AAH AFTER EXECUTION
0000 1111=0FH
CY AC CY 0
0000 1010=0AH AC
AA AA 1

B 0F C B 0F
B 1 C ANA B 0AC
D 0 E A
D E
D E A=A and
H
H L
L H L
R

BEFORE EXECUTION AFTER EXECUTION

0101 0101=55H
CY AC 1011 CY 0
0011=B3H AC
B3 0001 0001=11H 1 B3
A 55 2050H A 11 2050H

H 20 50 ANA M H 20 L
L
A=A and 50
 Opcode Operand Description
ANI 8-bit data Logical AND immediate with
accumulator

• T h e contents of the accumulator are logically ANDed

with the 8-bit data.
• T h e result is placed in the accumulator.
• S , Z, P are modified to reflect the result.
• CY is reset,AC is set.
•
Example: ANI 86H.
BEFORE EXECUTION AFTER EXECUTION

1011 0011=B3H
0011 1111=3FH

0011 0011=33H

CY AC 1
CY AC
ANI 3FH 0
A B3 A=A and DATA(8) A 33
Opcode Operand Description
ORA R Logical OR register or memory with
M accumulator

• The contents of the accumulator are logically ORed with the contents of the
register or memory.

• The result is placed in the accumulator.

• If the operand is a memory location, its address is specified by the contents of H-

L
pair.

• S, Z, P are modified to reflect the result.

• CY and AC are reset.

• Example: ORA B or ORA M.

 1010
1010=AAH
BEFORE EXECUTION 0001 0010=12H AFTER EXECUTION
1011 1010=BAH

CY AC CY 0
AC 0
ORA B
A=A or
R
A AA A BA
B 12 B 12
D E D E
C C
H L H L
 0101 0101=55H
1011
BEFORE EXECUTION 0011=B3H AFTER EXECUTION
1111 0111=F7H

CY AC CY AC
0
0
ORA M
B3 A=A or B3
A 55 2050H A F7 2050H
H 20 50 M H 20 50
L L
 Opcode Operand Description

ORI 8-bit data Logical OR immediate

with accumulator

• T h e contents of the accumulator are logically ORed with

the 8-bit data.
• T h e result is placed in the accumulator.
• S , Z, P are modified to reflect the result.
• CY and AC are reset.
•
Example: ORI 86H.
 1011 0011=B3H
0000 1000=08H

BEFORE EXECUTION 1011 1011=BBH AFTER EXECUTION

CY AC
CY AC
ORI 08H 0 0

A B3 A=A or
A BB
DATA(8)
 Opcode Operand Description

XRA R Logical XOR register or

memory with accumulator
M

• T h e contents of the accumulator are XORed with the contents

ofthe register or memory.
• T h e result is placed in the accumulator.
• If the operand is a memory location, its address is specified
by the contents of H-L pair.
• S, Z, P are modified to reflect the result of the operation.
• CY and AC are reset.
•
Example: XRA B or XRA M.
 1010
BEFORE EXECUTION 1010=AAH AFTER EXECUTION
0010 1101=2DH
1000 0111=87H

CY AC CY 0
AC
0
A AA A 87
B 1 C 2D B C 2D
D 0 E XRA C D E
H L A=A xor H L

R
 0101 0101=55H
BEFORE EXECUTION 1011 AFTER EXECUTION
0011=B3H
1110 0110=E6H

CY AC CY 0

2050H
B3 XRA M AC
0 2050H B3
A 55 A E6
H 20 50 A=A xor H 20 50
L L
M
 Opcode Operand Description

XRI 8-bit data XOR immediate with

accumulator

• T h e contents of the accumulator are XORed

withthe 8-bit data.
• T h e result is placed in theaccumulator.
• S, Z, P are modified to reflect the result.
• CY and AC are reset.
•
Example: XRI 86H.
 1011 0011=B3H
0011 1001=39H

BEFORE EXECUTION 1000 1010=8AH AFTER EXECUTION

CY AC
CY AC
XRI 39H 0 0

A B3 A=A xor
A 8A
DATA(8)
 Compare
• A ny 8-bit data, or the contents of
register, or memory location can be
compares for:
◦ Equality
◦ Greater Than
◦ Less Than

with the contents of accumulator.

• T h e result is reflected in status
flags.
Opcode Operand Description
CMP R Compare register or
memory with accumulator
M

• T h e contents of the operand (register or

memory)are compared with the contents of the
accumulator.

• B o t hcontents are preserved .

 BEFORE EXECUTION AFTER EXECUTION
A>R: CY=0
CY Z A=R: CY 01 Z 0
ZF=1
A
A 10 A<R: CY=1 A 10
B
B C
10 B C
D
D 20 C EE CMP D 20 E
H
H L
L
D A-R H L

10<20:CY=01
BEFORE EXECUTION AFTER EXECUTION
A>M: CY=0
A=M:
CY Z ZF=1 CY
ZF 1
A<M: CY=1
A B8
B8 0
A
B8
2050H B8
CMP 2050H
H 20 50 H 20
L M A- L 50
Opcode Operand Description

CPI 8-bit data Compare immediate with

accumulator

• T h e 8-bit data is compared with the

contentsof accumulator.

• T h e values being compared

remainunchanged.
BEFORE EXECUTION AFTER EXECUTION
A>DATA: CY=0
A=DATA: ZF=1
A<DATA: CY=1
CY AC
CPI 30H
CY Z
0 0

A BA
A- A BA

DATA

BA>30: CY=00
 Rotate
•
Each bit in the accumulator can be
shifted either left or right to the next
position.
Opcode Operand Description
RLC None Rotate accumulator left

• E a c h binary bit of the accumulator is rotated left by

one position.
• B i t D7 is placed in the position of D0 as well as in the
Carry flag.
• CY is modified according to bit D7.
• S , Z, P, AC are not affected.
•
Example: RLC.
 BEFORE EXECUTION

CY B7 B6 B5 B4 B3 B2 B1 B0

AFTER EXECUTION

B7 B6 B5 B4 B3 B2 B1 B0
B7
 Opcode Operand Description
RRC None Rotate accumulator right

• E a c h binary bit of the accumulator is rotated right by

one position.
• B i t D0 is placed in the position of D7 as well as in the
Carry flag.
• CY is modified according to bit D0.
• S , Z, P, AC are not affected.
•
Example: RRC.
 BEFORE EXECUTION

B7 B6 B5 B4 B3 B2 B1 B0 CY

AFTER EXECUTION

B0 B7 B6 B5 B4 B3 B2 B0
B1

collected by C.Gokul AP/EEE , Velalar college of Engineering and Technology,

Erode
 Opcode Operand Description
RAL None Rotate accumulator left
through carry

• E a c h binary bit of the accumulator is rotated left by

one position through the Carry flag.
• B i t D7 is placed in the Carry flag, and the Carry flag is
placed in the least significant position D0.
• CY is modified according to bit D7.
• S , Z, P, AC are not affected.
•
Example: RAL.
 BEFORE EXECUTION

CY B7 B6 B5 B4 B3 B2 B1
B0

AFTER EXECUTION

B7 B6 B5 B4 B3 B2 B1 B0
CY
 Opcode Operand Description
RAR None Rotate accumulator right
through carry

• E a c h binary bit of the accumulator is rotated right by

one position through the Carry flag.
• B i t D0 is placed in the Carry flag, and the Carry flag is
placed in the most significant position D7.
• CY is modified according to bit D0.
• S , Z, P, AC are not affected.
•
Example: RAR.
 BEFORE EXECUTION

B7 B6 B5 B4 B3 B2 B1 B0 CY

AFTER EXECUTION

CY B7 B6 B5 B4 B3 B2 B0
B1
 Complement
• T h e contents of accumulator can
be complemented.

• Each 0 is replaced by 1 and each

1 isreplaced by 0.
 Opcode Operand Description

CMA None Complement accumulator

• T h e contents of the accumulator

arecomplemented.
• N o flags are affected.
•
Example: CMA. A=A’
AFTER EXECUTION
BEFORE EXECUTION

A 00 A FF
 Opcode Operand Description
CMC None Complement carry

• T h e Carry flag is
complemented.
• No other flags are affected.
•
Example: CMC => c=c’ AFTER EXECUTION

BEFORE EXECUTION
C 00 C FF
Opcode Operand Description
STC None Set carry

• T h e Carry flag is set to 1.

• N o other flags are
affected.
•
Example: STC CF=1

S-set C-clear
(1) (0)
• T h e branch group instructions allows
the microprocessor to change the
sequence of program either
conditionally or under certain test
conditions.The group includes,
• ( 1 ) Jump instructions,
• ( 2 ) Call and Return instructions,
• ( 3 ) Restart instructions,
 Opcode Operand Description
JMP 16-bit Jump unconditionally
address

•
T h e program sequence is transferred to
thememory location specified by the 16-bit address
given in the operand.
•
Example: JMP 2034 H.
 Opcode Operand Description

Jx 16-bit Jump conditionally

address

•
T h e program sequence is transferred to
thememory location specified by the 16-bit address
given in the operand based on the specified flag of
the PSW.
•
Example: JZ 2034 H.
 Jump Conditionally
Opcode Description Status Flags
JC Jump if Carry CY = 1

JNC Jump if No Carry CY = 0

JZ Jump if Zero Z=1

JNZ Jump if No Zero Z=0

JPE Jump if Parity Even P=1

JPO Jump if Parity Odd P=0

A-Above , B-Below , C-Carry , Z-Zero , P-

Parity
Opcode Operand Description

CALL 16-bit Call unconditionally

address

•
T h e program sequence is transferred to
thememory location specified by the 16-bit
address given in the operand.
•
Before the transfer, the address of the next instruction
after CALL (the contents of the program counter) is
pushed onto the stack.
• Example: CALL 2034 . H
 Call Conditionally
Opcode Description Status Flags
CC Call if Carry CY = 1

CNC Call if No Carry CY = 0

CP Call if Positive S=0

CM Call if Minus S=1

CZ Call if Zero Z=1

CNZ Call if No Zero Z=0

CPE Call if Parity Even P=1

CPO Call if Parity Odd P=0

 Opcode Operand Description
RET None Return unconditionally

• T h e program sequence is transferred

fromthe subroutine to the calling program.
• T h e two bytes from the top of the stack are
copied into the program counter, and program
execution begins at the new address.
•
Example: RET.
 Return Conditionally
Opcode Description Status Flags
RC Return if Carry CY = 1

RNC Return if No Carry CY = 0

RP Return if Positive S=0

RM Return if Minus S=1

RZ Return if Zero Z=1

RNZ Return if No Zero Z=0

RPE Return if Parity Even P=1

RPO Return if Parity Odd P=0

 Opcode Operand Description

RST 0–7 Restart (Software Interrupts)

•
T h e RST instruction jumps the control to one of
eight memory locations depending upon the
number.
•
These are used as software instructions in a
program to transfer program execution to one of
the eight locations.
•
Instruction Code Vector Address
RST 0 0*8=0000H
RST 1 1*8=0008H
RST 2 2*8=0010H
RST 3 3*8=0018H
RST 4 4*8=0020H
RST 5 5*8=0028H
RST 6 6*8=0030H
RST 7 7*8=0038H
 5. Control Instructions
•
T h e control instructions control the
operation of microprocessor.

collected by C.Gokul AP/EEE , Velalar college of Engineering and Technology,

Opcode Operand Description
NOP None No operation

• No operation is performed.
• T h e instruction is fetched and decoded
butno operation is executed.
•
Example: NOP
 Opcode Operand Description
HLT None Halt

• T h e CPU finishes executing the

currentinstruction and halts any further
execution.
• A n interrupt or reset is necessary to exit from the
halt state.
•
Example: HLT
 Opcode Operand Description
DI None Disable interrupt

• T h e interrupt enable flip-flop is reset and

allthe interrupts except the TRAP are disabled.
• No flags are affected.
•
Example: DI
 Opcode Operand Description
EI None Enable interrupt

• T h e interrupt enable flip-flop is set and

allinterrupts are enabled.
• No flags are affected.

• T h i s instruction is necessary to re-

enablethe interrupts (except TRAP).
•
Example: EI
 Opcode Operand Description
RIM None Read Interrupt Mask

• T h i s is a multipurpose instruction used to read the

status of interrupts 7.5, 6.5, 5.5 and read serial data
input bit.
• T h e instruction loads eight bits in the accumulator
with the following interpretations.
•
Example: RIM
RIM Instruction
 Opcode Operand Description

SIM None Set Interrupt Mask

• T h i s is a multipurpose instruction and used to

implement the 8085 interrupts 7.5, 6.5, 5.5, and serial
data output.
• T h e instruction interprets the
accumulatorcontents as follows.
•
Example: SIM
SIM Instruction
Addressing Modes in 8085

Immediate Addressing Mode

Direct Addressing Mode

Register Addressing Mode

Indirect Addressing

Mode

Implicit Addressing Mode

 Immediate Addressing Mode
▪ 8/16-bit data is specified in the
instruction itself as one of its
operand.
▪ For example:
MVI B,20H
LXI D,1034H
ADI 45H
SUI 30H
CPI 68H

Unit-4 Assembly Language Basics Darshan Institute of Engineering & Technology

 Direct Addressing Mode
▪ 8/16-bit memory address is directly provided with the instruction.
▪ For example:
LDA 1035H ; here 1035 is 16-bit memory address
IN 02H ; 02 is 8-bit I/O port address
OUT 03H ; 03 is 8-bit I/O port address

Unit-4 Assembly Language Basics Darshan Institute of Engineering & Technology

 Register Addressing Mode
▪ It specifies register or register pair that contains data.
▪ For example:
A ←
MOV A,B ; B

A ←
ADD B ; A+B
DAD H ; HL ←
HL+RP

Unit-4 Assembly Language Basics Darshan Institute of Engineering & Technology

 Indirect Addressing Mode
▪ In this type of addressing mode, the 16-bit
memory address is
indirectly provided with the instruction using a register pair.
▪ For example:
LDAX D; A <- M[DE]
STAX B; A -> M[BC]

Unit-4 Assembly Language Basics Darshan Institute of Engineering & Technology

 Implicit/Implied Addressing Mode
▪ This mode doesn’t require any operand; the data is specified by
the Opcode itself.
▪ For example:
XTHL

SPHL

PCHL

Unit-4 Assembly Language Basics Darshan Institute of Engineering & Technology

 8085 Assembly Language Programs

Unit-4 Assembly Language Basics 9 Darshan Institute of Engineering & Technology

 Writing Assembly Language Programs
The steps to write Assembly Language Programs are as
follows:
Step-1: Read the problem carefully.
Step-2: Break it down into small steps.
Step-3: Represent the sequence with flowchart.
Step-4: Translate flowchart into appropriate mnemonic instructions.
Step-5: Translate mnemonic into machine code.
Step-6: Enter machine code in memory and execute.
Step-7: Start troubleshooting-debugging a program

Unit-4 Assembly Language Basics Darshan Institute of Engineering & Technology

 Documentation
▪ Appropriate comments are critical for conveying the logic behind
the program.
▪ The comment should explain what is intended; they should not
explain mnemonics.

▪ Comment is optional.
Example:
MOV A,B ; Move data from B to A
Χ
MOV A,B ; send data to accumulator for processing
√

Unit-4 Assembly Language Basics Darshan Institute of Engineering & Technology

 Program Execution
▪ Machine code can be loaded in R/W memory, with reference to
starting memory location.
▪ Execution can be done in two ways:
1. Execute entire code on click.
2. Single step execution.
• It will execute one instruction at a time.
• We can observe the content of register and flag after execution
of each instruction.

Unit-4 Assembly Language Basics Darshan Institute of Engineering & Technology

 Debugging Program
▪ Debug a program is similar to troubleshooting hardware.
▪ If the code doesn’t work, it is
essential to search carefully for errors in
programming logic, machine codes and execution.
How to Debug machine code:
▪ Translating assembly to machine code is
similar to building a circuit.
▪ Following errors are common:
1. Writing a wrong code.
2. Specifying the wrong jump location.
3. Writing memory address in decimal, thus specifying wrong jump location.
4. Writing lower order and higher order bits in wrong sequence.

Unit-4 Assembly Language Basics Darshan Institute of Engineering & Technology

 Add Two 8-bit Numbers
Write a program to add data at 1005H &
1006H memory location and store the result Start
at 1007H memory location.
Transfer 16-bit
address to HL Pair
1. LXI H,1005; to retrive m/m Data Transfer: A <- M[HL]
addr
2. MOV A,M; retrieve m/m
content HL=HL + 1
3. INX H;increment memeory to 1006H
4. ADD M;add accumulator with M[1006] A = A + M[HL]

5. STA 1007; store Store result

result [1007] <- A
6. HLT program
HLT; End

Unit-4 Assembly Language Basics Darshan Institute of Engineering & Technology

 8085 Assembly Program
Write a program to load register B with 37H and display number at
the output Port 01
1. MVI B,37; B <- 37H
2. MOV A,B ; A <- B for I/O processing
3. OUT 01 PORT 01 <- A
4. HLT ;

Unit-4 Assembly Language Basics Darshan Institute of Engineering & Technology

8085 Assembly Program
Write a program to add two 8-bit number (consider carry bit)

Accumulator <- ABh

B <- ACh

ADD Accumulator and

B

YES
Carry? Increment Result

NO
Display Result

End

160
8085 Assembly Program
Write a program to add two 8-bit number with carry

1. MVI A, ABh

2. MVI B, ACh

3. ADD B ; A=A+B

4. JC L1 ; if CY=1

5. JNC L2 ; if CY=0

6. L1:INR A ;Increment result if CY=1

7. L2:HLT

161
162
8085 Assembly Program
Exercise
Write a program to subtract two 8-bit number

163
164
165
166
8085 Assembly Program
Write a program to exchange the data at 1501H & 1502H memory location.
1. LDA 1501 ;load A <- M[1501]
2. MOV B,A ; B <- A

3. LDA 1502 ;load A <- M[1502]

4. STA 1501 ; M[1501] <- A

5. MOV A,B ; A <- B

6. STA 1502 ; M[1502] <- A

167
8085 Assembly Program
Write a program for reverse counter and display result in output port1

Initialize counter
A <- 0Ah
C <- 00h

Display output-> Port

01

Decrement Counter
YES

Counter ≠0

No
Halt

168
8085 Assembly Program
Write a program for reverse counter and display result in output port1
1. MVI A,0A
2. MVI C,00
3. L1: OUT 01 ; display content of accumulator
4. DCR A ; decrement accumulator
5. CMP C ; compare C with accumulator
6. JNZ L1 ; if Z ≠ 0
7. JZ L2 ; if Z = 0
8. L2: HLT

169
8085 Assembly Program
Write a program to Set PSW (Accumulator & 5 Flags)

1. LXI H, FFFF

2. PUSH H

3. POP PSW;lower 8-bit to flags;higher 8-bit to Accumulator

Write a program to Reset PSW (Accumulator & 5 Flags)

4. LXI H, 0000

5. PUSH H

6. POP PSW
170 170
8085 Assembly Program
Exercise
1. Memory Location 2050H holds databyte F7H. Write an instruction to transfer data byte to
Accumulator using 3 different Opcodes: MOV, LDAX, LDA

171 171
172
173
8085 Assembly Program
Write a program to add the content of M[2040H] with A,

Subtract M[2041H] from add result.

Assume

A=30H

M[2040]=68H

M[2041]=7FH

PROGRAM:

1. LXI H,2040

2. ADD M ; A=A+M[2040]

3. INX H ; HL=HL+1

4. SUB M ; A=A-M[2041]

5. HLT
174
8085 Assembly Program
WAP to add 10 bytes starting from 3001h to 300Ah. Use register B to save any carries generated, while
adding data bytes. Display result to output port 01h and store at M[300B].

Registers Memory

03 3001
A Result 04 3002
09 .
B Carry Counter C 06 .
D E D2
.
08
H L F7
A5
02
E3 300A
175
8085 Assembly Program
WAP to find largest number among 10 bytes starting from 3001h to 300Ah. Display result to output port 01h
and store at M[300B].

Registers Memory

03 3001
A Result 04 3002
09 .
B Counter C 06 .
D E D2
.
08
H L F7
A5
02
E3 300A
177
 Start 1. MVI A,00
2. MVI C,0A
WAP to find largest number from 3001h to 300Ah.

Clear Reg. to save Result 3. LXI H,3001

Set Counter 4. MOV A,M
5. L3:INX H
Set m/m Pointer
6. CMP M
Data Transfer: 7. JC L1
A <- m/m pointer 8. JNC L2
9. L1:MOV A,M
Pointer=Pointer + 1 10. JMP L2
11. L2:DCR C
12. JZ END
Compare
13. JNZ L3
A − m/m Pointer 14. END:OUT 01
15. STA 300B
Is there 16. HLT
Carry? End
NO YES
Data Transfer:
A <- m/m pointer Display and Save
NO
Result
Counter=Counter - 1 Is
YES
Counter= 178
0 178
179
8085 Assembly Program
Exercise
WAP to find Smallest number among 10 bytes starting from 3001h to 300Ah. Display result to output port
01h and store at M[300B].

180 180
8085 Assembly Program
WAP to find odd and even numbers in given array of 10 elements starting from
2001H and perform addition of Odd and Even number respectively.
Data=05h RRC

A:Accumulator
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 1 0 1
0 0 0 0 0 1 0

CY

181 181
 1. MVI B,00;StoreODD
Start
2. MVI D,00;StoreEVEN
3. MVI C,0AH;Counter
B <- 00h 4. LXI H,0001;Pointer
D<- 00h 5. L1: MOV A,M
WAP to find sum of ODD and EVEN number.

C <- 0Ah 6. MOV E,A

Set m/m Pointer 7. RRC
8. JC ODD
Data Transfer: 9. JNC EVEN
10. ODD:MOV A,E
A <- m/m pointer
11. ADD B
12. MOV B,A
Rotate all the bits to 13. JMP CNT
right and update 14. EVEN: MOV A,E
Carry bit 15. ADD D
16. MOV D,A
17. JMP CNT
Is there 18. CNT: INX H
Carry? NO 19. DCR C
YES 20. JZ END
21. JNZ L1
Odd Sum:A=A+B Even Sum:A=A+D 22. END: HLT

NO
Pointer=Pointer + 1
Is YES
Counter=Counter - 1 Counter= End 182
0 182
8085 Assembly Program
Exercise
• An array of Ten numbers is stored from memory location 2000H onwards. Write an 8085 assembly
language program to separate out and store the EVEN and ODD numbers on new arrays from 2100H and
2200H, respectively.
• WAP to find number of 1’s and 0’s of 8-bit number stored at M[2010]
• WAP to multiply two 8-bit numbers.
• WAP to arrange an array of 10 numbers starting from 3001 to 300A in descending order.
• WAP to eliminate duplicate entry from an array of 10 numbers.

183
184
185
186
187
 Timing & Machine Cycle
for 8085 Instructions

Unit-4 Assembly Language Basics 16 Darshan Institute of Engineering & Technology

 Timing Cycle required by 8085 Instructions
Operation T-States
Opcode Fetch 4-6T
Memory Read 3T
Memory Write 3T
I/O Read 3T
I/O Write 3T

• Instruction that require 5T-States for Opcode Fetch

HLT
• Instructions that require 6T-States for Opcode Fetch
1. CALL 5. PCHL
2. Conditional CALL 6. SPHL
3. DCX 7. PUSH
4. INX 8. Conditional RET
Unit-4 Assembly Language Basics Darshan Institute of Engineering & Technology
 Machine Cycle required by 8085 Instruction

Operation M/C
Fetch (F) 1
Memory Read (MEMR) 1
Memory Write (MEMW) 1
I/O Read (IOR) 1
I/O Write (IOW) 1
Read Immediate Data (R) 1

Unit-4 Assembly Language Basics Darshan Institute of Engineering & Technology

 Timing and Machine Cycle
1. MOV B,
D
Machine Cycle: = 1 Machine Cycle
1(F)
Timing Cycle: = 4T(Fetch)

Unit-4 Assembly Language Basics Darshan Institute of Engineering & Technology

Timing and Machine Cycle
2. MVI C ,17H
Machine Cycle: Fetch + R
1 +
Timing Cycle: 1=
2
Fetch + R
4T + 3T= 7T
Timing and Machine Cycle
3. MVI M , 25H
Machine Cycle: Fetch + R+ Write data(MEMW)
1 + 1 +1
Timing Cycle: Opcode=Fetch
3 + R + MEMW
4T + 3T + 3T = 10T

Darshan Institute of Engineering & Technology

Timing and Machine Cycle
4. MOV A,M
Machine Cycle: Fetch + Read Memory(MEMR)
1 +
Timing Cycle: 1
=2
Fetch + MEMR
4T + 3T = 7T
Timing and Machine Cycle
4. MOV M, A
Machine Cycle: Fetch + Write Memory(MEMW)
1+1=2
Timing Cycle: Fetch + MEMW
4T + 3T = 7T

Darshan Institute of Engineering & Technology

Timing and Machine Cycle
5. NOP
Machine Cycle: Fetch
=1 M/C
Timing Cycle: Cycle Fetch
= 4T
Timing and Machine Cycle
6. HLT : Halt and enter wait state
Machine Cycle: Fetch + Wait
=1 or more M/C
Timing Cycle: Cycle
Fetch + Wait
= 5T or more T-States

Darshan Institute of Engineering & Technology

Timing and Machine Cycle
7. IN 18H
Machine Cycle: Fetch + R + IOR
=1 +1+1
=3
Timing Cycle: Fetch + R + IOR
= 4T + 3T + 3T
= 10T
Timing and Machine Cycle
8. OUT 19H
Machine Cycle: Fetch + R + IOW
=1 +1+1
=3
Timing Cycle: Fetch + R + IOW
= 4T + 3T + 3T
= 10T
Timing and Machine Cycle
9. ADD B
Machine Cycle: Fetch
= 1 Machine Cycle
Timing Cycle: Fetch
= 4T
Timing and Machine Cycle
10. ADI 26H
Machine Cycle: Fetch + R
1 +
Timing Cycle: 1=2
Fetch + MEMR
4T + 3T = 7T
Timing and Machine Cycle
11. ADD M
Machine Cycle: Fetch + MEMR
1 +
Timing Cycle: 1=2
Fetch + MEMR
4T + 3T = 7T
Timing and Machine Cycle
12. SUB C
Machine Cycle: Fetch
= 1 Machine Cycle
Timing Cycle: Fetch
= 4T
Timing and Machine Cycle
13. SUI 26H
Machine Cycle: Fetch + R
1 +
Timing Cycle: 1=2
Fetch + MEMR
4T + 3T = 7T
Timing and Machine Cycle
14. SUB M
Machine Cycle: Fetch + MEMR
1 +
Timing Cycle: 1=2
Fetch + MEMR
4T + 3T = 7T
 Timing and Machine Cycle
15. LDA 2030H
Machine Cycle: Fetch + ReadL 8-bit + ReadH 8-bit +MEMR (content)
=1 +1+1+1
=4
Timing Cycle: Fetch + MEMR + MEMR + MEMR
= 4T + 3T + 3T + 3T
= 13T

Unit-4 Assembly Language Basics Darshan Institute of Engineering & Technology

Timing and Machine Cycle
16. POP RP :
POP B Fetch + MEMR (SP) + MEMR (SP+1)
Machine Cycle: =1 +1+1
=3
Timing Cycle: Fetch + MEMR + MEMR
= 4T + 3T + 3T
= 10T
Timing and Machine Cycle
16. PUSH RP : PUSH
BMachine Cycle: Fetch + MEMW (SP) + MEMW (SP-1)
=1 +1+1
=3
Timing Cycle: Fetch + MEMW + MEMW
= 6T + 3T + 3T
= 12T
 LHLD Instruction
Registers Memory

02 0001
A 04 0002
C 0A 0003
06 0004
B E
0F 0005
L
0 D 0006
D 0 D
0 5 0007
0 5
LHLD 0006H 03 0008
H

Unit-4 Assembly Darshan Institute of Engineering & Technology

 Timing and Machine Cycle
17. LHLD 2034H
Machine Cycle: Fetch + MEMRL(2034) + MEMRH(2034)
+ MEMR_Content(2034)
+ MEMR_Content (2035)
=1 +1+1+1+1
=5
Timing Cycle: Opcode Fetch+ MEMR + MEMR + MEMR + MEMR
= 4T + 3T + 3T + 3T + 3T
= 16T

Unit-4 Assembly Language Basics Darshan Institute of Engineering & Technology

Timing and Machine Cycle
18. RAR
Machine Cycle: Fetch
= 1 Machine Cycle
Timing Cycle: Fetch
= 4T
Timing and Machine Cycle
19. XTHL
Machine Cycle: Fetch + MEMR(SP)+MEMW(L)+
MEMR(SP+1)+MEMW(H)
=1 +1+1+1+1
=5
Timing Cycle: Fetch+ MEMR + MEMW + MEMR + MEMW
= 4T + 3T + 3T + 3T + 3T
= 16T

Darshan Institute of Engineering & Technology

 Timing and Machine Cycle
20. CALL 2030H
Machine Cycle: Fetch + MEMWL(Store) + MEMWH(Store)
+ MEMRL(Call) + MEMRH(Call)
=1 +1+1+1+1
=5
Timing Cycle: Fetch+ MEMW + MEMW + MEMR + MEMR
= 6T + 3T + 3T + 3T + 3T
= 18T

Unit-4 Assembly Language Basics Darshan Institute of Engineering & Technology

 Timing and Machine Cycle
21. RET
Machine Cycle: Fetch + MEMR (SP) + MEMR (SP+1)
=1 +1+1
=3
Timing Cycle: Fetch + MEMR + MEMR
= 4T + 3T + 3T
= 10T

Unit-4 Assembly Language Basics Darshan Institute of Engineering & Technology

 Exercise: Find Byte Size, Timing & Machine Cycle
1. LDAX B
2. SHLD 2470
3. SPHL
4. DAA
5. INR R/M
6. JMP
7. PCHL
8. CMP R/M
9. RRC
10. RIM
11. SIM
12. ORA R/M
13. XCHG
14. DI
15. EI

Unit-4 Assembly Language Basics Darshan Institute of Engineering & Technology

Exercise Solution
Sr. Instruction Byte Size Machine Cycle T-States
1. LDAX B 1 F+R=2 4T+3T=7T
2. SHLD 2470 3 F+R+R+W+W=5 4T+3T+3T+3T+3T=16T
3. SPHL 1 F=1 6T
4. DAA 1 F=1 4T
5. INR R 1 F=1 4T
INR M 1 F+R+W=3 4T+3T+3T=10T
6. JMP 2030 3 F+R+R=3 4T+3T+3T=10T
7. PCHL 1 F=1 6T
8. CMP R 1 F=1 4T
CMP M 1 F+R=2 4T+3T=7T
9. RRC 1 F=1 4T
10. RIM 1 F=1 4T
Exercise Solution
Sr. Instruction Byte Size Machine Cycle T-States
11. SIM 1 F=1 4T
12. ORA R 1 F=1 4T
ORA M 1 F+R=2 4T+3T=7T
13. XCHG 1 F=1 4T
14. DI 1 F=1 4T
15. EI 1 F=1 4T
 Timing Diagram

Unit-4 Assembly Language Basics 46 Darshan Institute of Engineering & Technology

 Opcode Fetch

CLK

A
15
High order memory address Unspecified
A8
AD7 Low order
Opcode
M/m addr.
AD0

ALE
IO/M

RD
 Memory read cycle

CLK

A
15
High order memory address
A8
AD7 Low order
Data from memory
M/m addr. S1 S0 Mode
0 0 HLT
AD0
0 1 WRITE
1 0 READ

ALE
IO/M
S0 IO/M=0, S1=1 , S0=0
S1
RD
 Memory write cycle

CLK

A
15
High order memory address
A8
AD7 Low order Data from
M/m addr. Microprocessor S1 S0 Mode
0 0 HLT
AD0
0 1 WRITE
1 0 READ

ALE
IO/M
S1 IO/M=0, S1=0 , S0=1
S0
WR
 I/O read cycle

CLK

A
15
High order I/O address
A8
AD7 Low order
I/O
I/O addr. S1 S0 Mode
data 0 0 HLT
AD0
0 1 WRITE
1 0 READ

ALE
S0
IO/M=1, S1=1 , S0=0
IO/M
S1
RD
 I/O write cycle

CLK

A
15
High order I/O address
A8
AD7 Low order Data from
I/O addr. Microprocessor S1 S0 Mode
0 0 HLT
AD0
0 1 WRITE
1 0 READ

ALE
S1
IO/M=1, S1=0 , S0=1
IO/M
S0
WR
Timing Diagram : MOV
Opcode Fetch Memory Read
B,M
T1 T2 T3 T4 T5 T6 T7

CLK

A High order memory Unspe High order memory

15
address cified address
A8

AD7 Low order Low order Data from

M/m Opcode M/m
AD0 addr. addr. memory

ALE

IO/M

RD
Timing Diagram : MVI A, 32H
Opcode Fetch Memory Read
T1 T2 T3 T4 T5 T6 T7

CLK

A High order memory Unspe High order memory

15
address cified address
A8

AD7 Low order Low order Read

M/m Opcode M/m
AD0 addr. addr. Immediate

ALE

IO/M

RD
Calculate Execution time of MVI A,32H
Given: Clock Frequency (f) = 2 MHz
Calculation:
1
Step-1: T-state = clock period = = = 0.5
1 μsec
Step-2: Execution time for Opcode
𝑓
Fetch
= 4T x 0.5 = 2μsec
2
Step-3: Execution time for Memory Read
= 3T x 0.5 = 1.5μsec
Step-4: Execution time for Instruction
= (4T + 3T) x 0.5
= 7T x 0.5
= 3.5μsec
 Timing Diagram : OUT
02H
Opcode Fetch Memory Read I/O Write
T1 T2 T3 T4 T1 T2 T3 T1 T2 T3

CLK

A High order Unspecif High

15 Port address 02H
memory address ied order memory
A8 address
Low Low Port Acc.
AD7 Opcode 02H
AD addr addr addr content
0

ALE
IO/M

RD

IOW
 Timing Diagram : IN 02H

Opcode Fetch Memory Read I/O Read

T1 T2 T3 T4 T1 T2 T3 T1 T2 T3

CLK

A High order memory Unspecif High order memory

15 Port address 02H
address ied address
A8
Low Low Port Acc.
AD7 Opcode 02H
AD addr addr addr content
0

ALE
IO/M

RD

IOR