Combinational Logic

 Logic circuits for digital systems may be combinational or sequential.

 A combinational circuit consists of logic gates whose outputs at any time are determined from only the
present combination of inputs.
 Ex:Adder

 A combinational circuit performs an operation that can be specified logically by a set of Boolean functions.

 In contrast, sequential circuits employ storage elements in addition to logic gates

C O M B I N AT I O N A L C I R C U I T S

 A combinational circuit consists of an interconnection of logic gates.

 The n input binary variables come from an external source; the m output variables are produced by the
internal combinational logic circuit and go to an external destination.
 In many applications, the source and destination are storage registers. If the registers are included with the
combinational gates, then the total circuit must be considered to be a sequential circuit.
 Ex:Counter
 For n input variables, there are 2n possible combinations of the binary inputs.
 For each possible input combination, there is one possible value for each output variable.
 Thus, a combinational circuit can be specified with a truth table that lists the output values for
each combination of input variables.
 A combinational circuit also can be described by m Boolean functions, one for each output
variable. Each output function is expressed in terms of the n input variables.
Design procedure for combinational circuits

 We’ll address three tasks:

 (1) Analyze the behavior of a given logic circuit,

 (2) synthesize a circuit that will have a given behavior, and

 (3) write hardware description language (HDL) models for some common circuits
 There are several combinational circuits that are employed extensively in the design of digital systems.
 These circuits are available in integrated circuits and are classified as standard components.
 They perform specific digital functions commonly needed in the design of digital systems.
 In this chapter, we introduce the most important standard combinational circuits, such as adders, subtractors,
comparators, decoders, encoders, and multiplexers.
 These components are available in integrated circuits as medium-scale integration (MSI) circuits.
 They are also used as standard cells in complex very largescale integrated (VLSI) circuits such as application-
specific integrated circuits (ASICs).
 A N A LY S I S PROCEDURE

 The analysis of a combinational circuit requires that we determine the function that the circuit implements.
 This task starts with a given logic diagram and culminates with a set of Boolean functions, a truth table, or,
possibly, an explanation of the circuit operation.
 In Table 4.1 , we form the eight possible combinations for the three input variables.
 The truth table for F2 is determined directly from the values of A , B , and C , with F2 equal to 1 for any
combination that has two or three inputs equal to 1.
 The truth table for F 2 is the complement of F2.
 The truth tables for T1 and T2 are the OR and AND functions of the input variables, respectively.
 The values for T3 are derived from T1 and F 2:T3 is equal to 1 when both T1 and F 2 are equal to 1, and
T3 is equal to 0 otherwise.
 Finally, F1 is equal to 1 for those combinations in which either T2 or T3 or both are equal to 1.
 Inspection of the truth table combinations for A, B, C, F1, and F2 shows that it is identical to the truth
table of the full adder for x, y, z, S , and C , respectively.
DESIGN PROCEDURE

 The procedure involves the following steps:

 1. From the specifications of the circuit, determine the required number of inputs and outputs and
assign a symbol to each.
 2. Derive the truth table that defines the required relationship between inputs and outputs.
 3. Obtain the simplified Boolean functions for each output as a function of the input variables.
 4. Draw the logic diagram and verify the correctness of the design (manually or by simulation).
 A truth table for a combinational circuit consists of input columns and output columns.
 The input columns are obtained from the 2n binary numbers for the n input variables.
 The binary values for the outputs are determined from the stated specifications.
 The output functions specified in the truth table give the exact definition of the combinational
circuit.
 It is important that the verbal specifications be interpreted correctly in the truth table, as they are
often incomplete, and any wrong interpretation may result in an incorrect truth table.
 The output binary functions listed in the truth table are simplified by any available method, such as
algebraic manipulation, the map method, or a computer-based simplification program.
 A practical design must consider such constraints as
 the number of gates,
 number of inputs to a gate,
 propagation time of the signal through the gates,
 number of interconnections.
Code Conversion Example

 converts binary coded decimal (BCD) to the excess-3 code for the decimal digits.
B I N A RY A D D E R – S U B T R A C T O R
 Half Adder
Binary Adder
Addition of n-bit numbers requires a chain of n full adders or a chain of one-half adder and n - 1 full adders.

To demonstrate with a specific example, consider the two binary numbers A = 1011 and B = 0011.
Their sum S = 1110 is formed with the four-bit adder as follows:
 Carry Propagation

 The addition of two binary numbers in parallel implies that all the bits of the augend and addend are available
for computation at the same time.
 The longest propagation delay time in an adder is the time it takes the carry to propagate through the full
adders.
 Inputs A3 and B3 are available as soon as input signals are applied to the adder. However, input carry C3 does
not settle to its final value until C2 is available from the previous stage. Similarly, C2 has to wait for C1 and so
on down to C0. Thus, only after the carry propagates and ripples through all stages will the last output S3 and
carry C4 settle to their final correct value.
 The number of gate levels for the carry propagation can be found from the circuit of the full adder.

 The signal from the input carry Ci to the output carry Ci+1 propagates through an AND gate and an OR gate, which
constitute two gate levels.

 If there are four full adders in the adder, the output carry C4 would have
2 * 4 = 8 gate levels from C0 to C4.

 For an n -bit adder, there are 2n gate levels for the carry to propagate from input to output.
Carry propagation
 The carry propagation time is an important attribute of the adder because it limits the speed with which two
numbers are added.
 An obvious solution for reducing the carry propagation delay time is to employ faster gates with reduced
delays.
 There are several techniques for reducing the carry propagation time in a parallel adder. The most widely used
technique employs the principle of carry lookahead logic .
 We now write the Boolean functions for the carry outputs of each stage and substitute the value of each
Ci from the previous equations:
C0 = input carry
C1 = G0 + P0C0
 C2 = G1 + P1C1 = G1 + P1 1G0 + P0C02 = G1 + P1G0 + P1P0C0
 C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0
Binary Subtractor
 The mode input M controls the operation.
 Adder operation
 When M = 0, the circuit is an adder, and when M = 1, the circuit becomes a subtractor. Each exclusive-OR
gate receives input M and one of the inputs of B .
 When M = 0, we have B xor 0 = B. The full adders receive the value of B , the input carry is 0, and the circuit
performs A + B .
 Subtraction operation
 When M = 1, we have B xor 1 = B’ and C0 = 1.
 The B inputs are all complemented and 1 is added through the input carry.
 The circuit performs the operation (A + the 2’s complement of B) .
 (The exclusive-OR with output V is for detecting an overflow.)
Overflow
DECODERS

 A decoder is a combinational circuit that converts binary information from n input lines to a maximum of
2n unique output lines.
 0

 Some decoders are constructed with NAND gates. Since a NAND gate produces the AND operation with an inverted
output, it becomes more economical to generate the decoder minterms in their complemented form.
 Furthermore, decoders include one or more enable inputs to control the circuit operation.
 A two-to-four-line decoder with an enable input constructed with NAND gates is shown in Fig. 4.19 .
 The circuit operates with complemented outputs and a complement enable input. The decoder is enabled when E is
equal to 0 (i.e., active-low enable).
 Because decoder and demultiplexer operations are obtained from the same circuit, a decoder with
an enable input is referred to as a decoder – demultiplexer .
 Decoders with enable inputs can be connected together to form a larger decoder circuit.
 Figure 4.20(next slide) shows two 3-to-8-line decoders with enable inputs connected to form a 4-
to-16-line decoder.
 When w=0, the top decoder is enabled and the other is disabled. The bottom decoder outputs are
all 0’s, and the top eight outputs generate minterms 0000 to 0111.
 When w =1, the enable conditions are reversed: The bottom decoder outputs generate minterms
1000 to 1111, while the outputs of the top decoder are all 0’s.
Cascading binary decoders
Combinational Logic Implementation
4.10 E N C O D E R S

 An encoder is a digital circuit that performs the inverse operation of a decoder.

Priority Encoder
A priority encoder is an encoder circuit that includes the priority function.
M U LT I P L E X E R S
 The circuit has two data input lines, one output line, and one selection line S .
 When S = 0, the upper AND gate is enabled and i0 has a path to the output. When S = 1, the
lower AND gate is enabled and i1 has a path to the output.
 The multiplexer acts like an electronic switch that selects one of two sources.
 The multiplexer is often labeled “MUX” in block diagrams.
 A four-to-one-line multiplexer is shown in Fig. 4.25 .
 Each of the four inputs, I0 through I3, is applied to one input of an AND gate. Selection lines S1
and S0 are decoded to select a particular AND gate.
 The outputs of the AND gates are applied to a single OR gate that provides the one-line output.
Boolean Function Implementation
Three-State Gates

• A multiplexer can be constructed with three-state gates—digital circuits that exhibit three states.
• Two of the states are signals equivalent to logic 1 and logic 0 as in a conventional gate.
• The third state is a high-impedance state in which (1) the logic behaves like an open circuit,
which means that the output appears to be disconnected,
• (2) the circuit has no logic significance, and
• (3) the circuit connected to the output of the three-state gate is not affected by the inputs to the
gate.
Synchronous Sequential Logic

 Hand-held devices, cell phones, navigation receivers, personal computers, digital cameras, personal
media players, and virtually all electronic consumer products have the ability to send, receive, store,
retrieve, and process information represented in a binary format.
 The technology enabling and supporting these devices is critically dependent on electronic components
that can store information, i.e., have memory.

 Sequential circuits, however, act as storage elements and have memory. They can store, retain, and then
retrieve information when needed at a later time.
 It consists of a combinational circuit to which storage elements are connected to form a feedback path.

 The block diagram demonstrates that the outputs in a sequential circuit are a function not only of the inputs, but also
of the present state of the storage elements.

 Thus, a sequential circuit is specified by a time sequence of inputs, outputs, and internal states.
 There are two main types of sequential circuits, and their classification is a function of the timing of their signals.
 synchronous sequential circuit.
 asynchronous sequential circuit.
 Synchronous sequential circuits that use clock pulses to control storage elements are called clocked sequential
circuits.
 A synchronous sequential circuit employs signals that affect the storage elements at only discrete instants of time.
 Synchronization is achieved by a timing device called a clock generator, which provides a clock signal having the
form of a periodic train of clock pulses . The clock signal is commonly denoted by the identifiers clock and clk .
 The storage elements (memory) used in clocked sequential circuits are called flip flops.
 A flip-flop is a binary storage device capable of storing one bit of information.
 In a stable state, the output of a flip-flop is either 0 or 1. A sequential circuit may use many flip-flops to
store as many bits as necessary.
 The block diagram of a synchronous clocked sequential circuit is shown in Fig. 5.2 .
 The outputs are formed by a combinational logic function of the inputs to the circuit or the values stored
in the flip-flops (or both).
STORAGE ELEMENTS: LATCHES

 A storage element in a digital circuit can maintain a binary state indefinitely (as long as power is delivered to the circuit).

 Storage elements that operate with signal levels (rather than signal transitions) are referred to as latches ; those controlled
by a clock transition are flip-flops .

 Latches are said to be level sensitive devices;

 flip-flops are edge-sensitive devices.

 The two types of storage elements are related because latches are the basic circuits from which all flip-flops are
constructed.
D Latch (Transparent Latch)
Edge-Triggered D Flip-Flop
HDL MODELS OF C O M B I N AT I O N A L
CIRCUITS
Gate-Level Modeling
Three-State Gates
 The gates are instantiated with the statement
 gate name (output,input, control);
Dataflow Modeling

 Verilog HDL provides about 30 different operators. Table 4.10 lists some of these operators, their symbols,
and the operation.
 Dataflow modeling uses continuous assignments and the keyword assign

• As an example, assuming that the variables were declared, a two-to-one-line multiplexer with scalar
data inputs A and B , select input S , and output Y is described with the continuous assignment
Behavioral Modeling

 Behavioral modeling represents digital circuits at a functional and algorithmic level. It is used mostly to
describe sequential circuits.

 Behavioral descriptions use the keyword always , followed by an optional event control expression and a
list of procedural assignment statements.

 The target output of a procedural assignment statement must be of the reg data type.

 Contrary to the wire data type, whereby the target output of an assignment may be continuously updated, a
reg data type retains its value until a new value is assigned.
Writing a Simple Test Bench

 A test bench is an HDL program used for describing and applying a stimulus to an HDL model of a
circuit in order to test it and observe its response during simulation.

 Test benches can be quite complex and lengthy and may take longer to develop than the design that
is tested.

 Care must be taken to write stimuli that will test a circuit thoroughly, exercising all of the operating
features that are specified.