Analog to Digital Converters

S. Alwyn Rajiv
Assistant Professor
Kamaraj College of Engineering and Technology
 Introduction
• Most of the real time parameters are analog in nature such as pressure,
temperature, speed, velocity, mass etc.
• All the communication and electronic applications are migrating to
digital techniques.
• The devices used bridge between analog parameters such as continues
voltage or current and binary based devices such as computer, digital ICs,
are termed as analog to digital converters.
• The real time parameters are first converted to current to voltage using
transducers and the output of transducer is given as the input to the ADC
to obtain binary digital values proportional to real time parameters.
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 Analog to Digital Converter

• - Analog input
• SOC – Start of Conversion
• EOC – End of Conversion

Where
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 Types of ADC
• Flash Type

• Successive Approximation

• Integrating type
– Single Slope ADC
– Dual Slope ADC

• ADC using voltage to time conversion

• Oversampling A to D converters
– Delta Modulation
– Adaptive DM (ADM)
–
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 Flash Type ADC
• This type of ADC is also called as
simultaneous type (or) parallel comparator
ADC (or) simply, comparator type.
• This type of ADC is the fastest of all ADCs
and expensive type too.

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Circuit Diagram Flash Type ADC

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• The circuits consists of comparators (7 comparators when n=3 and

excluding the bottom most comparator, which act as reference

comparator, resistive divider network and 8 to 3 priority line encoder.

• Note that the analog input is applied to non inverting terminal of all

the comparators and the comparative voltage is derived from reference

voltage using potential divider rule.

• For example, let us assume than is in between and .

• Since the input is greater than 0, , , , the four comparators will be

producing positive saturation (logic 1) which is then given to priority

encoder to produce a binary output =011

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• Therefore, based on the magnitude of input voltage , the comparators

will be switched ON or OFF and note that if any comparator is ON, all

the other comparators below it will also be ON.

• The greatest advantage of this type is the speed in the range of 100ns

or even less.

• And the drawbacks is the number of comparator required almost

doubles for each added bit in the input.

• The priority encoder becomes more complex as the value of n

increases.

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“Flash” is the name dedicated to speed. Its accuracy and input hold9
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 Successive Approximation ADC
• This type of ADC uses successive comparisons
to convert a analog signal to digital.
• This uses the same principles of finding the
weight of unknown weight using known fixed
value weight.

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• The heart of the circuits is a 8 bit successive approximation register (SAR). Initially the content of 8 bit

SAR is MSB only binary stream (10000000). It is given to a 8 bit DAC which in turn produces the

corresponding analog voltage.

Now

• This known analog voltage is compared with unknown Analog input . If >,the comparator is switched ON

(+) and MSB bit position is left as it is (Logic 1).

• On the other hand, if ,the comparator is switched O (+) and MSB bit position is inverted (Logic 0).

• On the next block pulse, SAR sets next bit position and D/A converted produces a corresponding analog

signal proportional to 01000000.

• This voltage is then compared with to decide whether the bit should be 1 or 0. Likewise, the comparison

is completed successively until deciding the value of (LSB).

• The conversion complete signal is arrived from SAR which also acts as the enable line E for the 8 bit latch.

The 8 bit latch finally provides the digital data output proportional to

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 Advantage

• Use only one comparator independent of number

of bits.
• It is faster than dual slope ADC with greater
resolution than flash type ADC
• The conversion process occurs in between start of
conversion (SoC) & End of Conversion (EoC).
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 Disadvantage

• Slow Speed as the number of clock cycles

equal to the number of bits.
• The input hold time is high and has medium
accuracy.

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 Integrating Type ADC
• The basic principle of integrating type ADC is to compare
the unknown analog input voltage with reference voltage
that begins at 0V and increase linearly with time.
• A ramp generator or integrator is used here.

• It can be classified into two types

– Single Slope ADC

– Dual Slope ADC

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 Single Slope ADC

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• A unknown analog input is given to the non inverting input of comparator.

• At the same time ramp reset is given to ramp generator. Thereafter, the

ramp generator generates a ramp starting from 0V.

• Let us assume that ramp generator produces a ramp up to 1V for every

1ms.

• Initially is compared with 0V which switches ON the comparator (+

assumed as logic 1).

• This allows the clock input to pass through the AND gate and the counter

starts counting.

• The output of the comparator is also given to timing and control unit which

allows the ramp generator to produce 1V output in 1ms of time.

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• Now 1 V is compared with and if input again the
comparator switches ON allowing the clock to the counter
to countup.

• This process continues and for each and every 1ms of time,
the ramp generator is incremented by 1V.

• Suppose if ramp generator output is greater than , the

comparator is switched OFF (- Assumed as logic 0) and the
clock input will be disconnected from entering into counter

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• Now, the counter stops and timing and control
unit issues a Latch/Strobe input to latches.
• The latches just switches the counted value to
the decoders or driver.
• The output of the driver a 7 segment LED
display. The display shows a digital value
equivalent to unknown analog input.

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 Disadvantage

• Changes in the component values induces

error.
• The drift in clock frequency causes errors.
• The conversion time is maximum if the
magnitude of input voltage is maximum.

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 Dual Slope ADC

• This type of generates two different ramps.

One with unknown analog input and other
with a known reference voltage.

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 • time is known and is unknown (not a

predetermined time). Slope at is unknown but

02/15/2024 slope at is unknown.

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• Assume a 4 bit decade counter initialized to 0000.

• Ramp output is set to 0V.

• The positive input voltage is applied to the input of

integrators inverting terminals. So output ramps
down.
• Now is negative which is less than ground applied to
non inverting terminal of OPAMP.
• Any negative voltage the output of comparator is
positive.
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• So clock passes through AND gate to the counter.
The negative ramp will proceed for the fixed time
period which is determined by the counts of counter.

Where RC is a Time constant

• The count detector detects this fixed count and issues
the reset signal to counter and connects through the
switch to integrator input.

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• The output of the integrator is now positive and rams up till 0 volt which is other
input to comparator. The comparator produces not allowing the clock to enter the
counter. The positive voltage is.

Where RC is a Time constant

• Now the amplitude of positive and negative ramp is same

• The above expression, is known and is known as predetermined time. Thus is

directly proportional to counter contents is also proportional to .The digital output

• This type of ADC is the most widely used ADC and more suitable for slowly
varying signals as input. Slow speed, High accuracy, & input hold time with high
resolution
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ADC. 26
 ADC using Voltage to Time Conversion

• The basic principle of voltage to time

conversion is to count for a fixed period of
time (fixed frequency) from a variable
frequency source or counting for a variable
period of time from a fixed frequency source.

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• is the reference voltage and it is negative.
• R and C with the OPAMP forms an Integrator
• The S/H circuit is the sample and hold circuit.
• Control voltage is used to sample input signal
and controls switch S.

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• The negative reference voltage is applied to integrators inverting
input.
• The output of integrator ramps up and compares with unknown
analog input sample (derived from S/H circuit)
• When , the comparator output is positive. During this time, is low
thus allowing the clock voltage ( to appear at CL input of counter.
• Counter starts counting till is greater than .

• When < , is negative. So cannot reach the CL input of high speed

counter. At the same time is high, the clock cannot enter the AND
gate.

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• is ON only for a period of

• is OFF for the period of during which the

counter counts.
• Whenever is at sampling time the switch ‘S’
closes and discharges the capacitor..
• During the switch Open allowing charging.
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• - Sampling Period and =

• - Sampling time

• - Holding Time

• - Input voltage

• - Integrator output voltage

• T – Duration during which clock pulses are counted

• - Control Voltage

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 Oversampling A to D Converters

• This type of ADC samples analog signal at the

rate much higher than the required sampling
rate ().
• The typical sampling rate is 16,32, or 64 times
of original sampling rate.

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 Delta Modulation
• Delta modulation (DM) developed in the 1940s is a differential pulse code modulation (DPCM)

techniques in which the derivative of the signal is quantized.

• When signal variations between the subsequent sample periods are very small, the word length of the

qunatisers can be reduced.

• With very high over sampling rates, the changes between sample periods are made very small, and

quantiser can be reduced to low bit.

• A single bit DPCM coder is known as a delta modulation

• With delta modulation, rather than transmit a coded representation of the sample, only a single bit is

transmitted, which simply indicates whether that sample is larger or smaller than the previous sample.

• If the current sample is smaller than the previous sample, a logic 0 is transmitted.

• If the current sample is larger than the previous sample, a logic 1 is transmitted.

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• The i/p analog is sampled and converted to a PAM signal.

• This PAM signal is compared with the output of DAC.

• The output of the DAC is a voltage equal to the regenerated

magnitude of the previous sample, which was stored in the up-
down counter as a binary number.

• The up-down counter is incremented or decremented depending

on whether previous sample is larger or smaller than the current
sample.

• The up-down counter is clocked at a rate equal to the sample

rate.
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• Initially up-down converter is zeroed.

• DAC output is 0V.

• First sample is taken, converted PAM signal, compared with 0V.

• The output of the comparator is logic 1 condition (+V).

• This is indicating current sample is larger in amplitude than the previous

sample.

• In next clock pulse, the up-down counter is incremented by 1.

• DAC o/p voltage is equal to the magnitude of the minimum step size.

• Logic 1 transmitted, up- down counter incremented.

• Logic 0 transmitted, up- down counter decremented.

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 Slope Overload

• The analog input signal changes at a faster rate than the DAC can maintain. The slope of the

analog signal is greater than the delta modulator can maintain and is called slope overload.

Prevention:

• Increase clock frequency

• Increase the magnitude of the minimum step size.

• Large resolution.

• Slope overload is more prevalent in analog signals that have steep slopes or whose amplitudes

vary rapidly.
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 Granular Noise

• When the original analog input signal has relatively constant amplitude, the

reconstructed signal has variations that were not present in the original signal, is

called granular noise.

Prevention:

• Decrease the step size.

• Small resolution

• Granular noise is more prevalent in analog signals that have gradual slopes and

whose
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