Booth Multiplication Algorithm
Booth Algorithm
•An efficient way to multiply two signed binary numbers
expressed in 2's complement notation :
•Reduces the number of operations by relying on blocks of
consecutive 1's
•Example:
•Y 00111110 = Y (25+24+23+22+21).
•Y 00111110 =Y × (01000000-00000010) = Y (26-21).
One addition and one subtraction
Another Eg:
Search for a run of ‘1’ bits in the multiplier
E.g. ‘0110’ has a run of 2 ‘1’ bits in the middle
Multiplying by ‘0110’ (6 in decimal) is equivalent to
multiplying by 8 and subtracting twice, since 6 x m = (8
– 2) x m = 8m – 2m (2k+1-2m) where k =3 and m=1
Description and Hardware for Booth
Multiplication
QR multiplier
Q least significant bit of QR
n
Q previous least significant bit of
n+1
QR
BR multiplicand
AC 0
SC number of bits in multiplier
Algorithm
Do SC times
QnQn+1 = 10
AC ← AC + BR + 1
QnQn+1 = 01
AC ← AC + BR
Arithmetic shift right AC& QR
SC ← SC – 1
For our example, and multiply (-9) x (-13)
The numerically larger operand (13) would
require 4 bits to represent in binary (1101). So we
must use AT LEAST 5 bits to represent the
operands, to allow for the sign bit.
Solution 2 - Booth’s Algorithm (1)…….
START
M A Q Q-1
A 0, Q-1 0
M Multiplicand
Q Multiplier
Count n
= 10 = 01
Q0, Q-1
AA-M =00 AA+M
=11
Arithmetic shift right:
A, Q, Q-1
Count Count - 1
No Yes
Count=0? END
6
Booth’s Algorithm(2)…..
Scan the bit and right of the bit of the multiplier at the same time
by control logic
If two bits =00 =11 - right shift only (A,Q,Q-1)
=01 A A +M and
right shift =10 A A - M and
right shift
To preserve the sign of the number in A and Q, arithmetic shift is
done (An-1 is not only shifted into A n-2 but also remains in A n-1)
7
Example of Booth’s Algorithm(3)….
8
Slides adapted from tan wooi haw’s
lecture notes (FOE)
M=0101, Q=1010 , - M = 1011
• Consider the multiplication of 5 x -6, both represented in 4-bit
twos complement notation, to produce an 8-bit product
M R egister A R egister Q R egister Q -1
0 1 0 1 0 0 0 0 1 0 1 0 0 Initial value
0 0 0 0 0 1 0 1 0 S hift 1st cycle
N/B: Negate the product if + 1 0 1 1
sign bit of product is 1 0 1 1 0 1 0 1 0 A A–M
negative, 1 2nd cycle
1 1 0 1 1 0 1 0 1 S hift
Negate 11100010 + 0 1 0 1
0 0 1 0 1 0 1 0 1 A A+M
1’ = 00011101
3rd cycle
2’ = 00011110 (30) 0 0 0 1 0 1 0 1 0 S hift
+ 1 0 1 1
Since sign bit is 1, it shown
1 1 0 0 0 1 0 1 0 A A–M
that it is a negative value,
4th cycle
Therefore product = -30 1 1 1 0 0 0 1 0 1 S hift
9
prod uct
Slides adapted from tan wooi
haw’s lecture notes (FOE)
M=1010, Q=1001 , - M = 0110
• Consider the multiplication of -6 x -7, both represented in
4-bit twos complement notation, to produce an 8-bit
productM R egister A R egister Q R egister Q -1
1 0 1 0 0 0 0 0 1 0 0 1 0 Initial value
+ 0 1 1 0
0 1 1 0 1 0 0 1 0 A A–M
1st cycle
0 0 1 1 0 1 0 0 1 S hift
+ 1 0 1 0
1 1 0 1 0 1 0 0 1 A A+M
2nd cycle
Product = 00101010
1 1 1 0 1 0 1 0 0 S hift
Since the sign bit is
positive , 0. 1 1 1 1 0 1 0 1 0 S hift 3rd cycle
+ 0 1 1 0
Therefore the product 0 1 0 1 0 1 0 1 0 A A–M
value is 42
4th cycle
0 0 1 0 1 0 1 0 1 S hift
10
prod uct
Flowchart for Booth Multiplication
Multiply Example: -9 × -13 = 117
BR = 10111, BR + 1 = 01001
Multiplicand in BR
Multiplier in QR Comment AC QR Qn+1 SC
00000 10011 0 5
AC ← 0 Subtract BR 01001
Qn+1 ← 0
SC ← n 01001
Ashr 00100 11001 1 4
= 10 = 01 Ashr 00010 01100 1 3
QnQn+1 Add BR 10111
11001
AC ← AC + BR + 1 = 00 AC ← AC + BR
Ashr 11100 10110 0 2
= 11 Ashr 11110 01011 0 1
ashr (AC & QR)
Subtract BR 01001
SC ← SC – 1 00111
Ashr 00011 10101 1 0
≠0 =0
SC
END
Multiply 7 x 3 using above signed 2's compliment binary
multiplication.
Multiplicand =7 Binary equivalent is 0111M
Multiplier = 3 Binary equivalent is 0011Q
-7 Binary equivalent is 1001 -M
A 0000 A 0101
-M 1001 M 0111
A 1001 A 0010 =10
Step A Q Qn+1 Action Count
1 0000 0011 0 Initial 4
2 1001 0011 0 AA-M
2 1100 1001 1 Shift 3
3 1110 0100 1 Shift 2
4 0101 0100 1 AA+M
4 0010 1010 0 Shift 1
5 0001 0101 0 Shift 0
Examples
Multiply the following using Booth’s algorithm
7 x -3
-7 x 3
-7 x -3
11 x 13
-11 x 13
11 x -13
-11 x -13
Reference
Morris Mano, “Computer System Architecture”, Pearson
Education, 3rd edition (Chapter 10)