6-Resource Sharing
6-Resource Sharing
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© Giovanni De Micheli – All rights reserved
Module 1
Objectives
Motivation and problem formulation
Flat and hierarchical graphs
Functional and memory resources
Extension to module selection
Allocation:
Number of resources available
Binding:
Relation between operations and resources
Sharing:
Many-to-one relation
Optimum binding/sharing:
Minimize the resource usage
Limiting cases:
Dedicated resources
One resource per operation
No sharing
Compatibility graph
Compatibility graph:
1 2
Vertices: operations
Edges: compatibility relation 5
3 4
Conflict graph:
Complement of compatibility graph Conflict graph
1 2
3 4
t2 s=x+y t=x-y 3 4
t3 z=a+t 5
Conflict Compatibility
1 2 1 2
5 5
3 4 3 4
Coloring Partitioning
ALU1: 1,3,5
ALU2: 2,4
1 2 10
TIME 1 * * +
3 6 11
TIME 2 * * <
4 7 8
TIME 3 - * *
5 9
TIME 4 - +
NOP
9
3 1 8
4 10
7 6 2
5 11
NOP 0
1 2 10
* * + 10
TIME 1 1 2
3 6 11
* 11
TIME 2 * < 3 6
4 7 8
- * *
TIME 3 4 7 8
5 9
TIME 4 - +
5 9
n
NOP
1 6 1
4
7 4 3
7
3
2 5
5
Conflict graph
Intervals
1 6
0 1 2 3 4 5 6 7 8
7 4 3 1 2 3
6 7 5
2 5 4
LEFT_EDGE(I) {
Sort elements of I in a list L in ascending order of li;
c = 0;
while (some interval has not been colored) do {
S = Ø;
r = 0;
while ( exists s є L such that ls > r ) do {
s = First element in the list L with ls > r;
S = S U {s};
r = rs;
Delete s from L;
}
c = c + 1;
Label elements of S with color c;
}
}
a
+
TIME 1 a a
* a 2
TIME 2
2
TIME 3 2 *
*
3 3
TIME 4 * *
4 3
TIME 5 a 4 a 4
*
+ *
TIME 6 a
*
TIME 7
NOP NOP a
TIME 1 a a
TIME 2 BR c d c d c d
TIME 3 b b
TIME 4 b
NOP NOP
Given:
Variable lifetime conflict graph
Find:
Minimum number of registers storing all the variables
Key point:
Interval graph
Left-edge algorithm (polynomial-time complexity)
1 2 z1 z2
TIME 1 * * z1 z2
z1 z2
3 6
TIME 2 * * z3 z4
z3 z4
z4
z3 4 7
TIME 3 - *
z5 z6 z5 z6
z6
z5
TIME 4 5
-
u
y
x
u 3 x u dx y u dx x dx x
1 2 10
TIME 1 * * +
z1 z2 3 a z1 z2 u y x
6
TIME 2 3 11
* * <
dx z3 z4
z3 z4 8
4
7 c
TIME 3 *
- *
y z7
z5 z6 z7
z5 z6
TIME 4 - 5 + 9
u y
y
u
(a) (b)
z1
z2 u
x
z1 z2
1
u y 4 2 z4 z3
x z3 z4 y
z5 z6
z7
z6
z5
z7
One bus:
3 variables can be transferred
Two busses:
All variables can be transferred
(c) Giovanni De Micheli 31
Module selection problem
Extension of resource sharing
Library of resources:
More than one resource per type
Example:
Ripple-carry adder (small and slow)
Carry look-ahead adder (big and fast)
Resource modeling:
Resource subtypes with
( area, delay ) parameters
Heuristic algorithm
Determine minimum latency with fastest resource subtypes
Recover area by using slower resources on non-critical paths
2 10
TIME 2 * +
3 8 11
* * <
TIME 3
4 7
TIME 4 - *
5 (2,2) 9
TIME 5 - +
n
NOP
Multipliers with:
( Area, delay ) = ( 5,1 ) and ( 2,2 )
Latency bound of 5
(1,1)
1 (1,2) (2,1) 10
* 2 +
TIME 1 *
3 6 11
TIME 2 * * <
4 7 * 8
TIME 3 - *
(2,2)
5
TIME 4 - + 9
n
NOP
Latency bound of 4
Fast multipliers for { v1 , v2 , v3 }
Slower multiplier can be used elsewhere
Less sharing
Minimum-latency design uses fast multipliers only
Impossible to use slow multipliers
c
U
DATA-PATH CONTROL-UNIT
Logic model:
Synchronous FSM
Physical implementation:
Hard-wired or distributed FSM
Microcode
1 2 6 8 1
TIME 1
* * * * + 0
7 9 1
TIME 2 3
* * + < 1
4
TIME 3 -
TIME 4 5
-
reset reset
NOP n
1,2,6,8,10 reset’ 3,7,9,11
s1 s2
reset
reset’
5
s4 reset’ 4
s3