Operating Systems

CS2006

Lecture: 3
Computer-System Architecture
What is a Computer
System?
Computer
System
Consists of CPU and device controllers
Connected through a common Bus.
Providing access to shared memory
Each device controller is in charge of a specific
device
Disk drives
Audio devices
Video display
 Computer System
Organization
 Computer-system operation
 One or more CPUs, device controllers connect through common
bus providing access to shared memory
 Concurrent execution of CPUs and devices competing for memory
cycles
 Computer-System Operation
 I/O devices and the CPU can execute concurrently

 Each device controller is in charge of a particular device type

 Each device controller has a local buffer

 CPU moves data from/to main memory to/from local buffers

 Cf) DMA (Direct Memory Access)

 I/O is from the device to local buffer of controller

 Device controller informs CPU that it has finished its operation by causing an
interrupt
 Major Computer
Components

7
 1- CPU
 Registers
 Program Counter (PC)
 Instruction Register (IR)
 Program Status Word (PSW)
 General-purpose registers
 Instruction Set Architecture
 RISC vs. CISC
 Intel, SPARC, MIPS, PowerPC, ARM, Alpha, …
 Pipelining
 Fetch, Decode, Execute, Write Back, etc.
 Instruction-Level Parallelism(ILP)
 Superscalar vs. VLIW
 Simultaneous Multithreading
 Processo
r
Internal Register
Memory Address Register (MAR)
Specifies the address for next read or write
Memory Buffer Register (MBR)
Contains data written into memory or receives data
read from memory
I/O address register
I/O buffer register

9
 User-Visible
Register
May be read by user processes
Available to all programs – application programs
and system programs
Types of registers
Data
Address
Index
Segment pointer
Stack pointer

12
Control and Status
Register
Program Counter (PC)
Contains the address of an instruction to be
fetched
Instruction Register (IR)
Contains the instruction most recently fetched
Program Status Word (PSW)
Condition codes
Interrupt enable/disable
Supervisor/user mode
 2- Memory Structure
 Storage systems organized in hierarchy
 Speed
 Cost
 Volatility

 Caching
 copying information into faster storage system
 main memory can be viewed as a last cache for secondary
storage
Storage-Device Hierarchy
Memory Hierarchy
 Caching
 Use of high-speed memory to hold recently-accessed data

 Requires a cache management policy

 Write-through vs. Write-back

 Caching introduces another level in storage hierarchy. This requires data that
is simultaneously stored in more than one level to be consistent
 Cache coherency
Migration of A From Disk to Register
 3- I/O Structure
 After I/O starts, control returns to user program only upon I/O completion
 Wait instruction idles the CPU until the next interrupt
 Wait loop (contention for memory access)
 At most one I/O request is outstanding at a time, no simultaneous I/O processing

 After I/O starts, control returns to user program without waiting for I/O
completion
 System call – request to the operating system to allow user to wait for I/O
completion
 Device-status table contains entry for each I/O device indicating its type, address,
and state
 Operating system indexes into I/O device table to determine device status and to
modify table entry to include interrupt
Device
Controllers
 I/O devices generally consists of two parts:
 An Electronic component: Device Controller
 A Mechanical component: The device itself
 Each device controller is in charge of a specific
device
 It maintains
 Some local storage buffer
 A set of special purpose register
 Accepts command from the Operating System
 For example to read data from the device.
Device
Controllers
A Device controller might accept a command:
Read
Sector 11,206
The device controller would:
Determine the current position of the head
Move the head to the required location
Accept data bit by bit
Store in a local buffer
Perform checksum on the data
Controllers contain small embedded programs to
carry out all this work.
Device
Drivers
 Who would initiate the controller
 Who would determine read/write
 Who would tell the sector number
 A part of operating system called Device Driver
 Software or Hardware?
 Software that talks to a controller
 Gives it command
 Accept Responses
 Same for all controllers?
 Different software for different type of controllers
 Each controller manufacturer has to supply a driver for
each operating system it supports
Device Status
Table
One entry per I/O device
Keeps record of
Device’s type
Address
State
 Not functioning
 Idle
 Busy
If the device is busy, the new request is saved in a
queue
Device Status
Table

9
 A
The operating system
Question
Gets an input
Performs a
computation
Produces an output
And Quits
Yes or no?

• The operating system is a Reactive Program

Operating
System
 Modern Operating Systems are Interrupt driven
 If
 No process to execute
 No I/O device to service
 No user to whom to respond
 Then
 OS will sit quietly, waiting for something to happen
 This something is Interrupt
 At a particular time either a user program is running or
operating system is running
Interrupt
s Interrupts are signals by external devices, normally

I/O devices.They tell the CPU to stop its current
activities and execute the appropriate part of the
operating system.
Types of
Interrupts
 There are three (or broadly two) types of
interrupts:

• Hardware Interrupts
• Software Interrupts
• Traps
Hardware
Interrupts
 Hardware Interrupts - generated by hardware devices to
signal that they need some attention from the OS.
 They may have just received some data (e.g., keystrokes on the keyboard
or an data on the Ethernet card);

 or they have just completed a task which the operating system

previously requested, such as transferring data between the hard drive
and memory.
Software
Interrupts
 Software Interrupts are generated by programs
when they want to request a system call to be
performed by the operating system.
Trap
s Traps are generated by the CPU itself to indicate

that some error or condition occurred for which
assistance from the operating system is needed.
Interrupts and
Traps
 Interrupts are hardware interrupts, while traps are
software- invoked interrupts.

The term Trap is used interchangeably with the term

Exception (which is an automatically occurring
software interrupt).
Interrupts and
Traps
 Simple Instruction
Cycle

23
Interrupt
s Suspends the normal

sequence of
execution
Used to improve
processor utilization
Interrupt
Handling
 Different routines handle different type of interrupts.
 Called Interrupt Service Routine (ISR)
 When the CPU is interrupted it stops what it is doing
 The address of the interrupted instruction is saved
 A generic routine is run
 This routine examines the nature of interrupt
 Calls the corresponding ISR
 The ISR’s are usually stored in the lower part of the memory
 After the interrupt is serviced, the saved address is loaded to
the Program Counter
 The Interrupted computation can resume as though the
interrupt had not occurred.
Interrupt
Cycle
 Interrupt
Timeline

27
 Simple Interrupt
Processing

28
 Multiple
Interrupts
 Disable interrupts while an interrupt is being
processed

29
 Multiple
Interrupts
 Define Priorities for
interrupts

30
 I/O
 How does the kernel notice an I/O has finished?
 Polling
Control
 Hardware interrupt
 I/O Control
(Cont’d)
Device interrupts

CPU stops current operation, switches to kernel mode, and

saves current PC and other state on kernel stack

CPU fetches proper vector from vector table and branches to

that address (to routine to handle interrupt)

Interrupt routine examines device database and performs

action required by interrupt

Handler completes operation, restores saved (interrupt state)

and returns to user mode (or calls scheduler to switch to
another program)
I/O
Interrupts
 I/O requested by user program
Control transferred to OS
The Device Driver loads appropriate registers within
the device controller
The device controller examines their contents
 If Read request:Transfer data from device to local buffer
Once the data transfer is complete informs the CPU
by interrupt
Two I/O
methods
 1. Synchronous
I/O
 The OS makes the CPU wait till the I/O complete interrupt is
generated
 How can a CPU wait, somehow it has to do F->D->E ??
 Wait can be accomplished by jumping to an infinite loop code in OS:
Loop: jump Loop
 If the devices does not support interrupts
 They will just set a flag in their register to indicate I/O complete
 The above loop would require to include Polling such devices as well
1. Synchronous
I/O
If the CPU always has to wait for the I/O
completion then the number of outstanding I/O
requests is?
 Exactly One
So, whenever the I/O complete interrupt is
generated the OS knows the source device
Drawback?
Excludes concurrent I/O operations to several
devices
 1. Synchronous
I/O Issues Read command to I/O
CPU -> I/O
module

Read status of I/O module I/O -> CPU

Not
Ready
Check
Error Condition
Status
Ready
Read word from I/O module I/O -> CPU

Write word into memory CPU -> memory

No
Done

35 Yes? Next Instruction

2. Asynchronous
I/O
Start the I/O request

Return control immediately to the user process
If the current user program cant run without the I/O,
let the current process wait
CPU: Schedule some other user program or operating
system code
If no process ready to run, then still need the idle
loop
 2. Asynchronous
I/O
The number of outstanding I/O requests
is?
 More then One
Need to keep track of multiple I/O
requests
2. Asynchronous
I/O Issues Read command to I/O
module
CPU -> I/O Do something else

Read status of I/O module I/O -> CPU

Interrupt

Check
Error Condition
Status
Ready
Read word from I/O module I/O -> CPU

Write word into memory CPU -> memory

No
Done

Ye? Next Instruction

s
2. Asynchronous
I/O
 The I/O controller interrupts when it needs to
be serviced
The OS determines the I/O controller
Processor reads the word of data from I/O controller
to the memory
Updates the status in the Device Status table
In case of I/O complete interrupt, checks the
additional request
The control is returned to the user program
3. Direct Memory Access
(DMA)
 Drawback of Asynchronous I/O?
 Any data transfer must traverse a path through the
processor
 In case of DMA, the following info to the DMA module:
 Read or Write request
 Address of the I/O device
 Starting location in memory to read from or write to
 Number of words
 The DMA module is then asked to start data transfer
 The above operations are performed by Device Driver
How a Modern Computer
Works

A von Neumann architecture

3. Direct Memory
Access
The processor can continue with its work
The DMA module transfer data directly from the
device to the main memory
But how many accesses to memory are possible at a
time
In order to do so, it has to “steal” cycles
from processor…Cycle Stealing
Since, only one access to memory is possible
at a time
3. Direct Memory
Access
The processor has to wait in the mean while for
memory
This would slow down the processor
But still more efficient than the previous two
cases
After the block transfer is completed, a single
I/O interrupt will be generated by the DMA
module.
3. Direct Memory
Access
Issues Read
CPU -> DMA
command
to I/O Do something
module else

Read status
Interrupt
of DMA
module DMA -> CPU

Ye
Next Instruction
s

Direct Memory Access

 Direct Memory Access
(DMA)
 Used for high-speed I/O devices able to transmit information at close
to memory speeds
 Device controller transfers blocks of data from buffer storage directly to
main memory without CPU intervention
 Only one interrupt is generated per block, rather than the one interrupt
per byte
 Bus arbitration between cache-memory and DMA transfers
 Memory cache must be consistent with DMA

45
 Interrupts and Exceptions
 Interrupts
 Generated by hardware devices
 Triggered by a signal in INTR or NMI pins (Pentium)
 Asynchronous

 Exceptions
 Generated by software executing instructions
 INT instruction in IA32
 Page fault, protection fault
 Synchronous
 Trap (expected) or fault (unexpected)
Referenc
ehttp://www.cs.toronto.edu/~demke/469F.06/Lectures/Lecture6.pdf
 Chapter 1, Operating Systems by William Stallings

 http://www.tldp.org/LDP/tlk/dd/interrupts.html
 http://en.wikibooks.org/wiki/Operating_System_Design/Processes/Interrupt
 http://www.slideshare.net/guest2e9811e/interrupts
 https://amser.org/g11619
 http://www.eecs.harvard.edu/~mdw/course/cs161/notes/osstructure.pdf
 http:/ /www.sci.brooklyn.cuny.edu/~jniu/teaching/csc33200/files/09
10- ComputerSystemOverview02.pdf
 http://siber.cankaya.edu.tr/OperatingSystems/ceng328/node87.html
 http://www.personal.kent.edu/~rmuhamma/OpSystems/Myos/processC
ontrol.htm
 http://www.tutorialspoint.com/operating_system/os_processes.htm
 http://wiki.answers.com/Q/Explain_process_control_block
 https://msdn.microsoft.com/en-us/library/windows/desktop/
aa365683(v=vs.85).aspx