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VHDL Statements

The document discusses various VHDL statements that can be used for modeling digital circuits. It distinguishes between concurrent statements that execute in parallel and sequential statements that execute in a sequential order. Some key statements mentioned include process (sequential), signal assignment (concurrent), conditional signal assignment, case statement, loops, and blocks. The document provides syntax and examples for many of these statements.

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P. VENKATESHWARI
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25 views

VHDL Statements

The document discusses various VHDL statements that can be used for modeling digital circuits. It distinguishes between concurrent statements that execute in parallel and sequential statements that execute in a sequential order. Some key statements mentioned include process (sequential), signal assignment (concurrent), conditional signal assignment, case statement, loops, and blocks. The document provides syntax and examples for many of these statements.

Uploaded by

P. VENKATESHWARI
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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VHDL statements

Concurrent and sequential statement


Concurrent Statement Sequential Statemnet
Begin Begin
Statement
Statement Statement
Statement
End Statement

Statement

End
No significance of order of statement It is executed one after another in sequential order.
Process is a concurrent statement Statements inside a process are executed sequentially
Cont….
Concurrent Sequential
Describes the connection between lower level Sequence of related events
components and combinational logic Such as state machines
It has two forms conditional assignment and selective It has only a single form which is an unconditional
assignment C<= a and b after 5ns;
Data flow Behavioural

BLOCK, PROCESS, ASSERT and COMPONENT PROCESS, IF, CASE, LOOP, EXIT, WAIT and Subprogram
Sequential statements
• Process
• Sensitivity list
• Process with incomplete sensitivity list
• WAIT
• Combinational and Sequential Process
• Signal Assignment
• Variable Assignment
Process
• It can have sensitivity list or wait
• Without this it runs forever at time 0.
• Syntax:
simple_1: process [(sensitivity_list)]
[type declaration]
[constant_declaration] constant x: integer:=4;
[variable_declaration]
[subprogram_declaration]
Begin
Sequential statements
End process simple_1;
Sensitivity list
• List of signals to which the process is sensitive.
• When a sensitivity list is specified the process will suspend only the
last statement , until a new event is produced on the signals in the
sensitivity list.
Syntax:
Process( a,b,c) sensitivity list
Y<= a and b or c;
Process with incomplete sensitivity list

• Missing some signals in the sensitivity list.

Syntax
Process(a,b)
WAIT

• Syntax:
Wait until signal_condition;
Wait on signal 1, signal 2,…;
Wait for time;

Eg:
Wait until (clk=‘1’);
Wait on clk;
Wait for 50ns;
Combinational and Sequential Process

• Process may be used in combinational and sequential ckts.


In sequential ckt, wait or if signal events should be used.
Entity and_gate is
Port( a,b,c: in bit; y:out bit);
End and_gate;
Architecture df of and_gate is
Begin
Process(a,b,c)
Begin
Y<= a and b and c;
End process;
End df;
Cont…
elsif
Elsif (j=‘1’ and k=‘0’)
Process(clk)
then
Variable state: bit:=‘0’;
State:=‘1’;
Begin
Elsif (j=‘0’ and k=‘0’)
If clk’event and clk=‘1’
then
then
State:=state;
If (j=‘1’ and k=‘1’) then
End if;
State:= not state;
Q<=state;
Elsif (j=‘0’ and k=‘1’)
Qbar<=not state;
then
End if;
State: =‘0’;
End process;
Signal Assignment (itself)

• Simple signal assignment statement.


Syntax:
Signal-object<=exp [after delay value];

X<= a and b after 10ns;


Variable Assignment (place of usage)
• Variables are declared and used inside a process statement.
• Syntax:
Variable-object :=expression;
Eg:
X:= a and b;
Conditional statements
• IF statement
• Case
• Loop
• Next
• Exit
• Null
• Assert a=‘false’
• Report (error , failure)
• Return
• Procedure call statement
IF statement (if-then-elsif)
If condition then
statement_sequence
Elsif condition then
statement_sequence
Else
statement_sequence
End if;

If (a=‘0’ & b=‘1’ | c=‘0’)


Case

Case exp is
When options_1=>
Statement
……
When options_n=>
Statement
When others=>
Statement
End case;

Case sel is
When ‘0’=> y<=a
When ‘1’ => y<=b
End case;
case expression is
When “0000”=>
Statement_sequence0
When 0001|val2|val3 =>
Case a is
Statement1 When “00”|”01”|”10”=>
When val4 to val8=> Y<=‘0’;
When others=>
Statement2
Y<‘1’;
When val9 to val15|val16 to val20=> End case
Statement3
When others=>
Statement4
End case;
Architecture beh of and_gate is
Begin
Process(a,b)
variable temp:std_logic_vector(1 downto 0);
Begin
temp:=a&b;
Case temp is
When “00” => y<=‘0’;
When “01” => y<=‘0’;
When “10” => y<=‘0’;
When “11” => y<=‘1’;
When others => y<= ‘0’;
End case;
End process;
End beh;
Loop

Simple loop, while loop and for loop

[label:] loop
Statement
End loop [label];

[label:] while ( a<5) loop


Y<= not c;
a<=a+1;
End loop [label];

For i in 5 downto 0 loop


Dout(i)<=‘0’;
End loop;
Next

• Current iteration is skipped and the execution must be continued with


the next iteration.
• ‘next’ statement can be used only inside a loop

Next [label] when condition;


Next when “11”;
EXIT
To exit from any iteration causing error

Exit [label] when condition;

Loop_one: loop
X<=x+1;
Exit loop_one when x>5;
End loop loop_one;
NULL
• It states that no action occurs
NULL;

When others=> NULL;


ASSERT
• It is useful for displaying warning or error messages during the
simulation.
• This statement tests the value of a Boolean condition and displays the
message specified if the condition goes false.

Assert condition
[report character_string]
[severity severity_level]; [note warning error failure]
RETURN
• Allowed within the subprogram
• It is a required statement in a function where function returns its own
function value

[label:] return expression;


Procedure call
• If a call is placed inside a sequential body it is executed in natural
sequence.
• If the call is placed in a concurrent body, the procedure is invoked
when event
Concurrent statements
• Simple signal assignment
• Conditional signal
• Selected signal assignment
• Block statement
• Guarded signal
• Generate statement
• Others and unaffected
• Concurrent assert statement
Simple signal assignment

• It appears directly inside the architecture.


• All statements are executed in a same simulation cycle
Syntax:
X<= a and b;
Y<= not c;
Z<= X or Y;
F<=d and Z;
Conditional signal

• Similar to if then else statement


Syntax:
Signal<= [expression when condition else]
[expression when condition else….]
Expression;

Y<= a when sel=“00” else


b when sel =“01” else
c when sel=“10” else
d when others;
End dataflow;
Selected signal assignment

• The selected signal assignment statement allows to select a source expression based on a
condition.
Syntax:
With selection_expression select
Signal<= express_1 when options_1,
express_n when options_n,
Expression when others;

With sel select


Y<= a when “00”,
b when “01”,
c when “10”,
d when others;
Block statement

• It separates part of the code without adding any functionality.


Syntax:
Block_label : block
<declaration>
Begin
<concurrent statements>
End block block_label;
Block1: block
Signal x,y,z: std_logic;
Begin
X<= a and b;
Block2: block
Begin
Y<= not c;
End block block2;
Block3: block
Signal y,z: std_logic;
Begin
Z=x xor c;
Y<= not z;
End block block3;
F<= d and z;
End block block1;
Guarded signal

Signal_name<= guarded a after 5ns;


A driver is automatically disconnected as a result of a guarded signal
assignment the guard associated to the block is false.
Generate statement

• It allows a section of code to be repeated a number of times, thus creating


several instances of the same assignment

For identifier in range generate


[concurrent assignments]
End generate;

If condition generate
[concurrent assignment]
End generate;
Others and unaffected
Concurrent assert statement

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