The document provides an overview of the ARM architecture. It describes ARM as a RISC microprocessor developed in the 1980s that is widely used in low-power embedded applications. Key points include ARM's load/store architecture, 32 general-purpose registers, conditional execution, and compressed Thumb instruction set. The document also covers ARM's pipeline organization, operating modes, instruction types like data processing and load/store, and its history and commercial success in embedded systems.
The document provides an overview of the ARM architecture. It describes ARM as a RISC microprocessor developed in the 1980s that is widely used in low-power embedded applications. Key points include ARM's load/store architecture, 32 general-purpose registers, conditional execution, and compressed Thumb instruction set. The document also covers ARM's pipeline organization, operating modes, instruction types like data processing and load/store, and its history and commercial success in embedded systems.
The document provides an overview of the ARM architecture. It describes ARM as a RISC microprocessor developed in the 1980s that is widely used in low-power embedded applications. Key points include ARM's load/store architecture, 32 general-purpose registers, conditional execution, and compressed Thumb instruction set. The document also covers ARM's pipeline organization, operating modes, instruction types like data processing and load/store, and its history and commercial success in embedded systems.
The document provides an overview of the ARM architecture. It describes ARM as a RISC microprocessor developed in the 1980s that is widely used in low-power embedded applications. Key points include ARM's load/store architecture, 32 general-purpose registers, conditional execution, and compressed Thumb instruction set. The document also covers ARM's pipeline organization, operating modes, instruction types like data processing and load/store, and its history and commercial success in embedded systems.
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ARM
1 What Is ARM? Advanced RISC Machine
First RISC microprocessor
for commercial use
Market-leader for low-power
and cost-sensitive embedded applications
2 ARM Powered Products
3 Features Architectural simplicity which allows Very small implementations which result in Very low power consumption
4 The History of ARM Developed at Acorn Computers Limited, of Cambridge, England, between 1983 and 1985 Problems with CISC: Slower than memory parts Clock cycles per instruction
5 ARM Architecture Typical RISC architecture: Large uniform register file Load/store architecture Simple addressing modes Uniform and fixed-length instruction fields
6 ARM Architecture (2) Enhancements: Each instruction controls the ALU and shifter Auto-increment and auto-decrement addressing modes Multiple Load/Store Conditional execution
7 ARM Architecture (3)
Results: High performance Low code size Low power consumption Low silicon area
8 9 Pipeline Organization Increases speed – most instructions executed in single cycle Versions: 3-stage (ARM7TDMI and earlier) 5-stage (ARMS, ARM9TDMI) 6-stage (ARM10TDMI)
10 Pipeline Organization (2) 3-stage pipeline: Fetch – Decode - Execute Three-cycle latency, one instruction per cycle throughput
i n s t i Fetch Decode Execute r u Fetch Decode Execute i+1 c t i i+2 Fetch Decode Execute o cycle n t t+1 t+2 t+3 t+4 11 Pipeline Organization (3) 5-stage pipeline: Stages: Reduces work per cycle => allows higher clock frequency Fetch reduction of CPI Decode (average number of clock Cycles Per Instruction) Execute
Buffer/data
Write-back
12 Pipeline Organization (4) Pipeline flushed and refilled on branch, causing execution to slow down Special features in instruction set eliminate small jumps in code to obtain the best flow through pipeline
13 Operating Modes Seven operating modes: User Privileged: System (version 4 and above) FIQ IRQ Abort exception modes Undefined Supervisor
14 Operating Modes (2) User mode: Exception modes: Normal program Entered execution mode upon exception System resources Full access unavailable to system resources Mode changed Mode changed freely by exception only
15 ARM Registers
31 general-purpose 32-bit registers
16 visible, R0 – R15 Others speed up the exception process
16 ARM Registers (2) Special roles: Hardware R14 – Link Register (LR): optionally holds return address for branch instructions R15 – Program Counter (PC) Software R13 - Stack Pointer (SP)
17 ARM Registers (3) Current Program Status Register (CPSR) Saved Program Status Register (SPSR) On exception, entering mod mode: CPSR SPSR_mod R13, R14 replaced by R13_mod, R14_mod In case of FIQ mode R7 – R12 also replaced
20 ARM Instruction Set Features: Load/Store architecture 3-address data processing instructions Conditional execution Load/Store multiple registers Shift & ALU operation in single clock cycle
21 ARM Instruction Set (3)
ARM instruction set
Data processing instructions Data transfer instructions Block transfer instructions Branching instructions
22 Data Processing Instructions Arithmetic and logical operations 3-address format: Two 32-bit operands (op1 is register, op2 is register or immediate) 32-bit result placed in a register Barrel shifter for op2 allows full 32-bit shift within instruction cycle
25 Data Processing Instructions (4) Conditional execution: Each data processing instruction prefixed by condition code Result – smooth flow of instructions through pipeline 16 condition codes: unsigned signed greater EQ equal MI negative HI GT higher than positive or unsigned lower signed less NE not equal PL LS LE zero or same than or equal unsigned signed greater CS higher or VS overflow GE AL always than or equal same unsigned signed less special CC VC no overflow LT NV 26 lower than purpose Data Processing Instructions (5)
e.g.:
if (z==1) R1=R2+(R3*4)
compiles to
EQADDS R1,R2,R3, LSL #2
( SINGLE INSTRUCTION ! )
27 Data Transfer Instructions Load/store instructions Used to move signed and unsigned Word, Half Word and Byte to and from registers Can be used to load PC (if target address is beyond branch instruction range)
LDR Load Word STR Store Word
LDRH Load Half Word STRH Store Half Word LDRSH Load Signed Half Word STRSH Store Signed Half Word LDRB Load Byte STRB Store Byte LDRSB Load Signed Byte STRSB Store Signed Byte 28 Block Transfer Instructions
Load/Store Multiple instructions
(LDM/STM) Mi Whole register bank or a LDM Mi+1 subset R0 Mi+2 R1 copied to memory or restored R2 with single instruction Mi+14 Mi+15 R14 STM R15 29 Modifying the Status Registers Only indirectly R0 R1 MSR moves contents from CPSR/SPSR MRS
to selected GPR R7
CPSR MSR R8 MRS moves contents SPSR from selected GPR R14 to CPSR/SPSR R15
Only in privileged modes 30 Thumb Instruction Set Compressed form of ARM Instructions stored as 16-bit, Decompressed into ARM instructions and Executed Lower performance (ARM 40% faster) Higher density (THUMB saves 30% space) Optimal – “interworking” (combining two sets) – compiler supported
