Verilog Lecture 2 - Noopur
Verilog Lecture 2 - Noopur
Verilog Lecture 2 - Noopur
properties.
Net Types
Example: Net Declarations
Wire a,b, c; // Three 1-bit nets.
wire [7:0] d, e, f; // Three 8-bit vectors.
supply1 vcc;
supply0 gnd;
Vectors & their ranges
In Verilog, a wire can be 1 bit wide or much wider. A wire that is more
than 1 bit wide is called a vector in Verilog. Although such a wire is also
known as a bus.
The maximum width of a vector is dependent on the simulator being
used. The IEEE 1364 standard states that a simulator must support at
least 1024-bit wide vectors.
To declare a wire more than one bit wide, a range declaration is used.
Ranges
Ranges specify the most-significant and least-significant indexes of a
vector.
Ranges can be either ascending or descending.
The range [7:0] is an 8-bit range, same as [0:7].
Furthermore, ranges do not need to be zero-based.
The range [682:690] is a 9-bit range.
Regs
Regs are used for modeling in procedural blocks.
The reg data type does not always imply modeling of
combinatorial logic.
A register can be 1 bit wide or declared a vector, just
as with nets.
Vector registers can be accessed a bit at a time or a
part at a time.
Example 2: Reg
reg a, b, c; // Three 1-bit registers.
reg [7:0] d, e, f; // Three 8-bit registers.
e[7]; // Refers to the most significant bit of e.
d[3:0] ;// Refers to the four Least significant bits of d
Arrays of registers: Memories
Memories are arrays of registers. A memory
declaration is similar to a reg declaration with the
addition of the range of words in the memory.
The range of words can be ascending or descending, as
machine-dependent.
Integers are signed and regs are unsigned.
Like integers, reals are 32-bit floating-point values.
Integers and reals are difficult to pass through ports
simulation time.
$time is double the size of an integer (usually 64 bits)
and is unsigned.
The $realtime returns a value as a real number. This
(32 bits).
For backwards compatibility, you can declare
parameters with ranges to make them bigger or smaller
than their default size.
Parameters may be strings.
Strings
Verilog does not have a unique string data type.
Rather, strings are stored in long registers using 8 bits
Results
The string Hello Verilog is stored as
48656c6c6f20566572696c6f67
Procedural Assignments
The data types reg, integer, real, and time can only be
assigned values in procedural blocks of code. These
assignments are called procedural assignments.
When the statement is executed, the variable on the
wire.
The left-hand side of a procedural assignment is a reg.
Types of Procedural Assignment
There are three varieties of the procedural assignment:
1. The Blocking procedural assignment
2. The non-blocking procedural assignment
3. The procedural assignment with an intra-assignment
delay
Blocking procedural assignment
Blocking assignment executes "in series" because a
blocking assignment blocks execution of the next
statement until it completes.
The results of the next statement may depend on the
executed.
Example 7:
module Blocking_assign;
integer i, j;
reg [7:0] a, b;
initial begin
i = 3;
j = 4;
a = i + j;
b = a + 1;
#10 i = a;
j = b;
end
endmodule
Non-blocking Assignment
Non-blocking assignment executes in parallel because it
describes assignments that all occur at the same time.
The right hand side is evaluated immediately and assignment to
the left hand side is postponed until other evaluation in the
current time step are completed.
The result of a statement on the 2nd line will not depend on the
results of the statement on the 1st line.
The non-blocking assignment uses a different assignment
operator “<=”.
You can use the non-blocking procedural statement whenever
you want to make several register assignments within the same
time step without regard to order or dependence upon each other.
Example 8:
module nonblocking (clk,a,c);
input clk;
input a;
output c;
wire a, clk;
reg b, c;
always @ (posedge clk )
begin
b <= a;
c <= b;
end
endmodule
Example 9:
1. module block_nonblock();
2. reg a, b, c, d , e, f ;
3. // Blocking assignments
4. initial begin
5. a = #10 1'b1;// The simulator assigns 1 to a at time 10
6. b = #20 1'b0;// The simulator assigns 0 to b at time 30
7. c = #40 1'b1;// The simulator assigns 1 to c at time 70
8. end
9.
10. // Nonblocking assignments
11. initial begin
12. d <= #10 1'b1;// The simulator assigns 1 to d at time 10
13. e <= #20 1'b0;// The simulator assigns 0 to e at time 20
14. f <= #40 1'b1;// The simulator assigns 1 to f at time 40
15. end
16.
17. endmodule
The procedural assignment with an intra-
assignment delay
The intra-assignment delay is a special form of the
procedural assignment with a delay in the middle.
With the delay on the right-hand side of the equal
vector.
Some operators return a single-bit value even if they
operators.
Register data types are used as unsigned values
first operand.
If any operand bit value is the unknown value x, then
statement in an expression.
The first operand is logically evaluated.
If it is true, the second operand is returned.
If the first operand is not true, the third operand is
returned.
Concatenations
You can make larger operands with concatenations.
Concatenations are legal both as a result on the left-
concatenation.
// A = 1'b1, B = 2'b00, C = 2'b10, D = 3'b110
Y = {B , C} // Result Y is 4'b0010
Y = {A , B , C , D , 3'b001} // Result Y is 11'b10010110001
Y = {A , B[0], C[1]} // Result Y is 3'b101
Example 1:
reg [3:0] a, b;
reg [7:0] c, d;
reg [11:0] e, f;
c = {a,b}; // The most significant bit of c is the most
significant bit of a.
e = {b,a,b};
f = {a,d}; // 4 bits + 8 bits = 12 bits.
Replication Operator
Repetitive concatenation of the same number can be expressed by using a
replication constant. A replication constant specifies how many times to
replicate the number inside the brackets ( { } ).
reg A;
reg [1:0] B, C;
reg [2:0] D;
A = 1'b1; B = 2'b00; C = 2'b10; D = 3'b110;
Y = { 4{A} } // Result Y is 4'b1111
Y = { 4{A} , 2{B} } // Result Y is 8'b11110000
Y = { 4{A} , 2{B} , C } // Result Y is 8'b1111000010
Signed Operations
Nets, regs, and times in Verilog are unsigned; only
integer and real types are signed by default.
The signed keyword is used to represent signed
declarations.
Signed values use 2's complement format.
Example 2:
module signunsign(a, b, c, d);
input [7:0] a; // unsigned
input signed [7:0] b; // signed
output [7:0] c; // unsigned
output signed [7:0] d; //signed
wire signed [7:0] e; // signed.
reg signed [7:0] f; // signed.
reg [7:0] g; // unsigned
endmodule
Case Statement
The keyword are case, endcase, default.
Syntax:
Case(expression)
label 01:statement_01;
label 02:statement_02;
label 03:statement_03;
….
…..
default:default_statement;
endcase
Nand Gate using the Case Statement
module nand_case(a,b,c);
input a,b;
output c;
reg c;
always@(a or b)
Begin
Case ({a, b})
2’b00: begin
c=1’b1;
end
2’b01: begin
c=1’b1;
end
2’b10: begin
c=1’b1;
end
2’b11: begin
c=1’b0;
end
endcase
End
endmodule