Verilog Lecture 1 - Noopur
Verilog Lecture 1 - Noopur
of HDLs.
Designers can write their RTL (Register-transfer-
Veriwell etc.)
It support synthesis. It is the process of converting the
Identifiers are the names you give to your wires, gates, functions, and
anything else you design or use.
The basic rules for identifiers are as follows:
May contain letters (a-z, A-Z), digits (0-9), underscores (_), and dollar
signs ($).
Must start with a letter or underscore.
Are case sensitive (unless made case insensitive by a tool option).
May be up to 1024 characters long.
WHITE SPACE:
White space is the term used to describe the characters
and block.
Single-line comments are lines (or portions of lines)
represent a number.
Radix Specifiers
For Example:
8'b10100101
16'habcd
MODULES:
The main building block in Verilog is the module.
You can create modules using the keywords module
and endmodule.
You can write all your code inside these keywords.
Modules provide necessary information about input
………….
<List of Program>
……….
endmodule
Declaration of input and output
After declaration of module, next step is to define the
input and output ports.
Example: input a,b; //two input each of one bit
If input or output are more than one bits then we can
define as below
or z.
PRIMITIVES
Verilog has a set of twenty-six built-in primitives. These
primitives represent built-in gates and switches.
The primitives and, nand, or, nor, xor, and xnor represent
simple logic functions with one or more inputs and one
output.
Buffers, inverters, and three-state buffers/inverters are
represented by buf, not, bufif1, bufif0, notif1, and notif0.
MOS-level unidirectional and bidirectional switches are
represented by the remaining primitives.
List of Verilog Primitives
PORTS
Ports in Primitives
module and(a,b,c);
Input a,b;
Output c;
and m1(c,a,b);
endmodule
Ports in Modules
module and(a,b.c);
input a,b;
output c;
and m1(c,a,b);
endmodule
Options for port connections
When instantiating a module, the (actual) port names in the port list must be
in one-to-one correspondence with the module’s formal names. There are
two ways to make the association.
Table.
Some more Format Specifiers
$write
$write is similar to $display: They both print results
when encountered.
The only difference between the two is that $display
1. module two_display;
2. initial
3. begin
4. $display("first half ");
5. $display("second half");
6. end
7. endmodule
Results
first half
second half
Example2:Combining $write and $display
1. module write_display;
2. initial
3. begin
4. $write ("first half ");
5. $display("second half");
6. end
7. endmodule
Results