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Asm 1

The document provides an overview of assembler concepts and IBM mainframe architecture. It discusses the evolution of IBM System/360 and System/370 architectures. It also describes assembler documentation, the translation of assembler code, memory architecture including bytes, registers, addressing modes, instruction types, program status word, and the fetch/execute cycle.

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Asm 1

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Assembler Concepts

Copyright © 2016 by David Woolbright.

An Old, Durable Architecture
• System 360 (1964)
• System 370 (1971)
• 370 Extended Architecture –XA (1983)
• Enterprise Systems Architecture – ESA
(1989)
• ESA 390 (1990-1999)
• Z/Architecture (2000)
Assembler Documentation
• The two most important
assembler manuals are
– Principles of Operation -
describes how the machine
and each instruction works
– Language Reference –
describes how to use the
assembler directives
Documentation
• IBM documentation for the High-level
Assembler (HLASM) is available over the
web:
• Principles of Operations
– SA22-7832-10
http://publibfp.dhe.ibm.com/epubs/pdf/dz9zr010.pdf
• High Level Assembler Language Reference
– SC26-4940-07
http://publibfp.dhe.ibm.com/epubs/pdf/asmr1022.pdf
Translation of Assembler Code
Assembler
Source Object Load
HLASM Binder
Code Module Module

Listing
Object Mods
Ready for
execution
…
MVC X,Y …1100101011000111…
L R3,0(R0,R1)
CLC
NAMEI,NAMEO
…
Architecture - Memory
• Bit
– Binary Digit (1 or 0) Byte

• Byte 4 Bits 4 Bits

– Zone Portion – 4 Bits Zone Numeric
– Numeric Portion – 4 Bits

• Bytes are numbered (each byte has an

address) starting at 0 and getting larger

Address 0 1 2 3 4 …
• Bytes are the smallest storage unit with
an address
Architecture - Memory
• Halfword
– 2 Bytes
– Halfword boundary (Address evenly divisible by 2)
• Fullword
– 4 Bytes
– Word Boundary (Address evenly divisible by 4)
• Doubleword
– 8 Bytes
– Double Word boundary (Address evenly divisible by 8)
• Quadword
– 16 Bytes
– Quad Word boundary (Address evenly divisible by 16)
Architecture - Memory

Byte Byte Byte Byte Byte Byte Byte Byte

Halfword Halfword Halfword Halfword

Fullword Fullword

Doubleword
Terms that Describe Memory
Metric

1000 KB kilobyte
10002 MB megabyte
10003 GB gigabyte
10004 TB terabyte
10005 PB petabyte
10006 EB exabyte
10007 ZB zettabyte
10008 YB yottabyte
Terms that Describe Memory
IEC JEDEC

1024 = 210 KiB kibibyte KB kilobyte

10242= 220 MiB mebibyte MB megabyte
10243= 230 GiB gibibyte GB gigabyte
10244= 240 TiB tebibyte –
10245= 250 PiB pebibyte –
10246= 260 EiB exbibyte –
10247= 270 ZiB zebibyte –
10248= 230 YiB yobibyte –
Representing Memory
Binary Decimal Hex
• The contents of memory is often 0000 0 0
0001 1 1
displayed in hexadecimal (base 16)
0010 2 2
digits
0011 3 3
• 1 hex digit = 4 bits
0100 4 4
• 2 hex digits = 1 byte 0101 5 5
0110 6 6
Binary: 1 1 0 1 0 1 1 0 0111 7 7
1000 8 8
Hex: D6 1001 9 9
1010 10 A
1011 11 B
1100 12 C
1101 13 D
1110 14 E
1111 15 F
Architecture - Registers
• 16 General Purpose Registers
– 64 Bits in a Register GPR
– 8 Bytes in a Register Word Word
4 Bytes 4 Bytes
– 2 Fullwords in a Register
– Used for Binary Arithmetic 64 Bits

– Used for creating Addresses

– Numbered 0 – 15
– Rightmost word functions as a 32-bit register
64-Bit GP Registers
Bit 0 63

Bit 32{0} 63 {31}

• Bits in a register are numbered 0 to 63 moving

from left to right
• The rightmost 32 bits can function as a 32-bit
register. In this case, we number those bits 32-
63 or 0-31 depending on the context
• In both cases, the register number is the same
Addressing
• Addressing is the process of
specifying the location of a byte
in memory
• Addressing varies based on instruction type
– Base Register + Displacement
– Base Register + Index Register + Displacement
– Relative
Addressing
• Base/Displacement Scheme
– Makes Object code smaller
– Makes Linkage simpler
• A specific byte is indicated by specifying a
beginning address (base) and an offset
from the base (displacement)
• Base address contained in a General
Purpose Register
• Displacement specified in an instruction
Base/Displacement Addressing
64-bit GP Register Displacement
+

0 63 0 11

• The contents of the base register are added to the displacement

• The result is truncated on the left depending on the machine’s
current addressing mode
o In 24-bit mode, the leftmost 40 bits are set to zeros.
o In 31-bit mode, the leftmost 33 bits are set to zeros.
o In 64-bit mode, the 64-bit address is not truncated.
• Initially we will use 31 bit addressing
Addressing
In an assembled instruction, a
Base/Displacement address looks
Register 10 like 4 hex digits:
BDDD
1500 B = Base Register
DDD = Displacement (0 – 4095)
Memory

Base Displacement Address: In explicit notation an address

1505 looks like D(B) or
A005
D(X, B)
D is a displacement
Object Code
B is a base register
X is an index register
How a programmer codes it
Trimodal Addressing
• The machine supports three addressing modes
(24, 31, and 64)
• Each mode determines the number of bits used
to make up an address
• 24 bits address 224 = 24 x 220 = 16 MB
• 31 bits can address 231 = 21 x 230 = 2 GB
• 64 bits can address 264 = 24 x 260 = 16 EB
• 5 Exabytes: All words ever spoken by human
beings.
Modal vs Non-Modal
• A modal instruction is one that is affected
when you change addressing modes
• A non-modal instruction is one that is not
affected by changing addressing modes
Using 64-Bit GP Registers
Bit 0 63

Bit 32{0} 63 {31}

• You don’t have to be running in 64-bit

addressing mode to use a 64-bit register
• A program can change addressing modes
while it runs
In the First Course
• Registers are 32 bits (rightmost bits)
• We are always running in 31-bit
addressing
Instructions
• There are well over 1000 instructions on the
latest IBM System/z machine!
• Many have very specific uses
• Some instructions are “privileged” and require
special permission to execute
• We are studying “non-privileged” instructions
• We will target a rich working subset of
instructions
Instruction Types
• Instructions are categorized by type
• Types control the format of an instruction
• Learning about a type will help you learn
characteristics of every instruction of that type
• We concentrate on five types: RR, RX, RS, SS,
and SI
• There are many more types!
• Most instructions involve two operands
Location of Data
RR

RX RS

SS
Memory Memory

Instruction in
Memory
Architecture – Program Status
Word
• PSW is a logical collection of data that indicates the
current status of the machine
• Contains two important fields for programmers:
– Condition Code (2 bits)
– Instruction Address (24, 31, or 64 bit addresses)
Architecture – Condition Code
• Condition code (2 bits)
• 00 – equal
• 01 – low
• 10 – high
• 11 – overflow

• Test the condition code with Branch Instructions

CLC X,Y SET COND CODE
BE THERE TEST CC
…
THERE EQU *
Architecture – Instruction Address
• Contains the address of the “next”
instruction PSW Instruction Address
0000000000108A20

… …

Memory
Architecture – Instruction Address
Decode
PSW Instruction Address
0000000000108A20

… …

Memory
Architecture – Instruction Address
Update Instruction Address
PSW Instruction Address
0000000000108A24

… …

Memory
Architecture – Instruction Address
Executes Decoded Instruction
PSW Instruction Address
0000000000108A24

… …

Memory
Architecture – Instruction Address
Go Back to Step 1
PSW Instruction Address
0000000000108A24

… …

Memory
How does a computer work?
• Fetch/Execute Cycle
– 1) Fetch the next instruction
– 2) Decode the instruction
– 3) Update the Instruction address field
– 4) Execute the decoded instruction
– 5) Go to step 1
• How does branching work?
A Standard Line of Assembler
• Assembler statements are usually coded
on one line (80 characters)
• Longer statements can be continued
Columns 1 – 71 form a statement field 72 73 - 80

Column 72 – Continuation (any non-blank character)

Columns 73-80 – Identification sequence field – can be left blank
Column 16 – the continue column where continued lines start
EBCDIC Encoding
Character Hex Equivalent Character Hex Equivalent

A C1 S E2
B C2 T E3
C C3 U E4
D C4 V E5
E C5 W E6
F C6 X E7

G C7 Y E8
H C8 Z E9
I C9
J D1
K D2 BLANK 40
L D3 COMMA 6B
M D4 PERIOD 4B
N D5 ASTERISK 5C
O D6
P D7
Q D8
R D9
EBCDIC Encoding
Character Hex Equivalent
0 F0
1 F1
2 F2
3 F3
4 F4
5 F5
6 F6
7 F7
8 F8
9 F9
EBCDIC Encoding

"The herein described method of compiling statistics which consists in recording

separate statistical items pertaining to the individual by holes or combinations of
holed punched in sheets of electrically non-conducting material, and bearing a
specific relation to each other and to a standard, and then counting or tallying such
statistical items separately or in combination by means of mechanical counters
operated by electro-magnets the circuits through which are controlled by the
perforated sheets, substantially as and for the purpose set forth."
Defining Data and Data Areas
• Format for defining data
name DS rTLn
name DC rTLn’constant’
• r – repetition factor
• T – data type
• L – length
• n - integer
Character Data
• One character per byte
• EBCDIC representation (hex digits)
• Max DC size is 256
• Max DS size is 65,535
• Express constant as a character string in single
quotes
• Constants are left justified and padded with
blanks on the right or truncated on the right
• Symbols refer to the first byte of the field and
have a length attribute
Data Types - Character
X DC CL3’AB3’
Y DS CL2000
Z DS 0CL5
DS CL3
A DS CL2 R
P DC CL3’8’ C1 C2 C3
Q DC 2C’A’
R DC CL3’ABCD’

2000 F8 40 40 C1 C1
C1 C2 F3 bytes

X Y Z A P Q
Location Counter
• As statements are assembled, the
assembler keeps up with locations of
identifiers by maintaining a location
counter
LOC
00000000 W DS CL3
00000003 X DS CL4
00000007 Y DS CL8
0000000F Z DS CL4
00000013
Location Counter
• A zero duplication factor leaves the
location counter in the same position
LOC
00000000 W DS CL3
00000003 X DS CL4
00000007 NAME DS 0CL30
00000007 FNAME DS CL10
00000011 LNAME DS CL20
00000025 …
Location Counter
The location counter can be set with an
orginate (ORG) assembler directive
LOC
00000000 W DS CL3
00000003 X DS CL4
00000007 NAME DS CL30
00000025 ORG NAME
00000007 FNAME DS CL10
00000011 LNAME DS CL20
00000025 …
Building Reports with ORG
LOC
00001000 RPTLINE DC CL80’ ’
Resets LOC to
00001050 ORG RPTLINE+10 RPTLINE+20 = 1014
0000100A MON DC CL3’MON’
0000100D ORG RPTLINE+20
00001014 TUE DC CL3’TUE’
00001017 ORG RPTLINE+30 Comma indicates no
0000101E WED DC CL3’WED’ operand. Location counter
00001021 ORG RPTLINE+40 set to highest unassigned
00001028 THU DC CL3’THU’ location. A common error
is to use ORG and leave
0000102B ORG RPTLINE+50
the location counter in the
00001032 FRI DC CL3’FRI’ middle of assigned
00001035 ORG , storage
00001050 ...
Character Instructions - MVC
• Move Characters MVC X,Y
• SS1 MVC X(2),Y
• Op1 – target field … X DS CL3
• Op2 – source field Y DS CL3
• Length – associated with operand 1 only!
• Default Length taken from operand 1
• Fields may overlap
• Max 256 bytes are moved (copied)
SS1 Object Instruction Format
• Storage to Storage (SS1)
General Format:
OP LL1 B1D1 D1D1 B2D2 D2D2

• OP – Operation code
• LL1 – Length of Op One – 1 (Max 255)
• B1D1D1D1 – Base/Disp of Operand 1
• B2D2D2D2 – Base/Disp of Operand 2
Three ways to Code Instructions
• MVC FNAMEO,FNAMEI
Symbolic addresses
• MVC 4(3,12),8(12) Explicit addresses
• MVC X,4(8) Mixed addresses
• MVC 0(3,R4),4(R9) Explicit addresses
with equate symbols used for registers
R4 EQU 4
Explicit Instruction Format
• Storage to Storage (SS1)
Explicit Instruction format
OP D1(L1,B1),D2(B2)
• OP – Operation code
• D1, D2 – Displacement of operand 1 and 2
• B1, B2 – Base regs of operand 1 and 2
• L1 – Length of operand 1- ( 1- 256
decimal)
MVC EXAMPLE 1
X DC CL5’12345’
Y DC CL5’6789A’
Z DC CL3’BCD’

1 2 3 4 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 1
X DC CL5’12345’
Y DC CL5’6789A’
Z DC CL3’BCD’

6 2 3 4 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 1
X DC CL5’12345’
Y DC CL5’6789A’
Z DC CL3’BCD’

6 2 3 4 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 1
X DC CL5’12345’
Y DC CL5’6789A’
Z DC CL3’BCD’

6 7 3 4 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 1
X DC CL5’12345’
Y DC CL5’6789A’
Z DC CL3’BCD’

6 7 3 4 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 1
X DC CL5’12345’
Y DC CL5’6789A’
Z DC CL3’BCD’

6 7 8 4 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 1
X DC CL5’12345’
Y DC CL5’6789A’
Z DC CL3’BCD’

6 7 8 4 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 1
X DC CL5’12345’
Y DC CL5’6789A’
Z DC CL3’BCD’

6 7 8 9 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 1
X DC CL5’12345’
Y DC CL5’6789A’
Z DC CL3’BCD’

6 7 8 9 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 1
X DC CL5’12345’
Y DC CL5’6789A’
Z DC CL3’BCD’

6 7 8 9 A 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 2
X DC CL5’12345’
Y DC CL3’678’
Z DC CL5’9ABCD’

1 2 3 4 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 2
X DC CL5’12345’
Y DC CL3’678’
Z DC CL5’9ABCD’

6 2 3 4 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 2
X DC CL5’12345’
Y DC CL3’678’
Z DC CL5’9ABCD’

6 2 3 4 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 2
X DC CL5’12345’
Y DC CL3’678’
Z DC CL5’9ABCD’

6 7 3 4 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 2
X DC CL5’12345’
Y DC CL3’678’
Z DC CL5’9ABCD’

6 7 3 4 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 2
X DC CL5’12345’
Y DC CL3’678’
Z DC CL5’9ABCD’

6 7 8 4 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 2
X DC CL5’12345’
Y DC CL3’678’
Z DC CL5’9ABCD’

6 7 8 4 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 2
X DC CL5’12345’
Y DC CL3’678’
Z DC CL5’9ABCD’

6 7 8 9 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 2
X DC CL5’12345’
Y DC CL3’678’
Z DC CL5’9ABCD’

6 7 8 9 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 2
X DC CL5’12345’
Y DC CL3’678’
Z DC CL5’9ABCD’

6 7 8 9 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 3
X DC CL3’123’
Y DC CL5’45678’
Z DC CL5’9ABCD’

1 2 3 4 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 3
X DC CL3’123’
Y DC CL5’45678’
Z DC CL5’9ABCD’

4 2 3 4 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 3
X DC CL3’123’
Y DC CL5’45678’
Z DC CL5’9ABCD’

4 2 3 4 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 3
X DC CL3’123’
Y DC CL5’45678’
Z DC CL5’9ABCD’

4 5 3 4 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 3
X DC CL3’123’
Y DC CL5’45678’
Z DC CL5’9ABCD’

4 5 3 4 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 3
X DC CL3’123’
Y DC CL5’45678’
Z DC CL5’9ABCD’

4 5 6 4 5 6 7 8 9 A B C D

X Y Z

MVC X,Y
MVC EXAMPLE 4
X DC C’ ’
Y DC CL7’1234567’

1 2 3 4 5 6 7

X Y

MVC Y,X
MVC EXAMPLE 4
X DC C’ ’
Y DC CL7’1234567’

2 3 4 5 6 7

X Y

MVC Y,X
MVC EXAMPLE 4
X DC C’ ’
Y DC CL7’1234567’

2 3 4 5 6 7

X Y

MVC Y,X
MVC EXAMPLE 4
X DC C’ ’
Y DC CL7’1234567’

3 4 5 6 7

X Y

MVC Y,X
MVC EXAMPLE 4
X DC C’ ’
Y DC CL7’1234567’

3 4 5 6 7

X Y

MVC Y,X
MVC EXAMPLE 4
X DC C’ ’
Y DC CL7’1234567’

4 5 6 7

X Y

MVC Y,X
MVC EXAMPLE 4
X DC C’ ’
Y DC CL7’1234567’

4 5 6 7

X Y

MVC Y,X
MVC EXAMPLE 4
X DC C’ ’
Y DC CL7’1234567’

5 6 7

X Y

MVC Y,X
MVC EXAMPLE 4
X DC C’ ’
Y DC CL7’1234567’

5 6 7

X Y

MVC Y,X
MVC EXAMPLE 4
X DC C’ ’
Y DC CL7’1234567’

6 7

X Y

MVC Y,X
MVC EXAMPLE 4
X DC C’ ’
Y DC CL7’1234567’

6 7

X Y

MVC Y,X
MVC EXAMPLE 4
X DC C’ ’
Y DC CL7’1234567’

X Y

MVC Y,X
MVC EXAMPLE 4
X DC C’ ’
Y DC CL7’1234567’

X Y

MVC Y,X
MVC EXAMPLE 4
X DC C’ ’
Y DC CL7’1234567’

X Y

MVC Y,X
Character Instructions - MVC
X DC CL4’ABC’
Y DC CL5’12345’
MVC X,Y

A B C 1 2 3 4 5

X Y
Character Instructions - MVC
X DC CL4’ABC’
Y DC CL5’12345’
MVC X,Y

1 B C 1 2 3 4 5

X Y
Character Instructions - MVC
X DC CL4’ABC’
Y DC CL5’12345’
MVC X,Y

1 B C 1 2 3 4 5

X Y
Character Instructions - MVC
X DC CL4’ABC’
Y DC CL5’12345’
MVC X,Y

1 2 C 1 2 3 4 5

X Y
Character Instructions - MVC
X DC CL4’ABC’
Y DC CL5’12345’
MVC X,Y

1 2 C 1 2 3 4 5

X Y
Character Instructions - MVC
X DC CL4’ABC’
Y DC CL5’12345’
MVC X,Y

1 2 3 1 2 3 4 5

X Y
Character Instructions - MVC
X DC CL4’ABC’
Y DC CL5’12345’
MVC X,Y

1 2 3 1 2 3 4 5

X Y
Character Instructions - MVC
X DC CL4’ABC’
Y DC CL5’12345’
MVC X,Y

1 2 3 1 2 3 4 5

X Y
Character Instructions - MVC
X DC CL4’ABC’
Y DC CL5’12345’
MVC Y,X

A B C 1 2 3 4 5

X Y
Character Instructions - MVC
X DC CL4’ABC’
Y DC CL5’12345’
MVC Y,X

A B C A 2 3 4 5

X Y
Character Instructions - MVC
X DC CL4’ABC’
Y DC CL5’12345’
MVC Y,X

A B C A 2 3 4 5

X Y
Character Instructions - MVC
X DC CL4’ABC’
Y DC CL5’12345’
MVC Y,X

A B C A B 3 4 5

X Y
Character Instructions - MVC
X DC CL4’ABC’
Y DC CL5’12345’
MVC Y,X

A B C A B 3 4 5

X Y
Character Instructions - MVC
X DC CL4’ABC’
Y DC CL5’12345’
MVC Y,X

A B C A B C 4 5

X Y
Character Instructions - MVC
X DC CL4’ABC’
Y DC CL5’12345’
MVC Y,X

A B C A B C 4 5

X Y
Character Instructions - MVC
X DC CL4’ABC’
Y DC CL5’12345’
MVC Y,X

A B C A B C 5

X Y
Character Instructions - MVC
X DC CL4’ABC’
Y DC CL5’12345’
MVC Y,X

A B C A B C 5

X Y
Character Instructions - MVC
X DC CL4’ABC’
Y DC CL5’12345’
MVC Y,X

A B C A B C A

X Y
Character Instructions - MVC
X DC Cl7’ABC’
Y DC CL5’12345’

MVC X(3),Y explicit length

MVC X,X+1 relative address
MVC X,=C’XYZ’ Careful! why?
Blanking Out a Line
BLANK DC C’ ’
BUFFER DS CL133

MVC BUFFER,BLANK

MVC BUFFER,=CL133’ ’
Blanking Out a Line
BUFFER DS 0CL133
DS 133CL1’A’

MVI BUFFER,C’ ’
MVC BUFFER+1(L’BUFFER-1),BUFFER
A A A A … A A A

Buffer
Buffer+1
MVC Y,X
Blanking Out a Line
BUFFER DS 0CL133
DS 133CL1’A’

MVI BUFFER,C’ ’
MVC BUFFER+1(L’BUFFER-1),BUFFER
A A A … A A A

Buffer
Buffer+1
MVC Y,X
Blanking Out a Line
BUFFER DS 0CL133
DS 133CL1’A’

MVI BUFFER,C’ ’
MVC BUFFER+1(L’BUFFER-1),BUFFER
A A … A A A

Buffer
Buffer+1
MVC Y,X
Blanking Out a Line
BUFFER DS 0CL133
DS 133CL1’A’

MVI BUFFER,C’ ’
MVC BUFFER+1(L’BUFFER-1),BUFFER
A A … A A A

Buffer
Buffer+1
MVC Y,X
Blanking Out a Line
BUFFER DS 0CL133
DS 133CL1’A’

MVI BUFFER,C’ ’
MVC BUFFER+1(L’BUFFER-1),BUFFER
A … A A A

Buffer
Buffer+1
MVC Y,X
Blanking Out a Line
BUFFER DS 0CL133
DS 133CL1’A’

MVI BUFFER,C’ ’
MVC BUFFER+1(L’BUFFER-1),BUFFER
A … A A A

Buffer
Buffer+1
MVC Y,X
Blanking Out a Line
BUFFER DS 0CL133
DS 133CL1’A’

MVI BUFFER,C’ ’
MVC BUFFER+1(L’BUFFER-1),BUFFER
… A A A

Buffer
Buffer+1
MVC Y,X
Blanking Out a Line
BUFFER DS 0CL133
DS 133CL1’A’

MVI BUFFER,C’ ’
MVC BUFFER+1(L’BUFFER-1),BUFFER
… A A A

Buffer
Buffer+1
MVC Y,X
Blanking Out a Line
BUFFER DS 0CL133
DS 133CL1’A’

MVI BUFFER,C’ ’
MVC BUFFER+1(L’BUFFER-1),BUFFER
…

Buffer
Buffer+1
MVC Y,X
Character Instructions - CLC
• Compare Logical Characters
• SS1
• Sets the condition code to indicate how Op1
compares to Op2
• Length – associated with operand 1 only!
• Default Length is length of operand 1
• Bytes compared using EBCDIC encoding
• Bytes compared left to right
• Max 256 bytes are compared
• Test with BE, BL, BH, BNE, BNL, BNH
Character Instructions - CLC
X DC C’ABC’
Y DC C’1234567’
Z DC C’ABCD’
CLC X,Y cc = low
BE THERE no branch
CLC Y,X cc = high
BNE THERE branch taken
CLC X(2),Z cc = equal
BNE THERE no branch taken
CLC Z,X cc = low
BNH THERE branch taken
Character Instructions - CLI
• Compare Logical Immediate
• SI
• Constant resides inside the instruction
• Sets the condition code to indicate how
Op1 compares to Op2
• Implicit length of 1!
• Byte compared using EBCDIC encoding
• Test with BE, BL, BH, BNE, BNL, BNH
Object Instruction Formats
• Storage Immediate (SI)
General Object Format:

OP II2 B1D1 D1D1

• OP – Operation code
• II2 – Immediate Constant – Operand 2
• B1D1D1D1 – Base/Disp of Operand 1
Character Instructions - CLI
X DC Cl3’ABC’
Y DC CL7’1234567
Z DC C’ABCD’
CLI X,C’A’ cc = equal
CLI Y,C’A’ cc = high
CLI X,X’40’ cc = high
CLI Z,C’B’ cc = low
CLI Y,B’11110001’ cc = equal
CLI Y,C’1’ cc = equal
CLI Y,X’F1’ cc = equal
BL THERE
Character Instructions - MVI
• Move Immediate
• SI
• Constant resides inside the instruction
• Moves one byte to operand one
• Implicit length of 1!
Character Instructions - MVI
X DC CL5’ABC’
Y DC CL7’1234567’
Z DC C’ABCD’
MVI X,C’F’
MVI Y,C’A’
MVI X,X’40’
MVI Z,64
MVI Z,B’11110001’
Defining an Output File
**********************************************************
*
Column 72
* OUTPUT FILE - DATA CONTROL BLOCK

**********************************************************
FILEOUT DCB DSORG=PS, X
MACRF=(PM), X
DDNAME=FILEOUT, X
RECFM=FB, X
LRECL=80
DCB – Data Control Block – storage used to describe a file
DSORG=PS – Data Set Organization – Physical Sequential
MACRF=(PM) – Output File – Move the record from my program
to an output buffer
DDNAME=FILEOUT – Data Definition Name – JCL File Name
RECFM=FB – Record Format – Fixed Blocked
LRECL=80 – Logical Record Length in bytes
Defining an Input File
**********************************************************
*

* INPUT FILE - DATA CONTROL BLOCK

**********************************************************
FILEIN DCB DSORG=PS, X
MACRF=(GM), X
DDNAME=FILEIN, X
RECFM=FB, X
EODAD=FINAL X
LRECL=80
MACRF=(GM) Macro Format – Input file - Get a record,move
it to my program
RECFM=FB – Record Format – Fixed blocked
EODAD – End Of Data Address – where do we branch when we
try to read a record from an empty file?
LRECL – the number of bytes in a logical record
DCB (Data Control Block) Parms
• MACRF=(GM)
– Macro format – controls the type of macros that are used for file
– GM – input file, move mode
– GL – input file, locate mode
– PM – output file, move mode
– PL – output file, locate mode
– We will start with GM and PM since these are the easiest, but
GL and PL are the most efficient for files with large record sizes
and many records
• DDNAME= name
– The JCL DD name
DCB (Data Control Block) Parms
• DSORG=PS
– A Physical sequential file organization
• RECFM=(FB)
– The record format
– FB – fixed blocked
– FBA – fixed blocked with ANSI carriage control characters
– FBM – fixed blocked with IBM carriage control characterss
– VB – variable blocked
– F – fixed unblocked
– V – variable unblocked
• EODAD=label
– End of Data Address. Branch here when EOF.
• LRECL=length
– Logical Record Length. Take default on the blocksize – let the OS
choose.
Opening and Closing Files

OPEN (FILEIN,(INPUT)) THE INPUT FILE

OPEN (FILEOUT,(OUTPUT)) MY REPORT

... (process the files)

CLOSE FILEIN
CLOSE FILEOUT
Reading and Writing Records
* MOVE MODE IO
GET FILEIN,RECIN
MVC MESSAGEO,MESSAGEI
PUT FILEOUT,RECOUT

GET Record
MVC
RECIN
Record PUT

RECOUT
Standard Entry and Exit
SKELAD4 CSECT
* STANDARD ENTRY
STM R14,R12,12(R13) STANDARD ENTRY
BASR R12,R0
USING *,R12
ST R13,SAVE+4
LA R13,SAVE
L R13,SAVE+4
…
* STANDARD EXIT
LM R14,R12,12(R13)
LA R15,0
BR R14
Save Area (18F)
Used by Pl/I
Program A's Save Area Address
Program C's Save Area Address
Register 14
Register 15
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6 Program A
Register 7
Register 8 Program B
Register 9
Register 10 Program C
Register 11
Register 12
Exercise #1
• Read a sequential dataset in which each record contains a
single date in the following format:
YYYYMMDD (columns 1-8)
• You can assume valid data.
• Print Three records in the output file for each input record
• Reformat the date data in the following format:
Year: 2004
Month: January
Day: 23
• The numeric month should be converted to English. Don’t try
to be fancy here, just use brute force for the conversions – we
don’t know much assembler at this point – a string of
comparisons will work.
Exercise #1
Here is some sample data:
20161128
20160115
20160215
20160315
20160415
20160515
20160615
20160715
20160815
20160915
20161015
20162115
20162215
20160102
20160130
19441207
Object Instruction Formats
• Storage to Storage (SS2)
General Object Format:
OP L1L2 B1D1 D1D1 B2D2 D2D2
• OP – Operation code
• L1 – Length of Operand One - Max value 15
• L2 – Length of Operand Two - Max value 15
• B1D1D1D1 – Base/Disp of Operand 1
• B2D2D2D2 – Base/Disp of Operand 2
Object Instruction Formats
• Register to Register (RR)
General Object Format:

OP R1R2

• OP – Operation code
• R1 – Operand 1 register
• R2 – Operand 2 register
Object Instruction Formats
• Register to Indexed Storage (RX)
General Object Format:

OP R1X2 B2D2 D2D2

• OP – Operation code
• R1 – Operand 1 Register
• X2 – Operand 2 Register
• B2D2D2D2 – Base/Disp of Operand 2
Object Instruction Formats
• Register to Storage (RS)
General Object Format:

OP R1R3 B2D2 D2D2

• OP – Operation code
• R1 – Operand 1 Register
• R3 – Operand 3 Register or Mask
• B2D2D2D2 – Base/Disp of Operand 2
Explicit Instruction Format
• Storage to Storage (SS2)
Explicit Instruction format
OP D1(L1,B1),D2(L2,B2)
• OP – Operation code
• D1, D2 – Displacement of operand 1 and 2
• B1, B2 – Base regs of operand 1 and 2
• L1 – Length of operand 1 (Max 256)
• L2 – Length of operand 2 (Max 256)
Explicit Instruction Format
• Register to Register (RR)
Explicit Instruction format
OP R1, R2
• OP – Operation code
• R1 – Register for operand 1
• R2 – Register for operand 2
Explicit Instruction Format
• Storage Immediate (SI)
Explicit Instruction format
OP D1(B1),I2
• OP – Operation code
• D1 – Displacement for operand 1
• B1 – Base Register for operand 1
• I2 – Immediate Constant for operand 2
Explicit Instruction Format
• Register to Indexed Storage (RX)
Explicit Instruction format
OP R1,D2(X2,B2)
• OP – Operation code
• R1 – Register for operand 1
• D2 – Displacement for operand 2
• B2 – Base Register for operand 2
• X2 – Index Register for operand 2
Explicit Instruction Format
• Register to Storage (RS)
Explicit Instruction format
OP R1,R3,D2(B2)
• OP – Operation code
• R1 – Register for operand 1
• R3 – Register or mask for operand 3
• D2 – Displacement for operand 2
• B2 – Base Register for operand 2
Reading Explicit Instructions
MVC 3(4,5),6(7) SS1

AP 3(4,5),6(7,8) SS2

MVI 4(8),X’40’ SI

LR 5,12 RR

STM 14,12,12(13) RS

L 6,9(5,8) RX
Reading Mixed Instructions
X DS CL8
Y DS CL20

MVC X(3),6(7) SS1

MVC X(L’Y),Y SS1
AP X(3),Y(8) SS2
MVI X,X’40’ SI
LR R5,R12 RR
STM R14,R12,SAVE RS
L R6,X(8) RX
Packed Decimal Data
• Two decimal digits per byte
• Sign occurs in the numeric portion of the
rightmost byte
• Valid signs: A,C,F are +
B, D are -
• Preferred signs: C (+), D (-)
• XPK DC PL3’54’
• Generates: 00054C
Example Packed Data Fields
APK DC P’12345’ 12345C
BPK DC PL2’12345’ 345C
CPK DC PL4’123.45’ 0012345C
DPK DC P’-345’ 345D
EPK DC P’0’ 0C
FPK DC P’-1’ 1D
Zoned Decimal Data
• One decimal digit per byte
• Sign occurs in the zone portion of the rightmost byte
• Valid signs: A,C,F are +
B, D are -
• Preferred signs: C (+), D (-)
• XPK DC ZL5’-354’
Generates: F0F0F3F5D4
• Some character fields qualify as zoned:
• X DC C’12345’
Generates: F1F2F3F4F5
Example Zoned Data Fields
AZD DC Z’12345’ F1F2F3F4C5
BZD DC ZL2’-12345’ F4D5
CZD DC Z’-12345’ F1F2F3F4D5
DZD DC ZL4’-345’ F0F3F4D5
EZD DC Z’0’ C0
FZD DC Z’-1’ D1
GC DC C’12345’ F1F2F3F4F5
Object Instruction Formats
• Storage to Storage (SS2)
General Object Format:
OP L1L2 B1D1 D1D1 B2D2 D2D2
• OP – Operation code
• L1 – Length of Operand One - Max value 15
• L2 – Length of Operand Two - Max value 15
• B1D1D1D1 – Base/Disp of Operand 1
• B2D2D2D2 – Base/Disp of Operand 2
Packed Instructions - Pack
• SS2
• The PACK instruction converts from zoned
decimal to packed decimal
XZD DC Z’-1234’ F1F2F3D4
XPK DS PL4 0001234D
…
PACK XPK,XZD
Packed Instructions - Pack
XZD DC Z’-1234’ F1F2F3D4
XPK DS PL4 0001234D
…
PACK XPK,XZD

XZD F1 F2 F3 D4

XPK FF FF FF FF
Packed Instructions - Pack
XZD DC Z’-1234’ F1F2F3D4
XPK DS PL4 0001234D
…
PACK XPK,XZD

XZD F1 F2 F3 D4

XPK FF FF FF 4D
Packed Instructions - Pack
XZD DC Z’-1234’ F1F2F3D4
XPK DS PL4 0001234D
…
PACK XPK,XZD

XZD F1 F2 F3 D4

XPK FF FF 23 4D
Packed Instructions - Pack
XZD DC Z’-1234’ F1F2F3D4
XPK DS PL4 0001234D
…
PACK XPK,XZD

XZD F1 F2 F3 D4

XPK FF 01 23 4D
Packed Instructions - Pack
XZD DC Z’-1234’ F1F2F3D4
XPK DS PL4 0001234D
…
PACK XPK,XZD

XZD F1 F2 F3 D4

XPK 00 01 23 4D
Packed Instructions - Pack
• The receiving field can be too short
XZD DC Z’-12345’ F1F2F3F4D5
XPK DS PL2 345D
…
PACK XPK,XZD
• Any data can be packed – results not
always good
Packed Instructions - Pack
• The receiving field can be too short
XZD DC Z’-12345’ F1F2F3F4D5
XPK DS PL2 345D

XZD F1 F2 F3 F4 D5

XPK FF 5D
Packed Instructions - Pack
• The receiving field can be too short
XZD DC Z’-12345’ F1F2F3F4D5
XPK DS PL2 345D

XZD F1 F2 F3 F4 D5

XPK 34 5D
Packed Decimal Arithmetic Issues
• Each operand contains at most 16 bytes –
31 digits plus a sign
• Data Exceptions (S0C7) occur when
performing arithmetic on data that is not
packed
• Loss of precision can occur on ZAP, AP,
SP – no notification
Packed Arithmetic - ZAP
• SS2
• Use ZAP to move packed data (not MVC)

XPK DS PL4
YPK DC P’54’ 054C
ZAP XPK,YPK
MVC XPK,YPK WHY NOT?

• Final result in XPK: 0000054C

• Sets the condition code to Positive, Minus, or equal
• Test with BP, BM, BE, BNP, BNM, BNE
Packed Arithmetic - AP
• SS2 – Add packed
• Op1 – Target Field (max 16 bytes)
• Op2 – Source Field (max 16 bytes)
• The target contains the arithmetic sum of
Op1 and Op2
• Sets the condition code:
– High – result > 0 Test with BP, BNP
– Low – result < 0 Test with BM, BNM
– Equal – result = 0 Test with BZ, BNZ
Packed Arithmetic - SP
• SS2 – Subtract packed
• Op1 – Target Field (max 16 bytes)
• Op2 – Source Field (max 16 bytes)
• The target contains the arithmetic result of
subtracting Op2 from Op1
• Sets the condition code:
– High – result > 0 Test with BP, BNP
– Low – result < 0 Test with BM, BNM
– Equal – result = 0 Test with BZ, BNZ
Packed Arithmetic
X DS PL8
Y DC PL4’123’
ZAP X,Y
AP X,X
SP X,=P’1’
ZAP X,X
BP THERE
Packed Arithmetic - MP
• SS2 – Multiply packed
• Op1 – Target Field (max 16 bytes)
• Op2 – Source Field (max 8 bytes)
• The target contains the product of multiplying
Op1 by Op2
• Does not set the condition code
• Op1 contains the multiplicand (before) and then
the product (after)
• Op2 contains the multiplier
• The number of leading bytes of zeros in op1
before multiplying must be >= no of bytes in op2
Leaving Enough Room
WORK DS PL4
A DC PL3’12345’
B DS PL2

ZAP WORK,A
MP WORK,B ABENDS!
WORK: 0012345C
Packed Arithmetic
X DS PL8
Y DC PL4’20’
Z DC PL4’30
ZAP X,Y
MP X,Z

ZAP X,=PL5’123456789’
MP X,Y PROBLEM
Packed Arithmetic - DP
• SS2 – Divide packed
• Op1 – Target Field (max 16 bytes)
Dividend/Quotient/Remainder
• Op2 – Source Field (max 8 bytes) Divisor
• The target initially contains the dividend
• After dividing, target contains quotient and remainder
• Remainder size = divisor size
• Quotient size = Target field size – Remainder size
• Does not set the condition code
• The number of leading bytes of zeros in op1 before
dividing must be >= no of bytes in op2
Packed Arithmetic
X DS PL8 COMPUTE 125/30
Y DC PL5’125’
Z DC PL3’30
ZAP X,Y
DP X,Z

X Before divide: 000000000000125C

X After divide: 000000004C00005C
Quotient Remainder
Example Division
Divide X by Y Giving QUOT Remainder REM
X DS PL5
Y DS PL3
WORK DS 0PL8
QUOT DS PL5
REM DS PL3
ZAP WORK,X
DP WORK,Y
Packed Arithmetic - CP
• SS2 – Compare packed
• Op1 – Target Field (max 16 bytes)
• Op2 – Source Field (max 16 bytes)
• Sets the condition code to indicate how
Op1 compares with Op2
• Numbers are compared arithmetically (not
a character compare with EBCDIC)
• Fields can be different sizes
Packed Arithmetic
X DC PL8’-30’
Y DC PL5’125’
Z DC PL3’30’
CP X,Y CC = LOW
CP Y,X CC = HIGH
CP Y,=P’125’ CC = EQUAL
CP Z,=X’030F’ CC = EQUAL
CP Example With
Extended Mnemonic
ZAP XPK,=P’0’
THERE EQU *
AP XPK,=P’1’
CP XPK,=P’10’
BNE THERE
…
XPK DS PL3
CP Example With
Branch on Condition
ZAP XPK,=P’0’
THERE EQU *
AP XPK,=P’1’
CP XPK,=P’10’
BC 7,THERE
…
XPK DS PL3
Some Extended Mnemonics
Each condition is represented with 4 bits

Equal Low High Overflow Condition

Zero Minus Plus
0 0 1 0 = 2 BH,BP
1 0 0 0 = 8 BE,BZ
0 1 1 1 = 7 BNE,BNZ
1 1 1 1 = F B
Packed Arithmetic - SRP
• SS – Shift and Round Packed
• Used to shift packed fields to the left or right in order to
compute decimal precision
• Op1 – Target Field (max 16 bytes)
• Op2 – A shift factor
– Positive shift factor 1-31 – left shift
– Negative shift factor in 2’s complement – right shift
– Express negative shift factor as 64 – n for n digit shift right
• Op3 – Rounding factor – (0-9)
– 0 – no rounding
– 5 – standard rounding
• Don’t shift a significant digit off the left
SRP Examples
SRP X,3,0 shift 3 digits left, no rounding
SRP X,5,0 shift 5 digits left, no rounding
SRP X,64-1,5 shift 1 right, round on 5
SRP X,64-3,5 shift 3 right, round on 5
SRP X,64-5,0 shift 5 right, no rounding

64-3 = 61 Decimal = B’111101’ plain binary

000011 = +3
111100 = complement
+1
111101 = 2’s complement = -3
111101 = 63 in decimal
SRP Details
• Can shift up to 31 digits to the left, 32
digits to the right
• Shifting a non-zero digit off the left causes
an overflow
• A decimal overflow exception occurs if the
decimal overflow mask is 1, otherwise you
can test for overflow with BO, BNO
• SPM can be used to control the mask bit
Packed Arithmetic
X DC P’-98765’
Y DC PL5’98765’
SRP X,64-3,5 X = 00099D

SRP Y,3,0 X = 098765000C

SRP Y,64-1,0 X = 000009876C

SRP X,1,0 ERROR or OVERFLOW

Shift Computations
X DS PL4 2 DECIMALS
Y DS PL4 3 DECIMALS
WORK DS PL10

Compute X + Y to 2 decimals rounded

ZAP WORK,X
SRP WORK,1,0
AP WORK,Y
SRP WORK,64-1,5
Shift Computations
X DS PL4 2 DECIMALS
Y DS PL4 3 DECIMALS
WORK DS PL10
Compute X / Y to 2 decimals rounded

9999v999 99999v990000

ZAP WORK,X
SRP WORK,4,0
DP WORK,Y
SRP QUOT,64-1,5
Shift Computations
X DS PL4 4 DECIMALS
WORK DS PL8
COUNT DS P’9’

Compute X10 TO 4 decimals rounded

ZAP WORK,X
LOOP EQU *
MP WORK,X
SRP WORK,64-4,5
SP COUNT,=P’1’
BNZ LOOP
Converting from Packed to Numeric
Edited Data
• Packed instruction - ED
• SS2
• Edit Pattern describes the output
– X’40’ blank, fill pattern
– X’20’ digit selector
– X’21’ digit selector and significance starter
– X’6B’ comma
– X’4B’ decimal point
Edit Patterns
• An edit pattern is defined in hex and is
called the edit “word”
• Packed field must match the edit “word”
• X’402020202120’ 5 digits
• X’4020202021204B2020’ 7 digits
• X’40202020’ 3 digits
Editing
• Create an edit word in memory that matches the
packed field
XWORD DC X’40202120’
XPK DS PL2
• Move the edit word to the output area (must
match the edit word)
XOUT DS CL4
MVC XOUT,XWORD
• Edit the packed field into the output area
ED XOUT,XPK
Internal Subroutines
BAS R7,SUB
…
BAS R7,SUB
…
SUB EQU *
___
___
___
BR R7
Practice Exercise #2
Greatest Common Divisor Computation for A and B
1. Let rem = remainder of dividing the larger number by
the smaller number
2. Replace the larger number with rem
3. Stop if A or B = 0, print A + B. Otherwise go to step 1
Example A B
84 24
12 24
12 0 GCD = 12 + 0 = 12
Practice Exercise #2
• Create a file of records with two integers
per record stored in a character format in
columns 1-8
• Print each integer and the gcd. Print one
record for each record in the input file
Practice Exercise #3
• Read a file that contains 3 5-byte fields in
character format (cols 1-5,6-10, 11-15)
• Call the three fields A, B, C
• Assume A has 2 decimals, B has 3, and C has 4
• For each record in the file, print a record on a
report
• Print A, B, C, A+B, (A+B)/C
• All answers should be good to one decimal
rounded
• Don’t divide by 0
Binary Data
• Binary data is stored in 2’s complement
format for signed arithmetic
• Binary data usually occurs as halfwords,
fullwords, and doublewords
• Data can be defined as binary
• Data can be converted to binary from
packed
• Some data is binary by nature (addresses)
You might need one of these
Defining Binary Data
A DC F’1’ 00000001
B DC H’-30’ FFE2
C DC D’50’ 0000000000000032
D DC B’10100000’ A0
E DC A(B) ????????
F DC X’0040’ 0040
Converting Between Types

Binary Data

CVB CVD

Packed Data

ED
PACK UNPK

Zoned Decimal Data Numeric Edited Data

Convert to Binary
• CVB
• RX
• Operand 1 – Register – target
• Operand 2 – Doubleword in memory – contains
packed data
• Packed data is converted to binary and placed in
the register
• Some doubleword values will not fit in a register
-2,147,483,648 -- +2,147,483,647
• Fixed point divide exception if conversion value
out of range
Convert To Binary (CVB)

BEFORE R8 AFTER R8
FF FF FF FF 00 00 00 78

DBLWD DS D

00 00 00 00 00 00 12 0c CVB R8,DBLWD

Eight byte staging area

CVB Example
XPK DC P’70’
DBLWD DS D
ZAP DBLDW,XPK
CVB R8,DBLWD

REG 8 = 00000046
Convert to Decimal
• CVD
• RX
• Operand 1 – Register - Source
• Operand 2 – Target is a Doubleword in
memory – contains packed data afterward
• Binary data is converted to packed and
placed in the doubleword
Convert To Decimal (CVD)

R8 CVD R8,DBLWD

FF FF FF FF

DBLWD DS D DBLWD DS D

00 00 00 00 00 00 12 0c 00 00 00 00 00 00 00 1d

Eight byte staging area (before) Eight byte staging area (after)
CVD Example
ASSUME R9 = 00000032
DBLWD DS D
XPK DS PL3
CVD R9,DBLWD
ZAP XPK,DBLWD

XPK = 00050C
Load Fullword
• RX
• L – Loads a binary fullword from memory into a register
• Op 1 – a Register
• Op 2 – a fullword in memory
Register
X DC F’20’

LOAD
L R8,X

Memory
Load Register
• RR
• LR – Load Register
• Copies the contents of Op-2 into Op-1
• Op-1 – a target register
• Op-2 – a source register
Load Register Example
LR R3,R7

R3 (Before) R7 (Before)

00 00 11 22 44 33 22 11

R3 (After) R7 (After)

44 33 22 11 44 33 22 11
Load and Test Register
• RR
• Identical to LR but also sets the condition
code to indicate how Op1 (final value)
compares to zero
• Op-1 – a target register
• Op-2 – a source register
Load and Test Register Example

LTR R7,R7
R7 (Before) CC = 00 EQUAL

R7 (After) CC = 01 LOW

FF FF FF FF FF FF FF FF
Load Halfword
• RX
• LH – Loads a binary fullword into a
register from a halfword in memory
• The halfword sign is propagated to fill the
leftmost bytes of the register
• Op 1 – a Register
• Op 2 – a halfword in memory
LH

R8 (Before)
00 00 FF FF LH R8,X

9A 23 MEMORY …

X DS H
LH

R8 (Before Sign Propagation)

00 00 9A 23 LH R8,X

9A 23 MEMORY …

X DS H
LH

R8 (After)
FF FF 9A 23 LH R8,X

Sign

9A 23 MEMORY …

X DS H
Store Fullword
• RX
• ST – Copies the contents of a register into a binary
fullword in memory
• Op 1 – a Register
• Op 2 – a fullword in memory
Register

Y DS F

STORE
ST R4,Y
Memory
Store Fullword Example
ST R3,X

R3
00 00 00 00

12 12 12 12

X DS F (Before)
Store Fullword Example
ST R3,X

R3
00 00 00 00

00 00 00 00

X DS F (After)
Store Halfword
• RX
• ST – Copies the contents (two rightmost bytes) of a
register into a binary halfword in memory
• Op 1 – a Register
• Op 2 – a halfword in memory
Register

Y DS H

STORE
STH R4,Y
Memory
Store Halfword Example
STH R3,X

R3
12 34 56 78

00 00

X DS H (Before)
Store Halfword Example
STH R3,X

R3
12 34 56 78

56 78

X DS H (After)
Putting Zoned Data in a Register

XZONED DS ZL5
XPK DS PL3
DBLWD DS D

PACK XPK,XZONED
ZAP DBLWD,XPK
CVB R7,DBLWD
Putting Packed Data in a Register

XPK DS PL3
DBLWD DS D

ZAP DBLWD,XPK
CVB R7,DBLWD
Putting Binary Data in a Register

XFULL DC F’-22’
XHALF DC H’32’

L R8,XFULL R8 = FFFFFFEA
LH R9,XHALF R9 = 00000020
RX and RR Instructions
Fullword Halfword Register
L LH LR
ST STH ---
A AH AR
S SH SR
C CH CR
M MH MR
D --- DR
Add, Subtract, Compare Fullword
• RX
• A - Add Fullword
• S - Subtract Fullword
• C - Compare Fullword
• Operand 1 – Target Register
• Operand 2 – Fullword in memory (source)
• The fullword is added to, or subtracted from, the
contents of the register
• For COMPARE, the contents are arithmetically
compared
Add and Subtract Fullword,
Halfword
W DS F
X DS H
Y DS F
Z DS F
L R8,W
AH R8,X
S R8,Y
ST R8,Z
Multiply Fullword
Even Odd
Register Register

X DS F
Before:
Uninitialized Multiplicand Y DS F
Z DS F
L R9,X
M R8,Y
ST R9,Z
After: Product Product
Divide Fullword
Even Odd
Register Register

X DS F
Before: Dividend Dividend
Y DS F
Left Right
Z DS F
L R8,X
SRDA R8,32
D R8,Y
After: Remainder Quotient ST R9,Z
Add, Subtract, Compare Halfword
• RX
• AH - Add Halfword
• SH - Subtract Halfword
• CH - Compare Halfword
• Operand 1 – Target Register
• Operand 2 – The halfword is internally and
temporarily sign-extended to a Fullword
• The Fullword is added to, or subtracted from, or
compared to the contents of the register
• For COMPARE, the contents are arithmetically
compared
Multiply Halfword
Register 7

X DS F
Before: Y DS H
Multiplicand
Z DS F
L R7,X
MH R7,Y
ST R7,Z
After: Product
Add and Subtract Register
• RR
• AR – Add Register
• SR – Subtract Register
• Op-1 – Target Register
• Op-2 – Source Register

X DS F
Y DS F
L R8,X
L R9,Y
AR R8,R9
Multiply Register
Even Odd
Register Register

X DS F
Before:
Uninitialized Multiplicand Y DS F
Z DS F
L R9,X
L R5,Y
MR R8,R5
After: Product Product ST R9,Z
Divide Register
Even Odd
Register Register

X DS F
Before: Dividend Dividend
Y DS F
Left Right
Z DS F
L R8,X
L R4,Y
SRDA R8,32
After: Remainder Quotient DR R8,R4
ST R9,Z
Alignment
• Doubleword, Fullword and Halfword
alignment can be provided to a field:
DS 0D Doubleword alignment
X DS ….
DS 0F Fullword alignment
Y DS ….
DS 0H Halfword alignment
Z DS ….
Alignment
• Forced alignment can be prevented by
coding a length for halfwords, fullwords
and doublewords:
DS 0F
X DS CL1
Y DS FL4
Z DS HL2
Practice Exercise 4
• Create a file of records
• Each record contains three integers
• Field A – columns 1-5 - zoned
• Field B – columns 6-7 – packed
• Field C – columns 8-11 – fullword
• Align the first byte of the record on a doubleword
• Print A, B, C, A+B, (A * B)/ C
• Do all the work as plain integer arithmetic in the
registers
Load Address
• RX
• LA - Load address
• Op1 – the target register
• Op2 – a fullword in memory. The address
of the memory location is copied into the
register
Load and Load Address

L R8,X
LA R9,X
After: R8 – 00003287
After R9 - 12FC0010

QSAM Locate Mode I/O
User Region
FILEIN User Program FILEOUT

USING INDSECT,R4
USING OUTDSECT,R5
OPEN FILEIN,(INPUT)
OPEN FILEOUT,(OUTPUT)
GET FILEIN
LR R4,R1
PUT FILEOUT
LR R5,R1
MVC RECOUT,RECIN
CLOSE FILEIN
INDSECT DSECT CLOSE FILEOUT
RECIN DS 0CLL80
NAMEI DS CL20
ADDR1 DS CL30
…

OUTDSECT DSECT
RECOUT DS 0CL80
NAMEO DS CL20

FILEIN DCB …
MACRF=(GL),