Digital Logic

Lecture 10

Combinational Logic: Decoders,

Encoders, and Multiplexers

The Hashemite University

Computer Engineering Department
Outline
 Introduction.
 Decoders.
 Encoders.
 Multiplexers.

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Introduction
 In this lecture we will complete viewing
the standard combinational circuits.
 Specifically, we will study:
 Decoders.
 Encoders.
 Multiplexers.

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 Decoders I
 Decoder is a combinational circuit that
converts a binary value to a specific binary
code  one to one mapping.
 Remember that an n-bit binary code can
represents up to a 2n binary codes.
 So, a decoder has the binary code as an input
and the original binary value as the output.
 For an n-bit binary code, the decoder has n
inputs and a maximum 2n outputs (may have
fewer outputs if you have unused codes as in
BCD).

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Decoders II
 We will study the n-to-m-line decoders where m <= 2n where it
simply generate the 2n minterms of the n input variables.
 Two types of decoders:
 Decoders without enable lines.
 Decoders with enable lines.
 Each type of these decoders can also be classified into:
 Active low decoders.
 Active high decoders.
 We will take an example the 3-to-8 line decoder (see the next
slide).
 You can design any decoder (2-to-4, etc) just truncate the
unwanted minterms.
 Remember that decoder term can be used to denote any binary
code converters in general.

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3-8 Active High decoder

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 Decoders III
 Truth table of 3-to-8 line decoder

X Y Z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

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Decoders II

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3-8 Active Low decoder

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Active low Decoders

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 Types of decoders

E E
Active high decoder Active high with enable Active low decoder Active low with enable
decoder decoder

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 Implementing boolean functions
using decoder
1- choose suitable size decoder
# of decoder inputs = # of function variables

2- You can use active high or active low decoder to implement

the function as SOP or POS.

a- For SOP implementation

If you are using Active High decoder  Connect minterms to OR gate
If you are using Active Low decoder  Connect minterms to NAND gate

b- For POS implementation

If you are using Active High decoder  Connect maxterms to NOR gate
If you are using Active Low decoder  Connect maxterms to AND gate

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Constructing large decoder from
smaller decoders

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Decoders IV
 A particular application of 3-to-8 line decoder
is binary-to-octal conversion.
 That is based on the 3-bit binary value you
get which octal digit represented by this
value.
 For example if the input is 111 convert it to
octal you get digit 7, the output of the
decoder will have a 1 (active) at D7 which
represent digit 7 in octal.
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Active Low Decoders
 Constructed with NAND gates.
 The selected minterm based on the input (i.e.
the active one) will have a 0 on its output line
and other unselected minterms will have 1
(the inactive state for active low output line).
 How to differentiate between active low and
active high decoders from its block diagram?
 Bubbles on the output lines  active low decoder.
 No bubbles on the output lines  active high
decoder.

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 Decoders with Enable Line I
 The following is a general design
or block diagram of binary
decoder.
 The “Enable” lines enables the
decoder to perform mapping.
 The “Enable” depends on
whether it is active low (have a
bubble in front of the line) or
active high (have no bubble in
front of the line or pin).
 Active low enable must have an
input of 0 to activate the
decoder.
 Active high enable must be
asserted (has value of 1) to
activate the decoder.
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Decoders with Enable Line II
 Some decoders may have more than 1 enable
line where each line can be different from the
other (i.e. whether it is active high or active
low).
 The state of the decoder it self (whether it is
active low or active high) is independent of
the enable line state.
 So, you may have an active low decoder with
active high enable line.
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Decoders with Enable Line III
 If a decoder is not enabled (not activated)
this means that the minterm selected by the
inputs is not activated and no specific output
is selected.
 The inactive state depends on the type of the
decoder:
 Active low decoder  all outputs will be high (at
level 1) when disabled (the enable line is not
activated).
 Active high decoder  all outputs will be low (at
level 0) when disabled (the enable line is not
activated).
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Active Low 2-to-4 Line
Decoder With Enable Line

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 Building Bigger Decoders from
Small Ones
 We can combine two 3-to-8 decoders to build a 4-to-16 decoder
(in this figure w is the MSB and z is the LSB).

Generates from
0000 to 0111

Generates from
1000 to 1111

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 Combinational Logic Implementation
Using Line Decoders I
 Decoders can be used to implement logic
functions with the condition that these functions
must be represented as a sum of minterms.
 The minterms in the function are combined
using an OR gate or NAND gate based on the
decoder type.
 Two cases:
 Active high decoders: combine these minterms with
OR gate.
 Active low decoders: combine these minterms with
NAND gate.
 Note that NAND-NAND is equivalent to AND-OR
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Combinational Logic Implementation
Using Line Decoders II
 What to do with functions that have a long
list of minterms (larger than 2n/2)?
 Active high decoder:
 Simply get the minterms in F’ and combine them with a
NOR gate.
 The output of the NOR gate is F.
 Active low decoder:
 Simply get the minterms in F’ and combine them with a
AND gate.
 The output of the AND gate is F.

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Example
 Design a full adder using OR gates and
3x8 active high decoder.
 Sol:
 From the truth table of full adder, the
sum-of-minterms representation of S
and C are:
S(x,y,z) = Σ(1,2,4,7)
C(x,y,z) = Σ (3,5,6,7)
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Example -- Solution

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Notes
 If you are given F(x, y, z) = xy’ + z, how you
can implement it using an active high decoder
and an OR gate?
 First you must define the minterms in F. the
simplest way is obtain the truth table of F and see
at which minterms it has value of 1.
 The previous note is applied for any
representation of F other than sum of
minterms.

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Encoders
 Encoders perform the inverse operation of a decoder.
 An encoder has 2n (or fewer) input lines and n output
lines.
 The output lines generate the binary code
corresponding to the input value.
 Two types of encoders:
 Encoders with mutually exclusive inputs: only one input is
active at a time.
 Priority encoders: multiple inputs can be active at the same
time.
 Example of encoders with mutually exclusive inputs is
octal to binary encoders (8-to-3 line encoder).

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Encoders vs. Decoders

Decoder Encoder

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 Octal-to-Binary Encoder
Design I
 Truth Table
D0 D1 D2 D3 D4 D5 D6 D7 X Y Z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

 Note that we need not to complete the whole table where we

have listed only 8 entries equal to the number of inputs (not 2^8
entries) since only 1 input is allowed to be active at a time.
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Octal-to-Binary Encoder
Design II
 From the truth table we can see that the
outputs of the encoders are based on ORing
the minterms found in the inputs:
 z=D1+D3+D5+D7
 y=D2+D3+D6+D7
 x=D4+D5+D6+D7
 So, the internal implementation of octal-to-
binary encoder is composed of 3 OR gates.

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 2n-to-n Encoder Design
Limitations
 This encoder has many limitations:
 Only one input can be active at a time, otherwise it
will produce undefined combination which do not
correspond to either of the activated inputs (based
on the OR expressions).
 Solution: give higher priority to inputs with higher
subscripts, e.g. D5 has higher priority than D2 and so on.
So, when both D5 and D1 for example are active the
outputs will be 101 since D5 has higher priority.
 Note that when all inputs are 0 the output will be
000 which is the same output when only D0 is
active.
 Solution: provide an additional output to indicate whether
at least there is one input is 1.
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Priority Encoder
 Priority encoder is an encoder that
solves the limitations of 2n-to-n encoder
discussed previously (include priority
and an additional output which is called
the valid bit (V) to indicate that at least
one input is 1).
 We will design a 4-to-2 priority encoder.

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Priority Encoder Design I
 Truth table:
Inputs Outputs
D0 D1 D2 D3 x y v
0 0 0 0 X X 0
1 0 0 0 0 0 1
X 1 0 0 0 1 1
X X 1 0 1 0 1
X X X 1 1 1 1

 Note that we have inserted the don’t care conditions in the

input side just to avoid the need to list all 16 entries in the
truth table (not to be used in simplification as the don’t
care found in the output).
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Priority Encoder Design II

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Priority Encoder Design III

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 Applications of Priority Encoders
 Inputs indicates a request for service. e.g., Interrupt
requests.
 if multiple requests are made simultaneously, the encoder
gives undesirable results.
 The solution is to assign priority to the input lines, priority
encoder.

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 Multiplexers I
 Multiplexer is a combinational circuit that selects one of
the inputs and directs it to a single output line.
 It is abbreviated as a MUX.
 It is also called data selector and a digital switch.
 The operation performed by a MUX is called election.
 The selection of the inputs is controlled by a selection
lines or inputs.
 In general a MUX has 2n inputs, n selection lines (implied
from the inputs so they are not counted with the inputs),
and exactly 1 output.

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Multiplexers II
 Each input of the multiplexer is 1-bit only.
 The internal implementation of the MUX is an
AND-OR circuit.
 Each input is fed into one AND gate in
addition to one input from each selection line.
 The selection lines are very similar to the
enable line in the decoder. If their values are
1 then the AND gate is enabled, otherwise
the AND gate is disabled so the input has no
effect on the output.

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Multiplexers III
 A multiplexer is named as follows:
(number of inputs)-to-(number of
outputs) MUX or simply (number of
inputs)X(number of outputs) MUX.
 For example: you may have a 2X1 MUX,
4X1 MUX, 8X1 MUX and so on.

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2X1 MUX Design I

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2X1 MUX Design I
 Boolean expression of the MUX output
is:
Y = I0S’ + I1S
 Note that which input that will be
passed to the output (selected)
depends on the value of S which is the
selection line here.

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4X1 MUX Design I

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4X1 MUX Design II
 Boolean expression of the MUX output
is:
Y = I0S1’S0’ + I0S1’S0 + I0S1S0’ + I0S1S0
 Note that which input that will be
passed to the output (selected)
depends on the product value of S0 and
S1 which are the selection lines here.

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Note
 MUXs can have also enable line(s).
 Similar to the decoder the enable line
will be fed into all AND gates in the
MUX.
 The enable line can be active high or
active low.

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Note
 MUXs can have also enable line(s).
 Similar to the decoder the enable line
will be fed into all AND gates in the
MUX.
 The enable line can be active high or
active low.

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Note
 MUXs can have also enable line(s).
 Similar to the decoder the enable line
will be fed into all AND gates in the
MUX.
 The enable line can be active high or
active low.

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m-bit MUX I
 Multiplexers can be combined with common selection
inputs to support multi-bit selection logic.
 Remember that a MUX selects between 2n 1-bit
inputs. But what about if you want to select between
2n m-bit numbers (where m is the number of bits in
each input)?
 As we done before, if you want to build for example a 2X1
MUX with 4-bit inputs, you have m MUXs (equal to the
number of bits in the numbers) and you work on the bit
level.
 In this example if you have two inputs A, and B you want to
select either A or B and see it on the output which is
Y3Y2Y1Y0.
 It is called quadruple MUX.

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m-bit MUX II

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m-bit MUX II
 E is the enable line, and here it is active low,
that is if E = 0 then the quadruple MUX
works, if E =1 the MUX is disabled and no
output is available.
 Remember that the basic block is a 2X1 MUX,
that it selects between two inputs so it has
one selection line.
 Is S = 0 then the output = A, and if S = 1
then the output of the MUX = B.
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Boolean Functions Implementation
Using Multiplexers I
 We have used a decoder with OR gate to implement
Boolean functions.
 Active high decoder contains all the minterms
represented by AND gates inside it.
 Have a deep look at the internal design of a MUX you
will find that a 2nX1 MUX is simply a nX2n decoder
with OR gate.
 So, you can use a MUX to implement any Boolean
function since all the needed minterms are available
without the need to OR gate since it is already found.
 The only difference that now you apply the inputs of
the Boolean function to the selection lines of the
MUX in the proper way.
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Boolean Functions Implementation
Using Multiplexers II
 To implement a Boolean function with n
inputs you have two options:
 Either to use a 2nX1 MUX where you have
n selection lines.
 Or to use a 2n-1X1 MUX where you have n-1
selection lines.

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Boolean Functions Implementation
Using Multiplexers III
 General rules for implementing any Boolean
function with n variables using 2nX1 MUX:
 Use a multiplexer with n selection lines and 2n
data inputs.
 List the truth table of F.
 Apply the n variables to the selection inputs of
multiplexer with the same significance order.
 For each data input (which is a minterm) place a 1
if F has an output of 1 for this minterm and 0 if F
has an output of 0 for this minterm.

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Example
 On board

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Boolean Functions Implementation
Using Multiplexers IV
 General rules for implementing any Boolean
function with n variables using 2n-1X1 MUX:
 Use a multiplexer with n-1 selection inputs and 2 n-
1
data inputs
 List the truth table of F.
 Apply the first n-1 variables to the selection inputs
of multiplexer with the same significance order.
 For each combination of the selection variables
evaluate the output as a function of the last
variable.
 The function can be 0, 1 the variable or the
complement of the variable.

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Example I

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Example II

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Additional Notes
 This lecture covers the following
material from the textbook:
 Chapter 4: Sections 4.9, 4.10 and 4.11

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EX. Analyze the following
combinational circuit

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